The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like interrupt priority, direct memory access (DMA), input/output processors, and serial communication.

1. UNIT-4
Asynchronous Data Transfer, Modes Of Transfer, Priority Interrupt,
DMA, Input-Output Processor (IOP), CPU-IOP Communication,
Serial communication

2. • Peripheral Devices
• Input-Output Interface
• Asynchronous Data Transfer
• Modes of Transfer
• Priority Interrupt
• Direct Memory Access
• Input-Output Processor
• Serial Communication
INPUT-OUTPUT ORGANIZATION

3. Peripheral Devices
 The input output subsystem of a computer,
referred to as I/O, provides an efficient mode of
communication between the central system and
the outside environment.
 Input output devices attached to the computer
are called as peripherals.
 Among the common peripheral are keyboards,
mouse, display units, and printers etc.
 Peripherals that provide auxiliary storage for the
systems are magnetic disks and tapes.
 Peripherals are electromechanical and
electromagnetic devices.

4. Peripheral Devices
 Devices that are under the direct control of the
computer are said to be connected on-line.
 These devices are designed to read information into
or out of the memory unit upon command from the
CPU and are considered to be part of the total
computer system.
 The data transfer rate of peripheral devices differ
from each other.
 Each peripheral behaves differently from any other.
 The input-output organization of a computer is a
function of the size of the computer and the devices
connected to it.

5. Peripheral Devices
ASCII Alphanumeric Characters: I/O
Devices that communicate with people
and the computer are usually involved in
the transfer of alphanumeric information to
and from the device and the computer.
The standard binary code for the
alphanumeric characters is ASCII
(American Standard Code for Information
Interchange).

6. American Standard Code for Information Interchange
b4 b3 b2 b1
0 0 0 0
0 0 0 1
0 0 1 0
.
.
.
.
.
.
.
.
.
.
.
.
1 1 1 0
1 1 1 1
b7 b6 b5
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

7. PERIPHERAL DEVICES
Input Devices
• Keyboard
• Optical input devices
- Card Reader
- Paper Tape Reader
- Bar code reader
- Digitizer
- Optical Mark Reader
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices
Output Devices
• Card Puncher, Paper Tape Puncher
• CRT
• Printer (Impact, Ink Jet,
Laser, Dot Matrix)
• Plotter
• Analog
• Voice
Peripheral Devices

8. INPUT/OUTPUT INTERFACE
Provides a method for transferring
information between internal storage
(such as memory and CPU registers)
and external I/O devices.
I/O devices needs special
communication links for interfacing
them with the CPU.
The purpose of the communication link
is to resolves the differences between
the computer and peripheral devices.
Input/Output Interfaces

9. INPUT/OUTPUT INTERFACE
 The major differences are:-
(1) Peripherals – Electromechanical and electromagnetic Devices
CPU or Memory - Electronic Device
Therefore a conversion of signal values may be required.
(2) Data Transfer Rate
 Peripherals - Usually slower
 CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed
(3) Unit of Information
 Peripherals – Byte, Block, …
 CPU or Memory – Word
(4) Data representations may differ.
(5) Operating mode of peripherals are differ from each other and each must be
controlled so as not to disturb the operation of others peripherals connected to
the CPU.
To resolve these differences, computer system includes special hardware
components between CPU and I/O devices to supervise and synchronize all
input and output transfers. These components are called interface units.
Input/Output Interfaces

10. I/O BUS AND INTERFACE MODULES
Each peripheral has an interface module associated with it interface
with do following:
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises the transfer rate
between peripheral and CPU or Memory
Typical I/O instruction
(Command)
Op. code Device address Function code
Input/Output Interfaces
Processor
Interface
Keyboard
and
display
terminal
Magnetic
tape
Printer
Interface Interface Interface
Data
Address
Control
Magnetic
disk
I/O bus

11. Commands
 The I/O bus from the processor is attached
to all the I/O devices interface.
 To communicate with a particular device,
the processor puts a device address on the
address line.
 When interface detects its own address, it
activate the path between the bus line and
the device that it controls.
 At the same time that the address is made
available in the address lines, the processor
provides a function code in the control lines.

12. Commands
The interface selected respond to the
function code and proceeds to execute
it.
The function code is referred to as an
I/O command and is in essence an
instruction that is executed in the
interface and its attached peripheral
unit.
There are four types of command that
an interface may receive.
Control, Status, Data Output, Data Input.

13. CONNECTION OF I/O BUS
Connection of I/O Bus to One Interface
Connection of I/O Bus to CPU
Input/Output Interfaces
I/O
bus
Op.
code
Device
address
Function
code
Accumulator
register
Computer
I/O
control
Sense lines
Data lines
Function code lines
Device address lines
CPU
I/O
bus
Device
address
Command
decoder
Function code
Data lines
Buffer register
Peripheral
register
Status
register
Sense lines
Output
peripheral
device
and
controller
AD = 1101 Interface
Logic

14. I/O BUS AND MEMORY BUS
•MEMORY BUS is for information transfers
between CPU and the MM
•I/O BUS is for information transfers between
CPU and I/O devices through their I/O interface
• In addition to communicating with I/O,
the processor must communicate with
the memory unit.
• Like the I/O bus, the memory bus contains
data, address, and read/write control lines.
Functions of Buses
Input/Output Interfaces

15. I/O BUS AND MEMORY BUS
Many computers use a common single bus
system for both memory and I/O interface units.
• Use one common bus but separate control
lines for each function
• Use one common bus with common control
lines for both functions
• Some computer systems use two separate
buses
*one to communicate with memory and
*the other with I/O interfaces
Physical Organizations
Input/Output Interfaces

16. ISOLATED vs MEMORY MAPPED I/O
- Separate I/O read/write control
lines in addition to memory
read/write control lines
- Separate (isolated) memory
and I/O address spaces
- Distinct input and output
instructions
Isolated I/O
Input/Output Interfaces

17. ISOLATED vs MEMORY MAPPED I/O
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O
transfer)
- Memory and I/O addresses share the
common address space
-> reduces memory address range
available
- No specific input or output instruction
-> The same memory reference
instructions can be used for I/O transfers
- Considerable flexibility in handling I/O
operations
Input/Output Interfaces

18. I/O INTERFACE
CS RS1 RS0 Register selected
0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Input/Output Interfaces
Chip select
Register select
Register select
I/O read
I/O write
CS
RS1
RS0
RD
WR
Timing
and
Control
Bus
buffers
Bidirectional
data bus
Port A
register
Port B
register
Control
register
Status
register
I/O data
I/O data
Control
Status
CPU I/O
Device
The I/O data to and from
the device can be
transferred into either
port A or port B.
The transfer of data, control, or status information is via a
common data bus. The distinction between data, control,
or status information is determine from the particular
interface register with which the CPU communicates.

19. ASYNCHRONOUS DATA TRANSFER
Synchronous and Asynchronous
Transfer Operations
Synchronous –
All devices derive use the
timing information from common
clock line
Asynchronous –
No common clock used. All devices
derive use timing information from
own clock.
Asynchronous Data Transfer

20. ASYNCHRONOUS DATA TRANSFER
Asynchronous Data Transfer
• Asynchronous data transfer between two
independent units requires that control signals
be transmitted between the communicating units
to indicate the time at which data is being
transmitted.
• One way to achieving this is by means of a
STROBE pulse method.
• Other way is HANDSHAKING method.
• In general case we consider the transmitting
unit as the source and receiving unit as the
destination.
Asynchronous Data Transfer

21. Asynchronous Data Transfer Methods
 Strobe pulse
- A strobe pulse is supplied by one unit to
indicate the other unit when the transfer
has to occur.
 Handshaking
- A control signal is accompanied with
each data being transmitted to indicate the
presence of data.
- The receiving unit responds with another
control signal to acknowledge receipt of the
data.

22. * Employs a single control line (STROBE) and a data bus .
* The strobe may be activated by either the source or
the destination unit.
STROBE CONTROL
Source
unit
Destination
unit
Data bus
Strobe
Data
Strobe
Valid data
Block Diagram
Timing Diagram
Source-Initiated Strobe
for Data Transfer
Source
unit
Destination
unit
Data bus
Strobe
Data
Strobe
Valid data
Block Diagram
Asynchronous Data Transfer
Destination-Initiated Strobe
for Data Transfer
Timing Diagram

23. HANDSHAKING
In Strobe Methods -
Source-Initiated -The source unit that
initiates the Transfer has no way of knowing
whether the destination unit has actually
received data.
Destination-Initiated - The destination unit
that initiates the transfer no way of knowing
whether the source has actually placed the
data on the bus.
* To solve this problem, the HANDSHAKE
method introduces a second control signal
to provide a Reply to the unit that initiates
the transfer.
Asynchronous Data Transfer

24. SOURCE-INITIATED TRANSFER USING HANDSHAKE
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
Block Diagram
Timing Diagram
Accept data from bus.
Enable data accepted
Disable data accepted.
Ready to accept data
(initial state).
Sequence of Events
Place data on Data bus.
Enable data valid.
Source unit Destination unit
Disable data valid.
Invalidate data on bus.
Source
unit
Destination
unit
Data bus
Data accepted
Data bus
Data valid
Valid data
Data valid
Data accepted
Asynchronous Data Transfer

25. DESTINATION-INITIATED TRANSFER USING HANDSHAKE
Block Diagram
Timing Diagram
Source
unit
Destination
unit
Data bus
Ready for data
Data valid
Sequence of Events
Place data on bus.
Enable data valid.
Source unit Destination unit
Ready to accept data.
Enable ready for data.
Disable data valid.
Invalidate data on bus
(initial state).
Accept data from bus.
Disable ready for data.
Ready for data
Data valid
Data bus
Valid data
Asynchronous Data Transfer

26. HANDSHAKING
Handshaking provides a high degree of
flexibility and reliability because the
successful completion of a data transfer
relies on active participation by both
units.
If one unit is faulty, data transfer will not
be completed -> Can be detected by
means of a timeout mechanism, which
produces a alarm if data transfer is not
completed in time.

27. ASYNCHRONOUS SERIAL TRANSFER
Asynchronous serial transfer
Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
- Employs special bits which are inserted at both ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.
A character can be detected by the receiver from the knowledge of
4 rules;
- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last bit of the character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
Four Different Types of Transfer :->>>
Asynchronous Serial Transfer
Start
bit
(1 bit)
Stop
bits
Character bits
1 1 0 0 0 1 0 1
(at least 1 bit)
Asynchronous Data Transfer

28. BAUD RATE
 Consider the serial transmission of a terminal
whose transfer rate is 10 character per second.
Each transmitted consists of a start bit, eight
information bits, and two stop bits, for a total of 11
bits. Ten character per second means that each
character takes 0.1 second for transfer. Since there
are 11 bits to be transmitted, it follows that the bit
time is 9.09 ms.
 The baud rate is defined as the rate at which serial
information is transmitted and is equivalent to the
data transfer in bits per second.
 Ten character per second with an 11-bit format has
a transfer rate of 110 baud.

29. UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
- UART -
A typical asynchronous communication interface available as an IC
Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors (parity , framing, overrun error)
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check
parity, and no. of stop bits , used for initialization.
Chip select
Register select
I/O read
I/O write
CS
RS
RD
WR
Timing
and
Control
Bus
buffers
Bidirectional
data bus
Transmitter
register
Control
register
Status
register
Receiver
register
Shift
register
Transmitter
control
and clock
Receiver
control
and clock
Shift
register
Transmit
data
Transmitter
clock
Receiver
clock
Receive
data
Asynchronous Data Transfer
CS RS Oper. Register selected
0 x x None
1 0 WR Transmitter register
1 1 WR Control register
1 0 RD Receiver register
1 1 RD Status register
Internal
Bus
It functions as both
as a transmitter
and receiver.
Parallel transformation
Parallel transformation
Serial transformation
Serial transformation

30. FIRST-IN-FIRST-OUT(FIFO or Queue ) BUFFER
 FIFO buffer stores information in first in and
first out manner.
 It can input data and out put data at two
different rates.
 So it is useful when source and destination
unit has different data transfer rates.
 Output data are always in the same order in
which the data entered the buffer.
 Useful in some applications when data is
transferred asynchronously

31. FIRST-IN-FIRST-OUT(FIFO) BUFFER
4 x 4 FIFO Buffer (4 4-bit registers R1,R2,R3,R4), store 4 words of four bits each.
A Control Register (flip-flops Fi, associated with each Ri), Fi is set 1 indicates a 4-bit
data word is stored in Ri, if Fi=0 means Ri not contain valid data. Control registers
direct the movement of data through the registers. Whenever Fi=1 and the Fi+1 bit is
reset (Fi’+1=1), a clock is generated
Causing register R(i+1) to accept data from Ri. The same clock sets Fi+1 to 1 and
reset Fi to 0.
Asynchronous Data Transfer
4-bit
register
S
R
F
F'
1
1
4-bit
register
S
R
F
F'
2
2
4-bit
register
S
R
F
F'
3
3
4-bit
register
S
R
F
F'
4
4
F
F
S
R
F
F'
S
R
Clock Clock Clock Clock
Data
output
Output
ready
Delete
Data
input
Insert
Input ready
Master clear
R1 R2 R3 R4
Destination-
Initiated pair of
Handshake lines
Source-initiated
pair of
handshake
lines

32. MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -
3 different Data Transfer Modes between the central
computer(CPU or Memory) and peripherals; Program-Controlled I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)
Program-Controlled I/O(Input Dev to CPU)
Modes of Transfer
Polling or Status Checking
• Continuous CPU involvement
• CPU slowed down to I/O speed
• Simple
• Least hardware
Read status register
Check flag bit
flag
Read data register
Transfer data to memory
Operation
complete?
Continue with
program
= 0
= 1
yes
no
CPU
Data bus
Address bus
I/O read
I/O write
Interface
Data register
Status
register F
I/O bus
Data valid
Data accepted
I/O
device
Transferring data under program control
requires constant monitoring of the peripherals
by the CPU.(CPU stays in a program loop).
Useful for small low speed computers or in
systems that are dedicated to monitor a device
continuously.

33. Example
Consider a typical computer that can
execute the two instructions that read
the status register and check the flag in
1 μs. Assume that the input device
transfers its data at an average rate of
100bytes per second. This is equivalent
to one byte every 10,000 μs. This
means that the CPU will check the flag
10,000 times between each transfer.
(Know as polling and status checking.)

34. MODES OF TRANSFER - INTERRUPT INITIATED I/O
• Polling takes valuable CPU time
• Open communication only when
some data has to be passed ->
Interrupt to the CPU.
• I/O interface, instead of the CPU,
monitors the I/O device.
• When the interface determines
that the I/O device is ready for
data transfer, it generates an
Interrupt Request to the
CPU.
Modes of Transfer

35. MODES OF TRANSFER - INTERRUPT INITIATED I/O
•Upon detecting an interrupt, CPU
stops momentarily the task it is doing,
branches to the service routine to
process the data transfer, and then
returns to the task it was performing.
• CPU responds to the interrupt signal
by storing the return address from the
program counter into memory stack
and then control branches to a
service routine that processes the
required I/O transfer.
Modes of Transfer

36. MODES OF TRANSFER - DMA
DMA (Direct Memory Access)
• Large blocks of data transferred
at a high speed to or from high
speed devices, magnetic drums,
disks, tapes, etc.
• DMA controller is a Interface that
provides I/O transfer of data
directly to and from the memory
and the I/O device
Modes of Transfer

37. MODES OF TRANSFER - DMA
DMA (Direct Memory Access)
•CPU initializes the DMA
controller by sending a memory
address and the number of
words to be transferred.
• Actual transfer of data is done
directly between the device and
memory through DMA
controller --> Freeing CPU for
other tasks.
Modes of Transfer

38. PRIORITY INTERRUPT
Priority
- Determines which interrupt is to
be served first when two or more
requests are made simultaneously
- Also determines which device’s
interrupts are permitted to
interrupt the computer while
another is being serviced
- Higher priority interrupts can
make requests while servicing a
lower priority interrupt
Priority Interrupt

39. PRIORITY INTERRUPT
Priority Interrupt by Software(Polling)
- Priority is established by the order
of polling the devices
(interrupt sources)
- Flexible since it is established by
software
- Low cost since it needs a very little
hardware
- Very slow
Priority Interrupt

40. PRIORITY INTERRUPT
Priority Interrupt by Hardware
- Require a priority interrupt
manager which accepts all the
interrupt requests to determine
the highest priority request
- Fast since identification of the
highest priority interrupt request
is identified by the hardware
- Fast since each interrupt source has
its own interrupt vector to access
directly to its own service routine
Priority Interrupt

41. HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -
Interrupt Request from any device (If no device has interrupt
then int. req. line is in High Level state[=>1], if any device
has its interrupt signal, the int. req. line goes to the low level
state[=>0].)
-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the
VAD on the bus
Among interrupt requesting devices the only device which
is physically closest to CPU gets INTACK=1, and it blocks
INTACK to propagate to the next device
Priority Interrupt
Device 1
PI PO
Device 2
PI PO
Device 3
PI PO
INT
INTACK
Interrupt request
Interrupt acknowledge
To next
device
CPU
VAD 1 VAD 2 VAD 3
Processor data bus
* Serial hardware priority function
* Interrupt Request Line
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain

42. Internal Logic for Daisy-chaining Scheme
S
R
Q
Interrupt
request
from device
PI
Priority in
RF
Delay
Vector address
VAD
PO
Priority out
Interrupt request to CPU
Enable
PI RF PO Enable
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1

43. PARALLEL PRIORITY INTERRUPT
IEN: (Interrupt Enable FF) Set or Clear by program instructions ION or IOF
IST: (Interrupt status FF) Represents an unmasked interrupt has occurred.
INTACK enables tristate Bus Buffer to load VAD generated by the
Priority Logic
Priority Interrupt
Mask
register
INTACK From CPU
Priority
encoder
I 0
I 1
I 2
I 3
0
1
2
3
y
x
IST
IEN
0
1
2
3
0
0
0
0
0
0
Disk
Printer
Reader
Keyboard
Interrupt register
Enable
Interrupt
to CPU
VAD
to CPU
VAD to CPU
(Bus buffer)

44. Parallel Priority Interrupt
 Interrupt Register:
- Each bit is associated with an Interrupt Request from
different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
 Mask Register:
- Mask Register is associated with Interrupt Register
(Control the status of each interrupt request.)
- Each bit can be set or cleared by an Instruction
- can be programmed to disable to lower-priority
interrupt while a higher-priority device is being
serviced. (vice-verso opposite.)

45. INTERRUPT PRIORITY ENCODER
The priority encoder is a circuit that implements the
priority function. If two or more input arrives at the same
time, the input having the highest priority will take
precedence.
Priority Encoder Truth table
1 d d d
0 1 d d
0 0 1 d
0 0 0 1
0 0 0 0
I0 I1 I2
I3
0 0 1
0 1 1
1 0 1
1 1 1
d d 0
x y IST
x = I0' I1'
y = I0' I1 + I0’ I2’
(IST) = I0 + I1 + I2 + I3
Inputs Outputs
Boolean functions
Priority Interrupt
D= don’t care
conditions
I0 has the
highest priority
IST is set one
only when one
or more input
are equal to
one.
The output of the priority encoder is used to form part of
vector address for each interrupt source.

46. The IEN can be set and cleared by program instructions.
When IEN is cleared, the interrupt request coming from
IST is neglected by CPU.
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle
During the interrupt cycle the CPU performs the following
sequence of Micro- Operations:
INTERRUPT CYCLE
SP  SP - 1 Decrement stack pointer
M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch next instruction.
Priority Interrupt

47. INTERRUPT SERVICE ROUTINE
Priority Interrupt
address Memory
JMP PTR
JMP RDR
JMP KBD
JMP DISK
0
1
2
3
I/O service programs
Program to service
magnetic disk
Program to service
line printer
Program to service
character reader
Program to service
keyboard
DISK
PTR
RDR
KBD
255
256
750
256
750
Stack
Main program
current instr.
749
KBD
interrupt
2
VAD=00000011 3
4
Disk
interrupt
5
6
7
8
9 10
11
1
CPU is executing the instruction at 749 of the main program. At that time a
interrupt comes from keyboard (KBD). Then computers goes to the interrupt
cycle, it stores the return address 750 in the stack and then takes the vector
address 00000011 from the bus and transfer it to the PC. The instruction at
location 3 is executed next, resulting in transfer the control to the KBD
program. Now CPU executing the KBD program’s 255 address instruction ,
then another interrupt comes from the DISK. Then CPU store the return
address 256 in stack and jumps to DISK program. After completing the DISK
program , CPU takes the return address from stack which is 256, after
completing the KBD program CPU takes next return address 750.

48. DIRECT MEMORY ACCESS
High-impedence
(disabled)
when BG is
enabled
CPU bus signals for DMA transfer
Block diagram of DMA controller
* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)

Address bus
Data bus
Read
Write
ABUS
DBUS
RD
WR
Bus request
Bus granted
BR
BG
CPU
Address bus
Data bus
DMA select
Register select
Read
Write
Bus request
Bus grant
Interrupt
DS
RS
RD
WR
BR
BG
Interrupt
Data bus
buffers
Address bus
buffers
Address register
Word count register
Control register
DMA request
DMA acknowledge to I/O device
Control
logic
Direct Memory Access
Internal
Bus
Contains the address to
specify the desired location in
memory, incremented after
each word is transferred
Decremented by one after
each word is transferred
and tested for zero

49. DMA I/O OPERATION
The DMA is initialized by the CPU. The CPU
initializes the DMA by sending the following
information through the data bus:
1. The starting address of memory block where
data are available (for read) or where data are to
be stored (for write).
2. The word count, which is the number of words
in the memory block.
3. Control to specify the mode of transfer such as
read or write.
4. A control to start the DMA transfer (GO
command)
Upon receiving a GO Command DMA performs I/O
operation.
Direct Memory Access

50. BURST TRANSFER / CYCLE STEALING
When DMA takes control of the bus system, it communicate directly with
The memory. The transfer can be made in several ways.
BURST TRANSFER
In DMA burst transfer, a block sequence consisting of a number of
memory word is transferred in a continuous burst. This mode is
needed for fast devices.
CYCLE STEALING
An alternative technique called Cycle Stealing allows the DMA
controller to transfer one data word at a time, after which it must return
control of the buses to the CPU.
- CPU is usually much faster than I/O(DMA), thus
CPU uses the most of the memory cycles
- DMA Controller steals the memory cycles from CPU
- For those stolen cycles, CPU remains idle
- DMA Controller may steal most of the memory cycles which may
cause CPU remain idle long time
Direct Memory Access

51. DMA TRANSFER
BG
BR
CPU
RD WR Addr Data
Interrupt
Random-access
memory unit (RAM)
RD WR Addr Data
BR
BG
RD WR Addr Data
Interrupt
DS
RS DMA
Controller
I/O
Peripheral
device
DMA request
DMA ack.
Read control
Write control
Data bus
Address bus
Address
select
Direct Memory Access

52. INPUT/OUTPUT PROCESSOR (IOP)
Instead of having each interface communicate with
the CPU, a computer may incorporate one or
more external processors and design them the
task of communicating directly with all I/O
devices with DMA capability. This external
processor is know as Input/Output processors or
IOPs. A processor that communicate media in a
serial fashion (like telephone line used) is called
a data communication processor (DCP). In
addition IOP can perform other processing tasks,
such as arithmetic, logic, branching, and code
translation. [The IOP is also know as channel]

53. CPU-IOP COMMUNICATION
Send instruction
to test IOP path
If status OK, then send
start I/O instruction
to IOP.
CPU continues with
another program
Transfer status word
to memory
Access memory
for IOP program
Conduct I/O transfers
using DMA;
Prepare status report.
I/O transfer completed;
Interrupt CPU
Request IOP status
Transfer status word
to memory location
Check status word
for correct transfer.
Continue
CPU operations IOP operations
Input/Output Processor
The memory unit acts as a message center where each processor leaves information for other.