The input-output subsystem allows communication between the central computer system and external devices. Peripherals like keyboards, printers, and storage devices are connected via interface units that resolve differences in data formats and transfer rates. There are two main methods for organizing input-output - isolated I/O uses separate instructions to access interface registers, while memory-mapped I/O accesses peripherals through memory addresses on a shared bus. Asynchronous transfer between asynchronous units like the CPU and I/O interfaces requires control signals to synchronize the transmission of data.
The document discusses input/output (I/O) in computer systems. It describes various I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It also covers I/O modules, external devices, addressing schemes, and interface standards like SCSI and FireWire.
The document discusses input and output in computer systems. It describes three main techniques for transferring data between the CPU and I/O devices: programmed I/O, interrupt-driven I/O, and direct memory access (DMA). Programmed I/O involves the CPU continuously polling I/O devices, interrupt-driven I/O uses interrupts to signal the CPU when data is ready, and DMA allows high-speed transfer of data directly between memory and I/O devices without CPU involvement.
This document discusses input/output (I/O) hardware and file systems. It describes how operating systems control I/O devices and provide an interface between devices and software. I/O devices are divided into block devices, which store and transfer data in fixed-size blocks, and character devices, which transfer data as character streams. Device controllers connect devices to the computer and convert data between device and memory formats. Memory-mapped I/O and port-mapped I/O are approaches for CPU communication with controllers. Direct memory access allows high-speed transfer of data directly between devices and memory without CPU involvement.
The document discusses three different I/O techniques:
1. Programmed I/O - The CPU controls the entire I/O process and must periodically check device status, wasting CPU time.
2. Interrupt-driven I/O - The CPU issues a command and is freed up while the device operates. The device then interrupts the CPU when ready.
3. Direct memory access (DMA) - Allows devices to communicate directly with memory without involving the CPU, using a DMA controller. This overcomes CPU waiting and avoids repeated status checks.
Input output hardware of operating systemRohitYadav633
This document discusses input and output hardware and devices. It describes I/O devices as those that send information to computers for processing or reproduce processed results. The document categorizes I/O devices as block devices that communicate in entire blocks of data or character devices that communicate byte by byte. It also discusses device drivers, controllers, synchronous vs asynchronous communication, and techniques for communication like memory mapping, DMA, polling, and interrupts.
The document discusses input/output (I/O) processing and the role of the operating system in managing I/O operations and devices. It covers I/O hardware components like ports, buses, and controllers. It also describes the different models for interaction between I/O controllers and CPUs, including polling, interrupts, and direct memory access (DMA). Finally, it discusses I/O application interfaces and blocking vs non-blocking I/O.
This document discusses I/O systems, including an overview of I/O hardware, the application I/O interface, the kernel I/O subsystem, and I/O performance. It describes how I/O requests are transformed into hardware operations through techniques like interrupts, DMA, polling, and blocking vs. asynchronous I/O. Specific I/O concepts covered include STREAMS, device characteristics, and data structures used in the kernel I/O subsystem.
This document discusses different input/output techniques for computer systems. It describes three main I/O techniques: programmed I/O, interrupt-driven I/O, and direct memory access. Programmed I/O involves the CPU waiting for I/O operations to complete, interrupt-driven I/O uses interrupts to notify the CPU when an operation is done, and DMA allows data transfers without CPU involvement. The document also outlines functions of I/O modules, which connect I/O devices to system buses, and different addressing and mapping schemes for I/O devices.
The document discusses input/output (I/O) in computer systems. It describes various I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It also covers I/O modules, external devices, addressing schemes, and interface standards like SCSI and FireWire.
The document discusses input and output in computer systems. It describes three main techniques for transferring data between the CPU and I/O devices: programmed I/O, interrupt-driven I/O, and direct memory access (DMA). Programmed I/O involves the CPU continuously polling I/O devices, interrupt-driven I/O uses interrupts to signal the CPU when data is ready, and DMA allows high-speed transfer of data directly between memory and I/O devices without CPU involvement.
This document discusses input/output (I/O) hardware and file systems. It describes how operating systems control I/O devices and provide an interface between devices and software. I/O devices are divided into block devices, which store and transfer data in fixed-size blocks, and character devices, which transfer data as character streams. Device controllers connect devices to the computer and convert data between device and memory formats. Memory-mapped I/O and port-mapped I/O are approaches for CPU communication with controllers. Direct memory access allows high-speed transfer of data directly between devices and memory without CPU involvement.
The document discusses three different I/O techniques:
1. Programmed I/O - The CPU controls the entire I/O process and must periodically check device status, wasting CPU time.
2. Interrupt-driven I/O - The CPU issues a command and is freed up while the device operates. The device then interrupts the CPU when ready.
3. Direct memory access (DMA) - Allows devices to communicate directly with memory without involving the CPU, using a DMA controller. This overcomes CPU waiting and avoids repeated status checks.
Input output hardware of operating systemRohitYadav633
This document discusses input and output hardware and devices. It describes I/O devices as those that send information to computers for processing or reproduce processed results. The document categorizes I/O devices as block devices that communicate in entire blocks of data or character devices that communicate byte by byte. It also discusses device drivers, controllers, synchronous vs asynchronous communication, and techniques for communication like memory mapping, DMA, polling, and interrupts.
The document discusses input/output (I/O) processing and the role of the operating system in managing I/O operations and devices. It covers I/O hardware components like ports, buses, and controllers. It also describes the different models for interaction between I/O controllers and CPUs, including polling, interrupts, and direct memory access (DMA). Finally, it discusses I/O application interfaces and blocking vs non-blocking I/O.
This document discusses I/O systems, including an overview of I/O hardware, the application I/O interface, the kernel I/O subsystem, and I/O performance. It describes how I/O requests are transformed into hardware operations through techniques like interrupts, DMA, polling, and blocking vs. asynchronous I/O. Specific I/O concepts covered include STREAMS, device characteristics, and data structures used in the kernel I/O subsystem.
This document discusses different input/output techniques for computer systems. It describes three main I/O techniques: programmed I/O, interrupt-driven I/O, and direct memory access. Programmed I/O involves the CPU waiting for I/O operations to complete, interrupt-driven I/O uses interrupts to notify the CPU when an operation is done, and DMA allows data transfers without CPU involvement. The document also outlines functions of I/O modules, which connect I/O devices to system buses, and different addressing and mapping schemes for I/O devices.
This document discusses I/O systems and their design. It describes the major components of I/O systems including devices, buses, and controllers. It discusses characteristics like performance, dependability, and expandability. Specific storage technologies like disks are examined in depth, covering aspects like seek time, rotational latency, and caching. The document also covers I/O programming techniques, buses, DMA, benchmarks, and example designs to optimize throughput and latency. A key consideration in design is balancing the workload between CPUs and I/O processors.
The document provides an overview of computer architecture and input/output techniques. It defines computer architecture as the set of instructions that describe a computer's organization and implementation. It discusses how I/O modules interface external devices like keyboards and printers to the CPU and memory. There are three main I/O techniques: programmed I/O where the CPU directly controls I/O, interrupt-driven I/O where devices interrupt the CPU when ready, and DMA where devices access memory independently of the CPU to improve efficiency. The document outlines the components and functioning of I/O modules and the various I/O commands used to control peripheral devices.
The document discusses application I/O interfaces and their characteristics. Application I/O interfaces provide standard ways for operating systems to treat I/O devices uniformly by hiding differences through device drivers. I/O interfaces have characteristics like their data transfer mode (character or block), access method (sequential or random), transfer schedule (synchronous or asynchronous), ability to be shared, speed, and supported input/output directions.
This document discusses programmed input/output (I/O) mode for data transfer. It explains that programmed I/O involves (1) the program waiting for the device to signal ready status by repeatedly testing status bits before each transfer, and (2) data is only transferred once the other end is ready. While this ensures the processor is dedicated to I/O, it can result in prolonged wait states which are inappropriate for asynchronous devices that can trigger events unpredictably, like keyboards. The document provides examples of reading and writing data using programmed I/O mode.
The document discusses the key components of an embedded system, including the memory map, I/O map, and interrupt map. The memory map shows the memory addresses for devices like RAM, ROM, and peripherals. The I/O map similarly lists addresses for devices that use a separate I/O space. The interrupt map defines interrupt numbers for devices that can trigger interrupts, like a serial controller. Together these maps provide an interface for the programmer to access hardware on the embedded board.
The document provides information about input/output management in operating systems. It discusses I/O devices, device controllers, direct memory access and DMA controllers. Some key points include:
I/O devices are divided into block devices which access fixed size blocks of data and character devices which access data as a sequential stream. Device controllers act as an interface between devices and device drivers. Direct memory access allows data transfer between memory and devices without CPU involvement by using a DMA controller. DMA controllers program data transfers and arbitrate bus access.
SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT II Embedded Systems MemoryArti Parab Academics
The document discusses different types of computer memory and memory testing techniques. It describes three main types of memory - RAM, ROM, and hybrid memory. RAM is volatile and used for main memory, ROM is non-volatile but can only be read from, and hybrid memory has aspects of both. The document then discusses various memory testing strategies to verify memory functionality, including testing the data bus, address bus, and memory devices themselves.
This document discusses input/output (I/O) organization in computer systems. It covers various I/O techniques including programmed I/O, interrupts, direct memory access (DMA), and I/O interfaces. Memory-mapped I/O allows I/O devices to use the same address space as memory. Interrupts allow I/O devices to signal the processor when they need service. DMA controllers can transfer data directly between I/O devices and memory without processor intervention. Buses and interface circuits are used to connect I/O devices to the processor and main memory.
Hardware refers to the physical components of computers that can be touched and seen. This includes input devices like keyboards and mice and output devices like monitors and printers. The document then provides details about computer buses that connect hardware components and allow communication, different types of computer memory architectures, input/output techniques like port I/O and memory-mapped I/O, and direct memory access which allows hardware devices to access memory directly without using the CPU.
Input/output modules are critical components that allow computers to interact with external devices. I/O modules serve as an interface between peripherals and the CPU/memory. They perform important functions like control and timing of data transfers, communication with the processor and devices, buffering data, and error detection. I/O modules connect to the system bus and contain data buffers, status registers, and logic to interact with the processor via control lines. This allows external devices like disks and tapes to connect indirectly to the computer and be managed through simple read/write commands.
The document discusses various input/output (I/O) organization topics including I/O interfaces, buses, programmed I/O, interrupts, direct memory access, and memory-mapped I/O. It provides details on synchronous and asynchronous buses, interrupt request hardware, enabling and disabling interrupts, and techniques for handling interrupts from multiple devices such as polling, vectored interrupts, and daisy chaining.
SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT III The 8051 MicrocontrollersArti Parab Academics
The 8051 Microcontrollers: Microcontrollers and Embedded processors, Overview of 8051 family. 8051 Microcontroller hardware, Input/output pins, Ports, and Circuits, External Memory. 8051 Programming in C: Data Types and time delay in 8051 C, I/O Programming, Logic operations, Data conversion Programs
The document discusses various input and output interfaces for computer systems including serial interfaces like RS-232C and USB, parallel interfaces, and wireless technologies like IrDA. It also covers input devices such as keyboards, mice, scanners, digital cameras, and technologies for audio, video, and accessibility for disabled users. Input devices convert human-centric inputs while output devices present processed data in a human-readable format.
This slide deals with the Input-Output Channel of an IBM 370 computer. It includes three Block diagrams of the I-O channels as well as the Memory Unit with the Description of each and every diagrams.
The document discusses various techniques for input/output (I/O) in computer systems, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes how I/O modules interface with CPUs and peripherals to handle data transfer between devices that operate at different speeds. Common I/O bus standards like ISA, PCI, FireWire, and InfiniBand are also overviewed in terms of their architecture, protocols, and applications.
The document discusses input-output (I/O) modules in computers. It explains that I/O modules play a crucial role in allowing communication between a computer's central processing unit (CPU) and external devices. I/O modules connect devices to the computer's system bus and control the exchange of data between devices and main memory or the CPU. They help address issues like differing data formats and speeds between devices and the CPU. The document outlines various I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access (DMA) that use I/O modules to facilitate input and output.
The document discusses the organization and design of computers. It covers:
1) The main components of a computer including the processing unit, memory system, control unit, and datapath.
2) How the control unit uses a finite state machine to interpret instructions and generate control signals to direct the datapath.
3) How the datapath consists of functional units like the ALU and registers to perform operations.
4) How instructions are fetched from memory and executed in three steps - fetch, decode, execute - by directing the flow of data through the datapath.
This document provides information about input-output interfaces in computer systems. It discusses how interface units connect peripheral devices to the CPU and resolve differences in data formats and transfer rates. Interface units include address decoders, registers for control, status, and transferring data. The document contrasts isolated I/O, where separate input/output instructions are used, versus memory-mapped I/O, where I/O devices use memory addresses. It provides an example of an interface unit with control, status and data registers that communicate with the CPU over a shared bus.
A peripheral device provides input/output functions for a computer as an auxiliary device without core computing functionality. Peripheral devices are classified into input devices, output devices, and storage devices. An input/output interface helps transfer information between internal storage and external peripheral devices. It resolves differences in data formats and speeds between the CPU and peripheral devices. The interface provides control signals and buffers data to synchronize operations. Computers can use separate I/O and memory buses or a common bus with separate control lines or common control lines to communicate with peripherals and memory.
This document discusses I/O systems and their design. It describes the major components of I/O systems including devices, buses, and controllers. It discusses characteristics like performance, dependability, and expandability. Specific storage technologies like disks are examined in depth, covering aspects like seek time, rotational latency, and caching. The document also covers I/O programming techniques, buses, DMA, benchmarks, and example designs to optimize throughput and latency. A key consideration in design is balancing the workload between CPUs and I/O processors.
The document provides an overview of computer architecture and input/output techniques. It defines computer architecture as the set of instructions that describe a computer's organization and implementation. It discusses how I/O modules interface external devices like keyboards and printers to the CPU and memory. There are three main I/O techniques: programmed I/O where the CPU directly controls I/O, interrupt-driven I/O where devices interrupt the CPU when ready, and DMA where devices access memory independently of the CPU to improve efficiency. The document outlines the components and functioning of I/O modules and the various I/O commands used to control peripheral devices.
The document discusses application I/O interfaces and their characteristics. Application I/O interfaces provide standard ways for operating systems to treat I/O devices uniformly by hiding differences through device drivers. I/O interfaces have characteristics like their data transfer mode (character or block), access method (sequential or random), transfer schedule (synchronous or asynchronous), ability to be shared, speed, and supported input/output directions.
This document discusses programmed input/output (I/O) mode for data transfer. It explains that programmed I/O involves (1) the program waiting for the device to signal ready status by repeatedly testing status bits before each transfer, and (2) data is only transferred once the other end is ready. While this ensures the processor is dedicated to I/O, it can result in prolonged wait states which are inappropriate for asynchronous devices that can trigger events unpredictably, like keyboards. The document provides examples of reading and writing data using programmed I/O mode.
The document discusses the key components of an embedded system, including the memory map, I/O map, and interrupt map. The memory map shows the memory addresses for devices like RAM, ROM, and peripherals. The I/O map similarly lists addresses for devices that use a separate I/O space. The interrupt map defines interrupt numbers for devices that can trigger interrupts, like a serial controller. Together these maps provide an interface for the programmer to access hardware on the embedded board.
The document provides information about input/output management in operating systems. It discusses I/O devices, device controllers, direct memory access and DMA controllers. Some key points include:
I/O devices are divided into block devices which access fixed size blocks of data and character devices which access data as a sequential stream. Device controllers act as an interface between devices and device drivers. Direct memory access allows data transfer between memory and devices without CPU involvement by using a DMA controller. DMA controllers program data transfers and arbitrate bus access.
SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT II Embedded Systems MemoryArti Parab Academics
The document discusses different types of computer memory and memory testing techniques. It describes three main types of memory - RAM, ROM, and hybrid memory. RAM is volatile and used for main memory, ROM is non-volatile but can only be read from, and hybrid memory has aspects of both. The document then discusses various memory testing strategies to verify memory functionality, including testing the data bus, address bus, and memory devices themselves.
This document discusses input/output (I/O) organization in computer systems. It covers various I/O techniques including programmed I/O, interrupts, direct memory access (DMA), and I/O interfaces. Memory-mapped I/O allows I/O devices to use the same address space as memory. Interrupts allow I/O devices to signal the processor when they need service. DMA controllers can transfer data directly between I/O devices and memory without processor intervention. Buses and interface circuits are used to connect I/O devices to the processor and main memory.
Hardware refers to the physical components of computers that can be touched and seen. This includes input devices like keyboards and mice and output devices like monitors and printers. The document then provides details about computer buses that connect hardware components and allow communication, different types of computer memory architectures, input/output techniques like port I/O and memory-mapped I/O, and direct memory access which allows hardware devices to access memory directly without using the CPU.
Input/output modules are critical components that allow computers to interact with external devices. I/O modules serve as an interface between peripherals and the CPU/memory. They perform important functions like control and timing of data transfers, communication with the processor and devices, buffering data, and error detection. I/O modules connect to the system bus and contain data buffers, status registers, and logic to interact with the processor via control lines. This allows external devices like disks and tapes to connect indirectly to the computer and be managed through simple read/write commands.
The document discusses various input/output (I/O) organization topics including I/O interfaces, buses, programmed I/O, interrupts, direct memory access, and memory-mapped I/O. It provides details on synchronous and asynchronous buses, interrupt request hardware, enabling and disabling interrupts, and techniques for handling interrupts from multiple devices such as polling, vectored interrupts, and daisy chaining.
SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT III The 8051 MicrocontrollersArti Parab Academics
The 8051 Microcontrollers: Microcontrollers and Embedded processors, Overview of 8051 family. 8051 Microcontroller hardware, Input/output pins, Ports, and Circuits, External Memory. 8051 Programming in C: Data Types and time delay in 8051 C, I/O Programming, Logic operations, Data conversion Programs
The document discusses various input and output interfaces for computer systems including serial interfaces like RS-232C and USB, parallel interfaces, and wireless technologies like IrDA. It also covers input devices such as keyboards, mice, scanners, digital cameras, and technologies for audio, video, and accessibility for disabled users. Input devices convert human-centric inputs while output devices present processed data in a human-readable format.
This slide deals with the Input-Output Channel of an IBM 370 computer. It includes three Block diagrams of the I-O channels as well as the Memory Unit with the Description of each and every diagrams.
The document discusses various techniques for input/output (I/O) in computer systems, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes how I/O modules interface with CPUs and peripherals to handle data transfer between devices that operate at different speeds. Common I/O bus standards like ISA, PCI, FireWire, and InfiniBand are also overviewed in terms of their architecture, protocols, and applications.
The document discusses input-output (I/O) modules in computers. It explains that I/O modules play a crucial role in allowing communication between a computer's central processing unit (CPU) and external devices. I/O modules connect devices to the computer's system bus and control the exchange of data between devices and main memory or the CPU. They help address issues like differing data formats and speeds between devices and the CPU. The document outlines various I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access (DMA) that use I/O modules to facilitate input and output.
The document discusses the organization and design of computers. It covers:
1) The main components of a computer including the processing unit, memory system, control unit, and datapath.
2) How the control unit uses a finite state machine to interpret instructions and generate control signals to direct the datapath.
3) How the datapath consists of functional units like the ALU and registers to perform operations.
4) How instructions are fetched from memory and executed in three steps - fetch, decode, execute - by directing the flow of data through the datapath.
This document provides information about input-output interfaces in computer systems. It discusses how interface units connect peripheral devices to the CPU and resolve differences in data formats and transfer rates. Interface units include address decoders, registers for control, status, and transferring data. The document contrasts isolated I/O, where separate input/output instructions are used, versus memory-mapped I/O, where I/O devices use memory addresses. It provides an example of an interface unit with control, status and data registers that communicate with the CPU over a shared bus.
A peripheral device provides input/output functions for a computer as an auxiliary device without core computing functionality. Peripheral devices are classified into input devices, output devices, and storage devices. An input/output interface helps transfer information between internal storage and external peripheral devices. It resolves differences in data formats and speeds between the CPU and peripheral devices. The interface provides control signals and buffers data to synchronize operations. Computers can use separate I/O and memory buses or a common bus with separate control lines or common control lines to communicate with peripherals and memory.
The document discusses input/output (I/O) organization in computers. It covers various topics related to I/O including I/O interfaces, asynchronous and synchronous data transfer, and different modes of data transfer like programmed I/O and direct memory access. It describes how I/O devices connect to the computer and how interface modules resolve differences in data formats and transfer rates between I/O devices and the CPU. It also discusses I/O buses and different methods of communication between CPU, memory, and I/O including separate I/O and memory buses, isolated I/O using separate control lines, and memory mapped I/O.
This document discusses input/output organization and peripheral devices. It covers the following key points in 3 sentences:
Peripheral devices allow input and output between the computer and external environment. The document outlines different types of input devices, output devices, and input/output devices. It also discusses the input/output interface which provides communication between the CPU, memory, and peripheral devices by resolving differences in data formats, transfer rates, and operating modes.
Input - Output Organization and I/O Interfacekasthurimukila
I/O interfaces are the mediums in which data are sent from internal logic to external sources and from which data are received from external sources. The interface signals can be unidirectional or bidirectional, single-ended or differential and could follow one of the different I/O standards.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like interrupt priority, direct memory access (DMA), input/output processors, and serial communication.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like UART, FIFO buffers, and different modes of data transfer between CPU and peripheral devices including program-controlled, interrupt-initiated, and direct memory access.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses the input/output interface that provides communication between the CPU and I/O devices. It also describes asynchronous data transfer methods like strobe pulse and handshaking that allow synchronization between independent units transferring data asynchronously.
The document discusses input/output organization. It covers peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer including programmed I/O, interrupt-initiated I/O, and direct memory access (DMA), priority interrupts, and input-output processors. Specifically, it describes how priority interrupts work using both software polling and hardware daisy chaining approaches, and how parallel priority interrupts use an interrupt register, mask register, and priority encoder to determine the highest priority interrupt request.
The document discusses input/output organization and accessing I/O devices. There are three key components to a computer system: the processor, memory, and I/O modules. I/O modules interface between peripheral devices and the system bus, controlling the transfer of data. I/O modules perform functions like control and timing, processor/device communication, data buffering, and error detection to facilitate input and output.
Computer organisation and architecture module 1abinrj123
The document discusses computer instructions and their formats. It explains that there are three main instruction formats: memory reference, register reference, and input/output. Memory reference instructions use bits to specify an address and addressing mode. Register reference instructions specify an operation on the AC register without an operand. Input/output instructions specify an I/O operation without a memory reference. The instruction set is complete if it includes arithmetic, data movement, program control, and I/O instructions.
The primary purpose of memory interfacing is to facilitate the transfer of da...Sindhu Mani
The document discusses memory interfacing concepts. It begins by outlining key concepts in memory interfacing such as the address bus, data bus, control signals, and memory decoding. It then discusses microprocessor interfacing, specifically I/O addressing using port-based and bus-based approaches. The document also covers interrupts, direct memory access (DMA), and the universal asynchronous receiver/transmitter (UART) component.
This document discusses input/output organization in computer systems. It describes peripheral devices for input and output, input/output interfaces that allow communication between peripherals and the CPU/memory, and various methods for transferring data asynchronously between independent devices or systems, including strobe control, handshaking, and serial transmission. Asynchronous data transfer is necessary because peripherals often operate at different speeds than the CPU and memory.
This document provides an overview of basic computer architecture and operation. It discusses the five main functional units of a computer: the control unit, arithmetic and logic unit, memory unit, input unit, and output unit. It describes how these units work together and are connected via buses to transfer data, addresses, and control signals. The document also covers topics like bus types, memory organization, the system clock, input/output handling, and the memory cycle.
The document discusses input/output (I/O) organization in computer systems. It describes three common methods for synchronizing data transfers between processors and I/O devices: program-controlled I/O where the processor polls device status, interrupts where devices signal readiness to the processor, and direct memory access where devices transfer data directly to memory. Interrupts allow the processor to perform other tasks while waiting for I/O, and involve saving state before servicing requests. Processors provide interrupt enabling and disabling to control when requests can be accepted.
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Internal and external hardware components of a computerbethan_eastlake
The document describes the internal and external hardware components of a computer. It discusses the CPU, main memory including RAM and ROM, input/output controllers and ports, system buses including the address bus, control bus, and data bus. Peripherals and secondary storage are also summarized as external components that connect via input/output controllers.
The document discusses cathode ray tubes (CRTs) and how they work to display images on screens. It describes how CRTs use an electron gun to produce a scanning electron beam that hits a phosphorescent screen, causing spots of light. Different phosphors allow for different colors. The beam is focused and deflected electromagnetically to refresh the screen rapidly and create a full image. Resolution depends on factors like phosphor type and beam intensity. Color images are represented using RGB color models that mix red, green, and blue intensities.
Projection is a technique to transform a 3D object into a 2D plane. There are two main types of projection: parallel projection and perspective projection. Parallel projection involves projecting lines parallel to the view plane, maintaining accurate measurements but less realistic appearance. Perspective projection accounts for the finite distance to the view plane, making images more realistic but challenging to implement due to vanishing points. Common parallel projections include orthographic and oblique, while common perspective projections include one point, two point, and three point perspectives.
The document discusses three color models:
1) RGB color model represents colors as combinations of red, green, and blue primary colors. It can be represented as a color cube with these primary colors at the vertices.
2) CMY color model uses cyan, magenta, and yellow primaries and subtracts from white to produce colors.
3) HSV color model describes colors in terms of hue, saturation, and value. Hue is represented as an angle around a hexagonal boundary in a three-dimensional hexcone shape. Saturation corresponds to purity and value corresponds to intensity.
CG03 Random Raster Scan displays and Color CRTs.ppsxjyoti_lakhani
The document discusses different types of graphics displays. It describes raster-scan displays, which use an electron beam that sweeps across the screen from top to bottom to display an image. Picture definition is stored in a frame buffer. It also describes random-scan displays, which direct the electron beam only where lines need to be drawn. Color CRT monitors use phosphors and a shadow mask to display color. Flat panel displays like plasma panels, thin-film electroluminescent displays, and liquid crystal displays provide thinner alternatives to CRTs.
The document discusses cathode ray tubes (CRTs) and how they work to display images on monitors. It describes how CRTs use an electron gun to produce a scanning electron beam that hits a phosphorescent screen, causing spots of light. Different phosphors allow for different colors. The beam is swept across the screen in a raster pattern through deflection coils. Factors like resolution, aspect ratio, and refresh rate affect image quality. Color images are represented using the RGB color model with red, green, and blue intensity values.
The document discusses computer graphics and the process of generating images through different stages: object space defines the envisioned drawing, image space is the continuous space containing the drawn object, and scan conversion converts it to discrete pixels on a screen causing aliasing. It also describes computer graphics tools including hardware like monitors and software like graphics routines and standards used to produce pictures. Finally, it outlines applications of computer graphics in engineering, medical visualization, animation, and more.
A doubly linked list is a type of linked list that allows navigation in both directions via previous and next pointers. It supports insertion and deletion at both the front and rear of the list. The document outlines the process for inserting and deleting nodes from a doubly linked list, including handling empty and non-empty list cases.
A double-ended queue (DEQueue) allows nodes to be added and removed from both the front and rear ends. It supports four basic operations - insertion and deletion from the front and rear. The document describes the DEQueue data structure and provides pseudocode for handling cases when inserting or deleting from an empty versus non-empty queue.
Tree terminology and introduction to binary treejyoti_lakhani
Trees are hierarchical data structures where data items have a parent-child relationship. There are several ways to represent trees in memory, including array and linked list representations. Array representation stores tree nodes sequentially in an array, where the index of each node can be used to determine its parent, left child, right child, and siblings according to specific formulas. For example, the parent of node at index n is located at (n-1)/2, the left child is at 2n+1, and the right child is at 2n+2. Array representation allows trees to be traversed and manipulated efficiently.
A priority queue is a queue that allows nodes to be added and deleted based on priority or preference. Nodes with higher priority are inserted at the front of the queue and lower priority nodes are added to the back. When deleting from the queue, the highest priority or first node is always removed first.
This C++ program implements functions to perform operations on a singly linked list:
1. A create_node function allocates and returns a new node with the given value.
2. An insert_begin function inserts a new node at the beginning of the list, updating the start pointer.
3. A delete_begin function deletes the node at the beginning of the list, updating the start pointer and deallocating the node.
4. A display function traverses the list and prints out the values of each node.
Ds06 linked list- insert a node after a given nodejyoti_lakhani
The document discusses inserting a node into a linked list after a given node. It describes linked lists as a linear data structure that stores multiple values in nodes connected by pointers. The algorithm for inserting a node after a given node is presented:
1. Find the node before the given node by traversing the list and comparing node values
2. Set the next pointer of the new node to the node after the given node
3. Set the next pointer of the node before the given node to the new node
This inserts the new node between the node before and after the given node in the linked list.
This document discusses inserting a node into a linked list at the end. It explains that to insert a node at the end, you first check if the list is empty and if so make the new node the start. If the list is not empty, you iterate through the list with a pointer ptr until ptr->next is NULL, at which point you set ptr->next to the new node and new_node->next to NULL. Diagrams are included to visualize the process. The algorithm runs in O(n) time where n is the number of nodes in the list.
Ds06 linked list- insert a node at beginningjyoti_lakhani
The document discusses linked lists and operations on linked lists such as insertion and deletion of nodes. It specifically describes an algorithm to insert a node at the beginning of a linked list. The algorithm first checks if the list is empty, and if so makes the new node the start. If the list is not empty, it sets the next pointer of the new node to the current start node, and then makes the new node the new start.
Ds06 linked list- intro and create a nodejyoti_lakhani
A linked list is a linear data structure that stores multiple values in nodes that are connected by pointers. Each node contains a data field for its value and a pointer field linking to the next node. This allows flexible and efficient insertion and removal of nodes anywhere in the list. The document outlines the basic structure of a linked list and node, and provides pseudocode for creating a new node by allocating memory, inserting the data value, and initializing the next pointer to NULL.
Ds04 abstract data types (adt) jyoti lakhanijyoti_lakhani
An abstract data type (ADT) defines a pen as a collection of related data items including type, brand, color, and price along with operations such as write. An ADT describes what data and operations are involved without specifying how they are implemented, focusing on the essential properties and behaviors. A data structure then provides the physical implementation of an ADT, realizing how the data and operations are structured and processed.
Ds03 part i algorithms by jyoti lakhanijyoti_lakhani
The document defines an algorithm as a finite sequence of unambiguous instructions to solve a problem and produce an output from given inputs. It notes that algorithms have advantages like being easy to plan, implement, understand and debug. The key aspects of algorithms discussed are that they must be step-by-step, unambiguous and able to solve problems in a finite amount of time. The document also discusses analyzing and choosing between algorithms, as well as designing, proving, coding and analyzing algorithms.
The document discusses algorithms, defining them as unambiguous step-by-step instructions to solve a problem within a finite time. It notes that algorithms can be represented in various ways like pseudo-code or flowcharts. The key aspects of algorithms covered include analyzing their time and space complexity, choosing appropriate data structures, proving their correctness, and coding them efficiently. The document emphasizes understanding the problem fully before designing an algorithm and choosing techniques like greedy or divide-and-conquer approaches.
The document discusses flow charts and pseudo code. It provides an overview of flow chart symbols and conventions, examples of algorithms expressed as both a flow chart and pseudo code, guidelines for writing pseudo code, and conventions commonly used in pseudo code.
Ds01 data structure introduction - by jyoti lakhanijyoti_lakhani
The document discusses data structures and algorithms. It explains that data structures organize data in a way that makes it easy to access, manipulate, and update. Using the correct data structure for a problem makes the problem more manageable and finding a solution easier. Algorithms provide step-by-step instructions to solve problems and are implemented using data structures. They allow complex problems to be broken down into smaller, modular problems.
A workshop hosted by the South African Journal of Science aimed at postgraduate students and early career researchers with little or no experience in writing and publishing journal articles.
Strategies for Effective Upskilling is a presentation by Chinwendu Peace in a Your Skill Boost Masterclass organisation by the Excellence Foundation for South Sudan on 08th and 09th June 2024 from 1 PM to 3 PM on each day.
How to Build a Module in Odoo 17 Using the Scaffold MethodCeline George
Odoo provides an option for creating a module by using a single line command. By using this command the user can make a whole structure of a module. It is very easy for a beginner to make a module. There is no need to make each file manually. This slide will show how to create a module using the scaffold method.
How to Setup Warehouse & Location in Odoo 17 InventoryCeline George
In this slide, we'll explore how to set up warehouses and locations in Odoo 17 Inventory. This will help us manage our stock effectively, track inventory levels, and streamline warehouse operations.
it describes the bony anatomy including the femoral head , acetabulum, labrum . also discusses the capsule , ligaments . muscle that act on the hip joint and the range of motion are outlined. factors affecting hip joint stability and weight transmission through the joint are summarized.
The simplified electron and muon model, Oscillating Spacetime: The Foundation...RitikBhardwaj56
Discover the Simplified Electron and Muon Model: A New Wave-Based Approach to Understanding Particles delves into a groundbreaking theory that presents electrons and muons as rotating soliton waves within oscillating spacetime. Geared towards students, researchers, and science buffs, this book breaks down complex ideas into simple explanations. It covers topics such as electron waves, temporal dynamics, and the implications of this model on particle physics. With clear illustrations and easy-to-follow explanations, readers will gain a new outlook on the universe's fundamental nature.
Main Java[All of the Base Concepts}.docxadhitya5119
This is part 1 of my Java Learning Journey. This Contains Custom methods, classes, constructors, packages, multithreading , try- catch block, finally block and more.
1. INPUT-OUTPUT ORGANIZATION
Peripheral Devices
The input-output subsystem of a computer, referred to as I/O, provides an efficient mode of
communication between the central system and the outside environment.
A computer serves no useful purpose without the ability to receive information from an outside source and
to transmit results in a meaningful form.
The most familiar means of entering information into a computer is through a typewriter like keyboard that
allows a person to enter alphanumeric information directly. Every time a key is depressed, the terminal
sends a binary coded character to the computer.
The fastest possible speed for entering information this way depends on the person’s typing speed. On the
other hand, the central processing unit is an extremely fast device capable of performing operations at very
high speed.
When input information is transferred to the processor via a slow keyboard, the processor will be idle most
of the time while waiting for the information to arrive. To use a computer efficiently, a large amount of
programs and data must be prepared in advance and transmitted into a storage medium such as magnetic
tapes or disks. The information in the disk is then transferred into computer memory at a rapid rate. Results
of programs are also transferred into a high-speed storage, such as disks, from which they can be
transferred later into a printer to provide a printed output of results.
Devices that are under the direct control of the computer are said to be connected on-line. These devices
are designed to read information into or out of the memory unit upon command from the CPU and are
considered to be part of the total computer system.
Input or output devices attached to the computer are also called peripherals.
The input-output organization of a computer is a function of the size of the computer and the devices
connected to it.
ASCII ALPHANUMERIC CHARACTERS
Input and output devices that communicate with people and the computer are usually involved in the
transfer of alphanumeric information to and from the device and the computer is ASCII It uses seven bits
to code 128 characters. The seven bits of the code are designated by b1 through b7 being the most
significant bit. The letter A, for example, is represented in ASCII as 1000001 (column 100, row 0001).
The ASCII code contains 94 characters that can be printed and 34 nonprinting characters used for various
control functions. The printing characters consist of the 26 uppercase letters A through Z, the 26 lowercase
letters, the 10 numerals 0 through 9, and 32 special printable characters such as %, *, and $.
The 34 control characters are designated in the ASCII table with abbreviated names.
The control characters are used for routing data and arranging the printed text into a prescribed format.
There are three types of control characters: format effectors, information separators, and communication
control characters.
Format effectors are characters that control the layout of printing. They include the familiar typewriter
controls, such as backspace (BS), horizontal tabulation (HT), and carriage return (CR). Information
separators are used to separate the data into divisions like paragraphs and pages. They include characters
such as record separator (RS) and file separator (FS).
2. The communication control characters are useful during the transmission of text between remote terminals.
Examples of communication control characters are STX (start of text) and ETX (end of text), which are
used to frame a text message when transmitted through a communication medium.
INPUT-OUTPUT INTERFACE
Input-output interface provides a method for transferring information between internal storage and external
I/O devices.
Peripherals connected to a computer need special communication links for interfacing them with the
central processing unit.
The purpose of the communication link is to resolve the differences that exist between the central
computer and each peripheral. The major differences are:
1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is different
from the operation of the CPU and memory, which are electronic devices. Therefore, a conversion of
signal values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and
consequently, a synchronization mechanism may be need.
3. Data codes and formats in peripherals differ form the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and each must be controlled so as not
to disturb the operation of other peripherals connected to the CPU.
To resolve these differences, computer systems include special hardware components between the CPU
and peripherals to supervise and synchronize all input and output transfers.
These components are called interface units because they interface between the processor bus and the
peripheral device. In addition, each device may have its own controller that supervises the operations of
the particular mechanism in the peripheral.
I/O
BUS
AND
INTERFACE
MODULES
The I/O bus from the processor is attached to all peripheral interfaces. To communicate with a particular
device, the processor places a device address on the address lines.
Each interface attached to the I/O bus contains an address decoder that monitors the address lines. When
the interface detects its own address, it activates the path between the bus lines and the device that it
controls.
3. At the same time that the address is made available in the address lines, the processor provides a function
code in the control lines. The interface selected responds to the function code and proceeds to execute it.
The function code is referred to as an I/O command and is in essence an instruction that is executed in the
interface and its attached peripheral unit.
There are four types of commands that an interface may receive. They are classified as control, status,
status, data output, and data input.
A control command is issued to activate the peripheral and to inform it what to do.
A status command is used to test various status conditions in the interface and the peripheral.
A data output command causes the interface to respond by transferring data from the bus into one of its
registers.
The data input command is the opposite of the data output. In this case the interface receives an item of
data from the peripheral and places it in its buffer register. The processor checks if data are available by
means of a status command and then issues a data input command.
The interface places the data on the data lines, where they are accepted by the processor.
I/O VERSUS MEMORY BUS
In addition to communicating with I/O, the processor must communicate with the memory unit.
Like the I/O bus, the memory bus contains data, address, and read/write control lines.
There are three ways that computer buses can be used to communicate with memory and I/O:
1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.
In the first method, the computer has independent sets of data, address, and control buses, one for
accessing memory and the other for I/O. This is done in computers that provide a separate I/O processor
(IOP) in addition to the central processing unit (CPU). The memory communicates with both the CPU and
the IOP through a memory bus. The IOP communicates also with the input and output devices through a
separate I/O bus with its own address, data and control lines.
The purpose of the IOP is to provide an independent pathway for the transfer of information between
external devices and internal memory.
ISOLATED VERSUS MEMORY-MAPPED I/O
Many computers use one common bus to transfer information between memory or I/O and the CPU.
The distinction between a memory transfer and I/O transfer is made through separate read and write lines.
The I/O read and I/O write control lines are enabled during an I/O transfer. The memory read and memory
write control lines are enabled during a memory transfer.
In the isolated I/O configuration, the CPU has distinct input and output instructions, and each of these
instructions is associated with the address of an interface register.
When the CPU fetches and decodes the operation code of an input or output instruction, it places the
address associated with the instruction into the common address lines.
4. At the same time, it enables the I/O read (for input) or I/O write (for output) control line. This informs the
external components that are attached to the common bus that the address in the address lines is for an
interface register and not for a memory word. On the other hand, when the CPU is fetching an instruction
or an operand from memory, it places the memory address on the address lines and enables the memory
read or memory write control line. This informs the external components that the address is for a
memory word and not for an I/O interface.
ASYNCHRONOUS DATA TRANSFER
The internal operations in a digital system are synchronized by means of clock pulses supplied by a
common pulse generator.
Two units, such as a CPU and an I/O interface, are designed independently of each other. If the registers in
the interface share a common clock with the CPU registers, the transfer between the two units is said to be
synchronous.
In most cases, the internal timing in each unit is independent from the other in that each uses its own
private clock for internal registers. In that case, the two units are said to be asynchronous to each other.
This approach is widely used in most computer systems.
Asynchronous data transfer between two independent units requires that control signals be transmitted
between the communicating units to indicate the time at which data is being transmitted.
One way of achieving this is by means of a strobe pulse supplied by one of the units to indicate to the other
unit when the transfer has to occur.
Another method commonly used is to accompany each data item being transferred with a control signal
that indicates the presence ofdata in the bus. The unit receiving the data item responds with another control
signal to acknowledge receipt of the data. This type of agreement between two independent units is
referred to as handshaking.
STROBE CONTROL
The strobe control method of asynchronous data transfer employs a single control line to time each
transfer. The strobe may be activated by either the source or the destination unit.
The data bus carries the binary information from source unit to the destination unit.
The strobe is a single line that informs the destination unit when a valid data word is available in the bus
5. In this case the destination unit activates the strobe pulse, informing the source to provide the data. The
source unit responds by placing the requested binary information on the data bus. The data must be valid
and remain in the bus long enough for the destination unit to accept it.
In many computers the strobe pulse is actually controlled by the clock pulses in the CPU.
The CPU is always in control of the buses and informs the external units how to transfer data.
HANDSHAKING
The disadvantage of the strobe method is that the source unit that initiates the transfer has no way of
knowing whether the destination unit has actually received the data item that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the source unit has
actually placed the data on the bus.
The handshake method solves this problem by introducing a second control signal that provides a reply to
the unit that initiates the transfer.
The basic principle of the two-write handshaking method of data transfer is as follows:
One control line is in the same direction as the data flow in the bus from the source to the
destination. It is used by the source unit to inform the destination unit whether there are valued
data in the bus. The other control line is in the other direction from the destination to the source.
It is used by the destination unit to inform the source whether it can accept data. The sequence of
control during the transfer depends on the unit that initiates the transfer.
The source unit initiates the transfer by placing the data on the bus and enabling its data valid signal. The
data accepted signal is activated by the destination unit after it accepts the data from the bus. The source
unit then disables its data valid signal, which invalidates the data on the bus. The destination unit then
disables its data accepted signal and the system goes into its initial state. The source dies not send the next
data item until after the destination unit shows its readiness to accept new data by disabling its data
accepted signal.
6. MODES OF TRANSFER
Data transfer between the central computer and I/O devices may be handled in a variety of modes. Some
modes use the CPU as an intermediate path; other transfer the data directly to and from the memory unit.
Data transfer to and from peripherals may be handled in one of three possible modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
Programmed I/O operations are the result of I/O instructions written in the computer program. Each data
item transfer is initiated by an instruction in the program.
In the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that it is ready
for data transfer. This is a time-consuming process since it keeps the processor busy needlessly.
It can be avoided by using an interrupt facility and special commands to inform the interface to issue an
interrupt request signal when the data are available from the device. In the meantime the CU can proceed
to execute another program. The interface meanwhile keeps monitoring the device. When the interface
determines that the device is ready for data transfer, it generates an interrupt request to the computer.
In direct memory access (DMA), the interface transfers data into and out of the memory unit through the
memory bus. The CPU initiates the transfer by supplying the interface with the starting address and the
number of words needed to be transferred and then proceeds to execute other tasks. When the transfer is
made, the DMA requests memory cycles through the memory bus. When the request is granted by the
memory controller, the DMA transfers the data directly into memory.
7. PRIORITY INTERRUPT
Data transfer between the CPU and an I/O device is initiated by the CPU. However, the CPU cannot start
the transfer unless the device is ready to communicate with the CPU. The readiness of the device can be
determined from an interrupt signal.
The CPU responds to the interrupt request by storing the return address from PC into a memory stack and
then the program branches to a service routine that processes the required transfer.
A priority interrupts is a system that establishes a priority over the various sources to determine which
condition is to be serviced first when two or more request arrive simultaneously.
The system may also determine which conditions are permitted to interrupt the computer while another
interrupt is being serviced.
Higher-priority interrupt levels are assigned to request which, if delayed of interrupted, could have serious
consequences. Devices with high-speed transfers such as keyboards receive low priority. When two
devices interrupt the computer at the same time, the computer services the devices interrupt the computer
at the same time, the computer services the device, with the higher priority first.
Establishing the priority of simultaneous interrupts can be done by software or hardware.
A polling procedure is used to identify the highest-priority source by software means.
8. In this method there is one common branch address for all interrupts.
The order in which they are tested determines the priority of each interrupt. The highest-priority source is
tested first, and if its interrupt signal is on, control branches to a service routine for this source. Otherwise,
the next-lower-priority source is tested, and so on.
The disadvantage of the soft ware method is that if there are many interrupts, the time required to poll
them can exceed the time available to service the I/O device. In this situation a hardware priority-interrupt
unit can be used to speed up the operation.
A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment.
It accepts interrupt requests from many sources, determines which of the incoming requests has the highest
priority, and issues an interrupt request to the computer based on this determination.
no polling is required because all the decisions are established by the hardware priority-interrupt unit. The
hardware priority function can be established by either a serial or a parallel connection of interrupt lines.
The serial connection is also known as the daisy chaining method.
DAISY-CHAINING PRIORITY
The daisy-chaining method of establishing priority consists of a serial connection of all devices that
request an interrupt. The device with the highest priority is placed in the first position, followed by lowerpriority devices up to the device with the lowest priority, which is placed last in the chain.
T’lkhis method of connection between three devices and the CPU is shown in Fig. 6-10
The interrupt request line is common to all devices and forms a wired logic connection. If any device has
its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the
interrupt input in the CPU.
When no interrupts are pending, the interrupt line stays in the high-level state and no interrupts are
recognized by the CPU.
This is equivalent to a negative logic OR operation. The CPU responds to an interrupt request by enabling
the interrupt acknowledge line. This signal is received by device 1 at its PI (priority in) input. The
9. acknowledge signal passes on to the next device through the PO (priority out) output only if device 1 is not
requesting an interrupt.
If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in
the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the
CPU to use during the interrupt cycle.
A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower priority device that
the acknowledge signal has been blocked.
A device that is requesting an interrupt and has a 1 in its PI input will intercept the acknowledge signal by
placing a 0 in its PO output.
If the device does not have pending interrupts, it transmits the acknowledge signal to the next device
PARALLEL PRIORITY INTERRUPT
The parallel priority interrupt method uses a register whose bits are set separately by the interrupt signal
from each device.
Priority is established according to the position of the bits in the register.
In addition to the interrupt register the circuit may include a mask register whose purpose is to control the
status of each interrupt request. The mask register can be programmed to disable lower-priority interrupts
while a higher-priority device is being serviced.
It can also provide a facility that allows a high-priority device to interrupt the CPU while a lower-priority
device is being serviced.
DIRECT MEMORY ACCESS (DMA)
The transfer of data between a fast storage device such as magnetic disk and memory is often limited by
the speed of the CPU.
Removing the CPU from the path and letting the peripheral device manage the memory buses directly
would improve the speed of transfer.
This transfer technique is called direct memory access (DMA).
During DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes
over the buses to manage the transfer directly between the I/O device and memory.
Data Transfer mediated by CPU
10. Data Transfer without CPU
DMA Controller:
The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O device.
In addition, it needs an address register, a word count register, and a set of address lines.
Figure 6.14 shows the block diagram of a typical DMA controller.
Components of DMA Controller
The unit communicates with the CPU via the data bus and control lines.
The registers in the DMA are selected by the CPU through the address bus by enabling the DS (DMA
select) and RS (register select) inputs.
When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers through the data
bus to read from or write to the DMA registers.
When BG = 1, the CPU has relinquished the buses and the DMA can communicate directly with the
memory by specifying an address in the address bus and activating the RD or WR control.
11. The DMA controller has three registers: an address register, a word count register, and a control register.
The address register contains an address to specify the desired location in memory.
The word count register is incremented after each word that is transferred to memory. This register is
decremented by one after each word transfer and internally tested for zero.
The control register specifies the mode of transfer. All registers in the DMA appear to the CPU as I/O
interface registers. Thus the CPU can read from or write into the DMA registers under program control via
the data bus.
Functionality of DMA Controller
The DMA is first initialized by the CPU. After that, the DMA starts and continues to transfer data between
memory and peripheral unit until an entire block is transferred.
The CPU initializes the DMA by sending the following information through the data bus:
1. The starting address of the memory block where data are available (for read) or where data are to be
stored (for write)
2. The word count, which is the number of words in the memory block
3. Control to specify the mode of transfer such as read or write
4. A control to start the DMA transfer
The starting address is stored in the address register. The word count is stored in the word count register,
and the control information in the control register. Once the DMA is initialized, the CPU stops
communicating with the DMA unless it receives an interrupt signal or if it wants to check how many
words have been transferred.
DMA Transfer
- The CPU communicates with the DMA through the address and data buses
- The DMA has its own address, which activates the DS and RS lines.
- The CPU initializes the DMA through the data bus.
- Once the DMA receives the start control command, it can start the transfer between the peripheral
device and the memory
- When the peripheral device sends a DMA request, the DMA controller activates the BR line,
informing the CPU to relinquish the buses.
- The CPU responds with its BG line, informing the DMA that its buses are disabled.
- The DMA then puts the current value of its address register into the address bus, initiates the RD
or WR signal, and sends a DMA acknowledge to the peripheral device.
- When BG = 0, the RD and WR are input lines allowing the CPU to communicate with the internal
DMA registers.
- When BG = 1, the RD and WR and output lines from the DMA controller to the random-access
memory to specify the read or write operation for the data.
- When the peripheral device receives a DMA acknowledge, it puts a word in the data us (for write)
or receives a word from the data bus (for read).
- Thus the DMA controls the read or write operations and supplies the address for the memory. The
peripheral unit can then communicate with memory through the data bus for direct transfer
between the two units while the CPU is momentarily disabled.