Lecture 36
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This document provides an overview of input/output organization and various input/output techniques including peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer such as programmed I/O, interrupt-initiated I/O, and direct memory access. It also discusses universal asynchronous receiver transmitter chips, first-in first-out buffers, and compares different modes of transfer including their advantages and disadvantages.
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This document summarizes key points from Chapter 3 of William Stallings' book "Computer Organization and Architecture". It discusses the top-level view of computer function and interconnection. The main components of a computer are the control unit, arithmetic logic unit, main memory, and input/output. Programs are sequences of steps that are executed via control signals. Buses are used to connect these components and transfer data, addresses, and control signals. Interrupts allow other devices to interrupt normal program execution.
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This document summarizes key points from Chapter 3 of William Stallings' book "Computer Organization and Architecture". It discusses the top-level view of computer function and interconnection. The main components of a computer are the control unit, arithmetic logic unit, main memory, and input/output. Programs are sequences of steps that are executed via control signals. Buses are used to connect these components and transfer data, addresses, and control signals. Interrupts allow other devices to interrupt normal program execution.
Control unit
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03 top level view of computer function and interconnection.ppt.enc
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03. top level view of computer function & interconnection
03. top level view of computer function & interconnection
Chapter 3 - Top Level View of Computer / Function and Interconection
Chapter 3 - Top Level View of Computer / Function and Interconection
03 top level view of computer function and interconnection
03 top level view of computer function and interconnection
top level view of computer function and interconnection
top level view of computer function and interconnection
Wk 4 top_level_view_of_computer_function_and_interconnection
Wk 4 top_level_view_of_computer_function_and_interconnection
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This document discusses input/output organization and peripheral devices. It covers the following key points in 3 sentences:
Peripheral devices allow input and output between the computer and external environment. The document outlines different types of input devices, output devices, and input/output devices. It also discusses the input/output interface which provides communication between the CPU, memory, and peripheral devices by resolving differences in data formats, transfer rates, and operating modes.
Computer organization part 2
The document discusses input-output organization and direct memory access. It describes how I/O devices are connected to computers through interfaces that handle synchronization and conversion between the CPU and peripherals. It also explains different I/O transfer modes like programmed I/O, interrupt-driven I/O, and direct memory access (DMA). DMA allows high-speed transfer of data directly between memory and an I/O device without CPU involvement by using bus request/grant signals to gain control of the buses.
03 Buses
The document discusses computer system buses and their role in connecting central processing units to memory and input/output devices. Buses transfer data, addresses, and control signals between components. Common bus types include data buses to transfer data, address buses to specify memory locations, and control buses that coordinate timing. Interrupt signals can suspend normal processing to handle higher priority events. Modern buses like PCI use arbitration to allow shared access among devices.
Counit2 2
The document discusses the basic components and operation of computers. It describes how a central processing unit (CPU) works with memory and input/output devices using control signals and buses to execute instructions. The CPU fetches and executes instructions in cycles, and can be interrupted by external events using interrupt signals. Buses connect the different components and allow for communication between the CPU, memory, and input/output devices.
Interfacingiodevice
The document discusses different methods for accessing I/O devices in computer systems. It describes how I/O devices connect to the processor through ports and can be accessed using IN and OUT instructions. There are three main strategies for I/O - polled I/O, interrupt-driven I/O, and direct memory access (DMA). Polled I/O involves the processor continuously checking devices for readiness, interrupt-driven I/O uses interrupts to signal readiness, and DMA allows direct transfer between device and memory without involving the CPU. The strategies differ in transfer rates, latency, and CPU overhead.
ch -6 IO.pptx
The document discusses different modes of data transfer between the central processing unit (CPU) and input/output (I/O) devices, including programmed I/O, interrupt-initiated I/O, and direct memory access (DMA). It describes how each mode functions, such as the CPU monitoring flags in programmed I/O or an I/O device interrupting the CPU when ready in interrupt-initiated I/O. The document also covers priority interrupts, DMA controllers that allow direct transfers between memory and I/O devices, and input/output processors that offload I/O tasks from the CPU.
Ch 3 95
The document discusses computer system buses and their role in connecting different components of a computer system. It describes the functions of common types of buses like data, address, and control buses. It also explains bus arbitration and timing, interrupt handling, and examples of specific bus architectures like PCI buses. Buses provide a communication pathway that allows the central processing unit (CPU) to transmit data and control signals to other devices like memory and input/output components.
Chapter 6
The document discusses various methods for input/output (I/O) in computer systems, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes I/O modules that interface peripherals with the CPU and memory. Common I/O techniques include programmed I/O where the CPU directly controls I/O, interrupt-driven I/O where devices interrupt the CPU, and DMA where an I/O controller handles data transfers without CPU involvement. Specific I/O interfaces like SCSI and FireWire are also overviewed.
Chapter 4
The document discusses input/output (I/O) problems in computer systems and solutions to those problems. Some key issues addressed are the variety of peripheral devices with different data rates and formats, and the mismatch between peripheral and processor speeds. The document describes I/O modules that interface between the CPU/memory and peripherals. I/O modules handle control, buffering, error detection and allow different I/O techniques like programmed I/O, interrupt-driven I/O and direct memory access (DMA) to transfer data efficiently.
Computer function-and-interconnection 3
The document provides a top-level overview of the basic components and functions of a computer system. It describes how a central processing unit (CPU) works with memory and input/output devices via buses to execute instructions. Interrupts allow efficient processing by suspending the current program to handle higher priority tasks or events before resuming the original program.
Computer function-and-interconnection 3
The document provides a top-level overview of the function and interconnection of computer components. It describes how a program is executed through an instruction cycle of fetching and executing instructions. It explains the role of the control unit and how different computer components like the CPU, memory, and I/O devices are interconnected through buses to allow the transfer of data and instructions. Interrupts provide a way to improve processing efficiency and allow different tasks to be interleaved.
Input output in computer Orgranization and architecture
Input Output Ports, Input Output Mapping, Memory Map Techniques, Interrupt Driven Input Output, DMA based Input Output, Input Output Processor/Channels
CH03-COA10e_ComputerFun5656565656565ction.pdf
This document discusses computer organization and architecture. It provides an overview of the von Neumann architecture, which is a simple structure capable of executing any program given a properly programmed control unit. The key aspects of the von Neumann architecture are that data and instructions are stored in a single memory, the contents of memory can be addressed by location, and execution occurs sequentially from one instruction to the next. The document also describes the typical components of a computer system, including the processor, memory, and input/output devices, and how they are interconnected using a shared bus system with separate address, data, and control lines.
Input - output organzation
This document discusses input-output (I/O) organization in a computer system. It describes various I/O interface techniques including programmed I/O, interrupt-initiated I/O, and direct memory access (DMA). It also discusses I/O bus and interface modules, I/O versus memory bus, modes of data transfer, interrupt priorities, and the role of an input-output processor (IOP). The IOP allows direct communication between I/O devices and memory using DMA to facilitate efficient transfer of data.
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Input output in computer Orgranization and architecture
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Lecture 44
This document discusses memory organization and management techniques. It covers memory hierarchy including main memory, auxiliary memory, cache memory and virtual memory. It then describes memory management hardware and its basic functions like dynamic storage relocation and memory protection. The document explains segmentation as a memory management scheme that supports variable sized segments. It provides an example to illustrate segmentation and how multiple users can share segments. Finally, it discusses combining segmentation with paging to create a segmented page system and how page and segment tables are implemented.
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This document discusses memory organization and virtual memory. It describes how virtual memory uses a memory mapping table to map virtual addresses to physical addresses, giving the illusion of a larger memory. It discusses page tables and how they map address spaces to memory spaces using pages. It also covers page faults, how they are handled by the operating system, and different page replacement algorithms like FIFO, OPT, and LRU used when a page fault occurs and a frame needs to be selected for replacement.
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The document discusses different types of memory organization and caching techniques used in computer systems. It describes the memory hierarchy including main memory, auxiliary memory, and cache memory. It discusses the locality of reference property and how cache memory exploits this to improve performance. It then summarizes different cache mapping techniques like direct mapping, set-associative mapping, and associative mapping. It also covers cache operations and replacement policies. Finally, it discusses write policies for caches including write-through and write-back.
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This document discusses various methods of input/output organization and asynchronous data transfer. It covers peripheral devices, input-output interfaces, asynchronous and synchronous data transfer, strobe control using a single control line, handshaking using two control signals, source and destination initiated transfers, and asynchronous serial transfer using start and stop bits.
Lecture 21
The document discusses the control unit of a computer. It covers control memory, microinstruction sequencing, the microinstruction format, design of the control unit, and the address sequencer. The address sequencer uses a multiplexer to select the next address from various sources like incrementing the current address, returning from a subroutine, branching to a new address, or mapping from the machine instruction.
Lecture 18
This document discusses input/output and interrupt handling in a basic computer system. It describes the I/O configuration including input and output registers and flags. It explains programmed and interrupt-initiated I/O, with the interrupt cycle storing the return address and branching to an interrupt service routine before returning to the main program. Input/output and interrupt instructions are also outlined.
Lecture 17
This document provides details about memory reference instructions in a computer system. It discusses instructions like AND, ADD, LDA, STA, BUN, BSA, and ISZ. The timing and execution of each instruction is explained across multiple timing signals. Memory reference instructions first read the operand from memory using the address stored in the register AR, then perform the operation whether it be logical, arithmetic, or flow control. The result is stored back in registers or memory as defined by the instruction. Diagrams are included to illustrate the instruction cycle and flow of memory reference instructions.
Lecture 16
This document discusses the instruction cycle and types of instructions in a basic computer system. It includes a flow chart showing the stages of the instruction cycle from fetching the instruction code to executing different instruction types. Register reference instructions are identified when the opcode field decodes to a register reference. These instructions perform operations on the accumulator register and condition codes like addition, logical shifts, conditional jumps. Memory reference and input/output instructions are also discussed along with determining the instruction type from the opcode fields.
Lecture 15
The document describes the basic instruction cycle of a computer. It explains that an instruction is executed in four steps: 1) fetching the instruction from memory, 2) decoding the instruction, 3) reading the effective address from memory if needed, and 4) executing the instruction. It then repeats this cycle for the next instruction. The document also provides more details on the fetch and decode portion of the cycle, showing how the program counter addresses memory to fetch the instruction and load it into the instruction register for decoding.
Lecture 14
This document summarizes a lecture on computer organization and design. It discusses the control unit and how it translates machine instructions into microoperations through either hardwired control or microprogrammed control. It then focuses on the timing and control of the basic computer's control unit. Specifically, it describes how an instruction register, decoders, sequence counter, and combinational logic are used to generate the necessary control signals through a clock and timing signals.
Lecture 13
This document summarizes a lecture on basic computer instructions. It discusses the format of basic computer instructions, including memory-reference instructions, register-reference instructions, and input-output instructions. Examples of specific instruction codes are provided, such as AND, ADD, LDA, STA, BUN, and INP. The completeness of an instruction set is also briefly discussed in terms of including functional, transfer, control, and input/output instructions.
Lecture 12
This document describes the basic computer organization and design over 5 lectures. It discusses the registers in the basic computer like the program counter, instruction register, data register, accumulator, and input/output registers. The registers are connected via a common bus system to allow transfer of data and instructions. The bus is controlled by 3 lines that select which register or memory the bus inputs from. This design allows the computer to perform operations by loading data from memory or registers onto the bus and then into other registers or memory as specified by the instruction code.
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Lecture 36
- 1. Input/Output Organization 1 Lecture 36 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Overview Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes of Transfer Priority Interrupt Direct Memory Access Input-Output Processor Serial Communication
- 2. Input/Output Organization 2 Lecture 36 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Universal Asynchronous Receiver Transmitter A typical asynchronous communication interface available as an IC Transmitter Register - Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits Chip select I/O read I/O write CS RS RD WR Timing and Control Bus buffers Bidirectional data bus Transmitter register Control register Status register Receiver register Shift register Transmitter control and clock Receiver control and clock Shift register Transmit data Transmitter clock Receiver clock Receive data CS RS Oper. Register selected 0 x x None 1 0 WR Transmitter register 1 1 WR Control register 1 0 RD Receiver register 1 1 RD Status register InternalBus
- 3. Input/Output Organization 3 Lecture 36 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT First In First Out Buffer * Input data and output data at two different rates * Output data are always in the same order in which the data entered the buffer. * Useful in some applications when data is transferred asynchronously 4 x 4 FIFO Buffer (4 4-bit registers Ri), 4 Control Registers(flip-flops Fi, associated with each Ri) 4-bit register S R F F' 1 1 4-bit register S R F F' 2 2 4-bit register S R F F' 3 3 4-bit register S R F F' 4 4 F F S R F F' S R Clock Clock Clock Clock Data output Output ready Delete Data input Insert Input ready Master clear R1 R2 R3 R4
- 4. Input/Output Organization 4 Lecture 36 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Modes of Transfer – Programmed I/O 3 different Data Transfer Modes between the central computer(CPU or Memory) and peripherals; • Program-Controlled I/O • Interrupt-Initiated I/O • Direct Memory Access (DMA) Program-Controlled I/O(Input Dev to CPU) Polling or Status Checking • Continuous CPU involvement • CPU slowed down to I/O speed • Simple • Least hardware Read status register Check flag bit flag Read data register Transfer data to memory Operation complete? Continue with program = 0 = 1 yes no CPU Data bus Address bus I/O read I/O write Interface Data register Status register F I/O bus Data valid Data accepted I/O device
- 5. Input/Output Organization 5 Lecture 36 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Modes of Transfer – Interrupted I/O & DMA DMA (Direct Memory Access) - Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc. - DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device - CPU initializes the DMA controller by sending a memory address and the number of words to be transferred - Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks - Polling takes valuable CPU time - Open communication only when some data has to be passed -> Interrupt. - I/O interface, instead of the CPU, monitors the I/O device - When the interface determines that the I/O device is ready for data transfer, it generates an Interrupt Request to the CPU - Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing Interrupt Initiated I/O