The document describes the verification of a UART IP core using UVM. It provides details about the key features of UART including the Wishbone interface and baud rate generation. The document outlines the UVM testbench architecture and various test cases verified, including half duplex mode, full duplex mode, loopback mode, and error conditions. Waveforms are shown for different test cases, inputs, and outputs.

1. UART IP VERIFICATION
By
Naveen C
Batch-43

2. Contents
What is UART?
Introduction
Key Feature of UART
UVM TB Architecture
Test Cases verified
Waveforms
2

3. Introduction
The Universal Asynchronous Receiver Transmitter
or simple UART is one of the common peripheral
found on microcontrollers (MCU) widely used for
communication with the external devices and
systems.
Modules, ASIC's , and PC's are among the devices
that the microcontroller can communicate to
through the UART.

4. UART

5. Features
•WISHBONE interface in 8-bit data bus mode or 32-bit
data bus mode.
•FIFO mode is supported.
•An on-chip bit rate (baud rate) generator to control
transmit and receive data rate.

7. Divisor Latch Byte
Calculating Divisor Latch Byte:
Divisor latch Byte= (input clock speed) / (16 x baud rate)
Two different input clock frequency taken are 50MHz and
25MHz
Baud rate = 1,00,000

8. Operation
o Upon a write to the data input bus WB_DAT_I, the
core will automatically serialize and emit the byte
on the Trx_PAD_O.
o According to the interrupt we have enabled the
int_o goes high whenever an interrupt is available.
o Upon reception of a bit stream on Srx_PAD_O, the
core will unserialise the information and check for
error and it will send the received data to receiver
FIFO.
o This announce that the received byte can be read
on the data output bus WB_DAT_O. As soon as
the fifo trigger level reached and its get enabled the
Int_o will get high and can be read at the output
port.

9. Data framing…

10. UVM Architecture

11. Modes of Operation
Three main modes of operation
 Half Duplex mode
 Full Duplex Mode
 Loop Back Mode

12. Half Duplex Mode

13. Full Duplex Mode
Transmission is bidirectional.
UART 1 Transmits and UART 2 Receives.
meanwhile UART 2 Transmits and UART 1
receives.

14. Loop Back Mode

15. TEST CASES
Half Duplex Mode
Full Duplex Mode
Dual Loop Back Mode
Parity Error
Break interrupt
Overrun condition
Framing Error
Timeout Indication
Transmitter holding register empty
Setting LCR to Transmitting 5 bits data
Setting LCR to Transmitting 6 bits data
Setting LCR to Transmitting 7 bits data

16. Half Duplex Mode INPUT

17. Half Duplex Mode
OUTPUT

18. Full Duplex Mode INPUT

19. Full Duplex Mode
OUTPUT

20. Loop Back Mode INPUT

21. Loop Back Mode
OUTPUT

22. Parity Error INPUT

23. Parity Error OUTPUT

24. Break interrupt INPUT

25. Break Interrupt OUTPUT

26. Overrun Error INPUT

27. Overrun Error OUTPUT

28. Framing Error INPUT

29. Framing Error OUTPUT

30. Timeout Indication
INPUT

31. Timeout Indication
OUTPUT

32. Transmitter Holding Register Empty
INPUT

33. Transmitter Holding Register Empty
OUTPUT

34. THANK YOU