AMBA AHB is a bus interface suitable for high-performance synthesizable designs. It defines the interface between components, such as masters, interconnects, and slaves.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
Advance Microcontroller Bus Architecture(AMBA).
this is a advance bus architecture. it is defined by ARM.
all the content is taken from http://infocenter.arm.com/ website.
AXI is an on-chip, point to point communication protocol. It is used as a high-performance bus in various IP or SoC Systems. It is used for connecting high-performance processors with memory.
Verification of amba axi bus protocol implementing incr and wrap burst using ...eSAT Journals
Abstract This paper describes the development of verification environment for AMBA AXI (Advanced Extensible Interface) protocol using
System Verilog. AXI supports high performance, high-frequency system designs. It is an On-Chip communication protocol. It is
suitable for high-bandwidth and high frequency designs with minimal delays. It provides flexibility in the implementation of
interconnect architectures and avoid use of complex bridges. It is backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are that it consists of separate address, control and data phases. It support unaligned data
transfers using byte strobes. It requires only start address to be issued in a burst-based transaction. It has separate read and write
data channels that provide low-cost Direct Memory Access (DMA). This paper is aimed at the verification of various burst type
transaction (INCR and WRAP) of the AXI bus protocol and the Verification Environment is built using System Verilog coding[1].
Keywords: AMBA AXI, INCR, Wrap Burst, System Verilog
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs
Diagnostic Access of AMBA-AHB Communication Protocolsidescitation
In this paper a diagnostic access of AMBA AHB communication protocols is
designed and implemented. AMBA AHB communication protocols are designed using
master slave topology. A core is designed for implementation of communication protocols
between master and slave device to perform efficient write operation. The process involves
design and implementation of a master unit and a slave unit. Further a test bench is
designed to simulate the communication between master and slave. A synthesis report of the
process is generated using VHDL and XILINX. The process is configured for Address and
Data bus of 32 bit width. The designed AMBA AHB communication protocol between
master and single slave supports technology independent data transfer between high band
width and high clock frequency multiprocessors and multi-CPU based embedded systems
like arm processors and low bandwidth peripherals like IC based processors, standard
macro cells, flash memory etc. The features required for high performance, high clock
frequency systems including burst transfers, single clock edge operations, non–tristate
implementation and wider data bus configuration are implemented in the design.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
Advance Microcontroller Bus Architecture(AMBA).
this is a advance bus architecture. it is defined by ARM.
all the content is taken from http://infocenter.arm.com/ website.
AXI is an on-chip, point to point communication protocol. It is used as a high-performance bus in various IP or SoC Systems. It is used for connecting high-performance processors with memory.
Verification of amba axi bus protocol implementing incr and wrap burst using ...eSAT Journals
Abstract This paper describes the development of verification environment for AMBA AXI (Advanced Extensible Interface) protocol using
System Verilog. AXI supports high performance, high-frequency system designs. It is an On-Chip communication protocol. It is
suitable for high-bandwidth and high frequency designs with minimal delays. It provides flexibility in the implementation of
interconnect architectures and avoid use of complex bridges. It is backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are that it consists of separate address, control and data phases. It support unaligned data
transfers using byte strobes. It requires only start address to be issued in a burst-based transaction. It has separate read and write
data channels that provide low-cost Direct Memory Access (DMA). This paper is aimed at the verification of various burst type
transaction (INCR and WRAP) of the AXI bus protocol and the Verification Environment is built using System Verilog coding[1].
Keywords: AMBA AXI, INCR, Wrap Burst, System Verilog
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs
Diagnostic Access of AMBA-AHB Communication Protocolsidescitation
In this paper a diagnostic access of AMBA AHB communication protocols is
designed and implemented. AMBA AHB communication protocols are designed using
master slave topology. A core is designed for implementation of communication protocols
between master and slave device to perform efficient write operation. The process involves
design and implementation of a master unit and a slave unit. Further a test bench is
designed to simulate the communication between master and slave. A synthesis report of the
process is generated using VHDL and XILINX. The process is configured for Address and
Data bus of 32 bit width. The designed AMBA AHB communication protocol between
master and single slave supports technology independent data transfer between high band
width and high clock frequency multiprocessors and multi-CPU based embedded systems
like arm processors and low bandwidth peripherals like IC based processors, standard
macro cells, flash memory etc. The features required for high performance, high clock
frequency systems including burst transfers, single clock edge operations, non–tristate
implementation and wider data bus configuration are implemented in the design.
I am working as a Assistant Professor in ITS, Ghaziabad.This is very useful to U.P.Technical University,Uttrakhand Technical University students. Give feedback to rakeshroshan@its.edu.in
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
Note : To get more understanding Recommending to see first section - Low power in vlsi with upf basics part 1
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
2. Introduction:
• AMBA AHB is a bus interface suitable for high-performance synthesizable designs. It defines
the interface between components, such as masters, interconnects, and slaves.
• AHB also supports multi-master designs by the use of an interconnect component that
provides arbitration and routing signals from different masters to the appropriate slaves.
• AMBA AHB implements the features required for high-performance, high clock frequency
systems including:
• Burst transfers.
• Single clock-edge operation.
• Non-tristate implementation.
• Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.
3. Master Interface:
A master provides address and control information to initiate read and write
operations
4. AHB Block Diagram shows Multiple master AHB system design with Arbiter
5. Global Signals :
Master signals :
Signal Name Destination Description
HCLK Clock source
The bus clock times all bus transfers. All signal timings are related
to the rising edge of HCLK.
HRESETn Reset controller
The bus reset signal is active LOW and resets the system and the
bus.During reset all slaves must ensure that HREADYOUT is HIGH.
Signal Name Destination Description
HADDR[31:0] Slave and decoder The 32-bit system address bus.
HBURST[2:0] Slave
The burst type indicates if the transfer is a single transfer or forms
part of a burst.
Signal Description :
6. Signal Description : Conti...
Master signals :
Signal Name Destination Description
HMASTLOCK Slave
When HIGH, indicates that the current transfer is part of a locked
sequence. Locked transfer is used to maintain the integrity of a
semaphore.
HPROT[3:0] Slave
The protection control signals provide additional information
about a bus access and indicate how an access should be handled
within a system. The signals indicate if the transfer is an opcode
fetch or data access, and if the transfer is a privileged mode
access or a user mode access.
HPROT[6:4] Slave
The 3-bit extension of the HPROT signal that adds extended
memory types. This signal extension is supported if the AHB5
Extended_Memory_Types property is True.
HSIZE[2:0] Slave
Indicates the size of the transfer, that is typically byte, halfword,
or word. The protocol allows for larger transfer sizes up to a
maximum of 1024 bits.
7. Signal Description : Conti...
Master signals :
Signal Name Destination Description
HNONSEC Slave and decoder
Indicates that the current transfer is either a Non-secure transfer
or a Secure transfer. This signal is supported if the AHB5
Secure_Transfers property is True.
HEXCL
Exclusive Access
Monitor
Exclusive Transfer. Indicates that the transfer is part of an
Exclusive access sequence. This signal is supported if the AHB5
Exclusive_Transfers property is True.
HMASTER[3:0]
Exclusive Access
Monitor and slave
Master identifier. Generated by a master if it has multiple
Exclusive capable threads. Modified by an interconnect to ensure
each master is uniquely identified. This signal is supported if the
AHB5 Exclusive_Transfers property is True.
HWDATA[31:0]a Slave
The write data bus transfers data from the master to the slaves
during write operations. A minimum data bus width of 32 bits is
recommended. However, this can be extended to enable higher
bandwidth operation.
8. Signal Description : Conti...
Master signals :
Signal Name Destination Description
HTRANS[1:0] Slave
-> IDLE[00] : Indicates that no data transfer is required.
-> BUSY [01]:This transfer type indicates that the master is
continuing with a burst but the next transfer cannot take place
immediately.
-> NONSEQUENTIAL[10]:Indicates a single transfer or the first
transfer of a burst.
-> SEQUENTIAL[11]: The remaining transfers in a burst are
SEQUENTIAL and the address is related to the previous
transfer.
HWRITE Slave
Indicates the transfer direction. When HIGH this signal indicates a
write transfer and when LOW a read transfer.
9. Slave Interface:
A slave responds to transfers initiated by masters in the system. The slave uses the HSELx
select signal from the decoder to control when it responds to a bus transfer. The slave
signals back to the master:
• The completion or extension of the bus transfer.
• The success or failure of the bus transfer.
10. Signal Description :
Slave signals :
Signal Name Destination Description
HRDATA[31:0]a Multiplexor
During read operations, the read data bus transfers data from the
selected slave to the multiplexor. The multiplexor then transfers
the data to the master. A minimum data bus width of 32 bits is
recommended. However, this can be extended to enable higher
bandwidth operation.
HREADYOUT Multiplexor
When HIGH, the HREADYOUT signal indicates that a transfer has
finished on the bus. This signal can be driven LOW to extend a
transfer.
HRESP
Multiplexor
When LOW, the HRESP signal indicates that the transfer status is
OKAY. When HIGH, the HRESP signal indicates that the transfer
status is ERROR.
HEXOKAY
Multiplexor
Exclusive Okay. Indicates the success or failure of an Exclusive
Transfer. This signal is supported if the AHB5 Exclusive_Transfers
property is True.
13. Transfers : Conti...
Transfer Size :
The transfer size set by HSIZE must be less than or equal to the width of the data bus. For
example, with a 32-bit data bus, HSIZE must only use the values 0b000, 0b001, or 0b010.
14. Transfers : Conti...
Burst Operation :
Masters must not attempt to start an incrementing burst that crosses a 1KB address boundary
Masters can perform single transfers using either SINGLE transfer burst or Undefined length
burst that has a burst of length one.