Features, Register Set, Flag Register, Internal Block Diagram, Interrupts of Intel 80286 microprocessor

1. 80286 Microprocessor
SUBMITTED BY
AVIN MATHEW
S2 MCA
M1411

2. Features of 80286
 The Intel 80286 is a high-performance 16-bit microprocessor.
 It has been specially designed for multiuser and multitasking
systems.
 Various versions of 80286 are available that run on 12.5 MHz,10
MHz and 8MHz clock frequencies.
 80286 is upwardly compatible with 8086 in terms of instruction set.
(That is the 8086,8088,80186,80286 CPU family all contain the same
instruction set)

3. Features of 80286 (Cont.)
 The memory management which is an important task of the operating
system is now supported by a hardware unit called memory
management unit.
 The 80286 is the first CPU to incorporate the integrated memory
management unit.
 It has four-level memory protection and support for virtual
memory and operating system
 It is available in variety of pin packages such as 68-pin PLCC (Plastic
Leaded Chip Carrier), Ceramic LCC (Leadless Chip Carrier), and
PGA(Pin Grid Array).

4.  It has 24 address lines and 16 data lines.
 There are two operating modes for 80286
 The real address mode
 The protected virtual memory address mode
 In real address mode the processor can address upto 1MB of physical
memory.
 The virtual address mode is for multiuser/multitasking system. In this
mode of operation the memory management unit can manage upto
1GB of virtual memory.
 In virtual address mode one user cannot interface with the other. Also
users cannot interface with operating system. These features are called
protection.
Features of 80286 (Cont.)

5. Register Set of 80286

6.  The 80286 CPU contains almost the same set of registers, as in 8086,
viz.
 (a) Eight 16-bit general purpose registers
 (b) Four 16-bit segment registers
 (c) Status and control register
 (d) Instruction Register
 The flag register bits D0, D2, D4, D6, D7 and D11 are modified
according to the result of the execution of logical and arithmetic
instructions. These are called status flag bits.

7. 80286 Flag Register

8.  The additional fields available in 80286 flag registers are,
 IOPL-I/O Privilege Field (bits D12 and D13)
 NT - Nested Task flag (bit D14)
 PE - Protection Enable (bit D16)
 MP – Monitor Processor Extension (bit D17)
 Processor Extension Evaluator (bit D19)

9.  Machine Status Flag (MSW) :
 The machine status word consists of four flags. These are –
PE,MP,EM, and TS of the four lower order bits D19 to D16 of
the upper word of the flag register.
 The LMSW and SMSW instructions are available in the
instruction set of 80286 to write and read the MSW in real address
mode.

10. Internal Block Diagram of 80286

11. Internal Block Diagram of 80286
 The CPU may be viewed to contain four functional parts, viz.
 (a) Address Unit (AU)
 (b) Bus Unit (BU)
 (c) Instruction Set (IU)
 (d) Execution Unit (EU)
 The Address Unit (AU) is responsible for calculating the physical address of
instructions and data that CPU wants to access.
 This physical address computed by the address unit is handed over to the Bus
Unit (BU) of the CPU.
 The address latches and drivers in the bus unit transmit the physical address thus
formed over the address bus A0-A23.
 One of the major function of the bus unit is to fetch instruction bytes from the
memory.

12.  The Instruction Unit(IU) accepts instructions from the prefetch
queue and an instruction decoder decodes them one by one.
 The output from the decoding circuit drives a control circuit in the
Execution Unit (EU) is responsible for instructions received from
the decoded instruction queue, which sends the data part of the
instruction over the data bus.

13. Interrupts of 80286
 The interrupts of 80286 may be divided into three categories, viz.
 (a) External or Hardware interrupts
 (b) INT instruction or software interrupts
 (c) Interrupts generated internally by exceptions
 Maskable Interrupt INTR :
 This is a maskable interrupt input pin of which the INT type is to be provided by an
external circuit like an interrupt controller.
 Non-maskable Interrupt :
 NMI has higher priority than the INTR interrupt.
 Whenever this interrupt is received, a vector of value of 02 is supplied internally to
calculate the pointer to the interrupt vector table.
 Once the CPU responds to a NMI request, it does not serve any other interrupt request
(including NMI).

14. Interrupts of 80286
 Single Step Interrupt :
 As in 8086, this is an internal interrupt that comes into action, if the trap flag (TF) of
80286 is set.
 The CPU stops the execution after each instruction cycle so that the register contents
(including flag register), the program status word and memory, etc. may be examined at
the end of each instruction execution.
 Non-maskable Interrupt :
 If more than one interrupt signal occur simultaneously, they are processed according to
the priorities as in the table below