Lecture17
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This document summarizes a lecture on static combinational circuit design. It discusses how to convert AND/OR logic to NAND/NOR logic using DeMorgan's laws. It also discusses designing a 2-input multiplexer using NAND gates. Finally, it covers topics like calculating delay, annotating designs with transistor sizes, modeling parasitic delay, asymmetric gates, skewed gates, and creating a catalog of skewed gates.
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![Design and Implementation of VLSI Systems
(EN0160)
Lecture 17: Static Combinational Circuit Design (1/2)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160](https://image.slidesharecdn.com/lecture17-130227092331-phpapp01/85/Lecture17-1-320.jpg)
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The document discusses multi-level gate circuits and their terminology. It provides examples of realizing functions with AND-OR, OR-AND, OR-AND-OR circuits. It also discusses realizing circuits using only NAND or NOR gates. The procedures for designing two-level and multi-level circuits with NAND and NOR gates are described. Alternative gate symbols and examples of designing circuits to realize multiple functions are also presented.
NAND gate
This document describes the NAND gate, a digital logic gate that implements the NAND logical operation. It has two or more inputs but only one output. The output is HIGH only if at least one of the inputs is LOW, and is LOW only when all inputs are HIGH. NAND gates can be used to implement any Boolean function, and are commonly used to build circuits because they are simple and fast. The document explains how NAND gates can function as NOT, AND, and OR gates and illustrates their pin diagrams and truth tables.
Nyquist adc
This document discusses various types of analog-to-digital converters (ADCs). It describes integrating ADCs which work by integrating the input voltage over time and counting. Successive approximation ADCs work by successively refining the digital output until it approximates the input. Flash ADCs use many comparators in parallel to directly convert the input to a thermometer code. Other ADC types discussed include pipeline, interpolating, algorithmic, and time-interleaved ADCs. Issues in designing flash ADCs like input loading, resistor matching, and noise are also covered.
Noise reduction techniques
Designing Mixed Signal Systems with Noise Reduction Techniques in Mind focused on implementing noise reduction techniques when designing mixed signal systems. The presentation covered sources of noise such as devices, emissions, and traces; techniques to reduce noise like choosing lower noise devices, improving layout, and adding filtering; and applying these techniques across three design revisions to significantly reduce noise. Testing results showed noise levels drop from 44 code widths to just 1 after implementing various noise reduction strategies in a weight sensing application.
Lecture20
This document discusses different circuit design techniques for combinational logic, including:
1. Pseudo-nMOS circuits which use a permanently on pMOS transistor but have static power consumption issues.
2. Cascode Voltage Switch Logic seeks the performance of pseudo-nMOS without static power draw but requires input complements.
3. Pass transistor logic uses only two transistors but output levels are not restored perfectly and cannot drive other gates directly.
Basic circuit or cad
The document discusses basic circuit simulation concepts using OrCAD software. It covers capacitors and inductors in series and parallel, reviews their frequency response characteristics, and how they can be used to create filters. It also discusses decibels, cursor controls in OrCAD, common problems in simulations, transformers, diodes, rectification circuits, and voltage regulators.
Lecture 10.ppt
Very Large Scale Integration (VLSI) is a solid career choice and offers job opportunities for ECE freshers pursuing core employment. In India and overseas, VLSI provides a variety of employment roles featuring outstanding professional growth and salary incentives.
mc_dac_agjskskskskskskssksksksksksksk.pdf
* Real-world signals are analog but digital formats provide advantages for processing and transmission
* Analog-to-digital converters (ADCs) convert analog signals to digital, and digital-to-analog converters (DACs) perform the reverse conversion
* A common DAC implementation uses a binary-weighted resistor network, where the reference voltage is applied to resistors according to the digital input bits, and the output is the sum of all currents which is then converted to a voltage
CMOS Topic 6 -_designing_combinational_logic_circuits
This document discusses designing combinational logic circuits using static complementary CMOS design. It explains how to construct static CMOS circuits for logic gates like NAND and NOR by using pull-up and pull-down networks of PMOS and NMOS transistors respectively. Issues related to pass-transistor design like noise margins and static power consumption are also covered. The document provides details on implementing various logic functions using pass-transistor logic and differential pass-transistor logic. It discusses solutions to overcome the disadvantages of pass-transistor logic like level restoration and use of multiple threshold transistors.
Analog to Digital Converters and Data Acquisition Systems
This document discusses principles of data acquisition systems and analog-to-digital converters. It describes the basic functions of data acquisition systems including analog input, output, and digital and timing I/O. It then discusses analog-to-digital converter types including integration, successive approximation, flash, and sigma-delta converters. It covers characteristics, principles of operation, advantages and disadvantages of each type. Finally, it outlines the functional blocks of a typical data acquisition system including specification parameters and the analog input stage.
Delay Calculation in CMOS Chips Using Logical Effort by Prof. Akhil Masurkar
1) The document discusses using logical effort to estimate delay in CMOS chips. Logical effort allows estimating delay without simulating specific transistor sizes.
2) Delay has two components - effort delay proportional to load and parasitic delay independent of load. Effort delay depends on logical effort and electrical effort.
3) Logical effort measures a gate's ability to source current relative to an inverter. Electrical effort is the ratio of output to input capacitance.
08 decoder
The document describes decoders and encoders. It begins by explaining what a decoder is, providing examples of 2-to-4 and 3-to-8 decoders. It then discusses how decoders can be used to implement general logic and combinational circuits using decoders and OR gates. The document proceeds to describe specific decoder chips like the 74x139 and 74x138 decoders. It also discusses using 3-state buffers with decoders and building decoders from smaller decoders. The document then shifts to discussing encoders, 7-segment decoders, truth tables, and K-maps in the design of decoders and encoders. It concludes by discussing priority encoders and the 74x148 priority encoder chip.
Similar to Lecture17 (20)
CMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuits
Analog to Digital Converters and Data Acquisition Systems
Analog to Digital Converters and Data Acquisition Systems
Delay Calculation in CMOS Chips Using Logical Effort by Prof. Akhil Masurkar
Delay Calculation in CMOS Chips Using Logical Effort by Prof. Akhil Masurkar
Lecture17
- 1. Design and Implementation of VLSI Systems (EN0160) Lecture 17: Static Combinational Circuit Design (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160
- 2. How to convert an AND/OR to a NAND/NOR network? Sketch a 2 by 1 multiplexer design using AND, OR, and NOT gates. D0 S Y D1 S S. Reda EN160
- 3. Converting AND/OR networks to NAND/NOR networks • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic – Remember DeMorgan’s Law Y Y (a) (b) Y Y D (c) (d) S. Reda EN160
- 4. Compound gates • Logical Effort of compound gates S. Reda EN160
- 5. Delay calculation example • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. D0 D0 S S Y Y D1 D1 S S H = 160 / 16 = 10 B=1 N=2 S. Reda EN160
- 6. Solution: simple versus compound for the MUX case D0 D0 S S Y Y D1 D1 S S P = 2+2 = 4 P = 4 +1 = 5 G = (4 / 3)g / 3) = 16 / 9 (4 G = (6 / 3)g = 2 (1) F = GBH = 160 / 9 F = GBH = 20 ˆ f = N F = 4.2 ˆ f = N F = 4.5 ˆ D = Nf + P = 12.4τ ˆ D = Nf + P = 14τ S. Reda EN160
- 7. Annotating design with transistor sizes • Annotate your designs with transistor sizes that achieve this delay. 8 8 8 10 10 8 25 25 10 10 24 Y Y 25 6 6 12 8 8 25 6 6 8 8 16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36 S. Reda EN160
- 8. Parasitic modeling • Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? 2τ • If B arrives latest? 2.33τ 2 2 Y A 2 6C B 2x 2C If input arrival time is known –Connect latest input to inner terminal S. Reda EN160
- 9. Asymmetric gates • Asymmetric gates favor one input over another • Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input – So total resistance is same • gA = 10/9 • gB = 2 • gtotal = gA + gB = 28/9 • Asymmetric gate approaches g = 1 on critical input • But total logical effort goes up S. Reda EN160
- 10. Symmetric gates • Inputs can be made perfectly symmetric 2 2 Y A 1 1 B 1 1 S. Reda EN160
- 11. Skewed gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor • Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = 2.5 / 3 = 5/6 – gd = 2.5 / 1.5 = 5/3 S. Reda EN160
- 12. Hi- and Lo-Skew • Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. • Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) • Logical effort is smaller for favored direction • But larger for the other direction S. Reda EN160
- 13. Catalog of skewed gates S. Reda EN160