Lecture 1
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This document summarizes the key topics covered in a lecture on digital electronics basics, including: - Logic gates (AND, OR, NOT) and their truth tables. - Flip flops which can store one bit and have two stable states, including common types like SR, D, JK, and T flip flops. - Clocked flip flops which only change state on the rising/falling edge of a clock pulse for synchronization. - Registers, counters, multiplexers, demultiplexers, decoders and encoders which were also overviewed but not described in detail.
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The document provides information about various types of digital logic circuits including flip-flops, microcontrollers, and computer architectures. It describes the basic operation and applications of SR, JK, D, and T flip-flops. It also discusses asynchronous and synchronous counters built using flip-flops. The document compares microcontrollers to microprocessors and describes the von Neumann and Harvard computer architectures. It provides details on the Pic 16F628A microcontroller and the hardware and software used for microcontroller programming.
5th unit Microprocessor 8085
The document provides information about the 8085 microprocessor. It begins with definitions of key terms like microprocessor, CPU, ALU, and bus. It then discusses the evolution of microprocessors from early 4-bit models to later 8-bit, 12-bit, and 16-bit models like the Intel 8085. The document details the architecture of the 8085, including its pin descriptions and addressing modes. It categorizes the instruction set into groups for data transfer, arithmetic, logical, branch, and machine control operations. Memory-mapped I/O is also introduced.
Csa chapter 2
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This document provides information about sequential logic circuits. It begins by defining sequential logic circuits as consisting of a combinational circuit with storage elements that provide feedback, causing the output to depend on the sequence of inputs. It describes the main types of sequential circuits as synchronous and asynchronous. It also discusses different types of storage elements including latches and flip-flops. Latches are level sensitive while flip-flops are edge triggered. Specific latch and flip-flop circuits like the SR latch, D latch, and JK flip-flop are described along with their operations.
Basic computer organisation design
The document discusses interrupt-initiated input/output in computer systems. It explains that when an I/O device is ready to transfer data, it generates an interrupt request to the CPU. The CPU then stops its current task, branches to an interrupt service routine to process the data transfer, before returning to its original task. It provides a flowchart of the interrupt cycle and describes the register transfer operations that occur, including saving the return address and branching to an interrupt handling location in memory. Finally, it outlines the basic hardware components of a computer, including memory, registers, decoders, and control logic gates.
counter using 4 master slave flip-flops
This document describes how to design a 4-bit counter using master-slave JK flip-flops. It begins by explaining what a flip-flop is and describing common flip-flop types like the SR, JK, and master-slave JK flip-flop. It then shows how to connect 4 master-slave JK flip-flops in a ring configuration to form a counter that will count from 0 to 15 (hexadecimal F). The document concludes by presenting the circuit design of a 4-bit counter created using DSCH simulation software, along with output waveforms and a timing diagram verifying the counter operates as intended.
Plc example presentation
The document provides information about programmable logic controllers (PLCs). It defines a PLC as a digital computer used to automate electromechanical processes. The document then discusses the key advantages of PLCs like being cost-effective, flexible, and able to operate reliably for years. It also describes the basic architecture of a PLC including input and output modules, a central processing unit, and a programming device. Examples of ladder logic programming are also included to illustrate how PLCs can be programmed to control processes like starting motors in forward and reverse directions.
8. Kevin Stanton-report PSUBOT
The document provides an overview of the hardware and software components of the PSUBOT, an autonomous wheelchair robot. It describes the various subsystems that control functions like motor control, feedback, sonar, and voice recognition. The PSUBOT uses an electric wheelchair base equipped with computers, sensors, and software to allow voice-controlled navigation for disabled users within known buildings.
De EE unit-3.pptx
1. The document discusses sequential logic circuits and various types of storage elements used in them, including latches and flip-flops.
2. It describes the basic operation of latches, SR latches, D latches, and various types of flip-flops including RS, JK, T, and D flip-flops.
3. The key differences between latches and flip-flops are explained, with latches being level-sensitive and flip-flops being edge-triggered.
Architecture of 8051
The 8051 microcontroller is an 8-bit microcontroller that contains a CPU, RAM, ROM, I/O ports, and special function registers on a single chip. It has components like an ALU, program counter, registers, timers/counters, internal RAM and ROM, four 8-bit I/O ports, an interrupt controller, serial communication capabilities, and other registers. The 8051 has 12 major components that allow it to perform arithmetic, logical operations, store and fetch instructions, interface with external devices, and communicate serially.
Unit 4 - PLC.pptx
The document provides information about programmable logic controllers (PLCs). It defines a PLC according to the NEMA standard as a digitally operating, microprocessor-based electronic apparatus that uses a programming memory to implement logic, sequencing, timing, counting, and arithmetic functions to control machines and processes. The document discusses the historical development of PLCs, their basic components including inputs, outputs, power supply and programming. It provides examples of PLC applications and programming techniques such as ladder logic. It also lists some leading PLC brands and provides basic information about relays and internal relays used in PLC systems.
ie450pp10.ppt
The document provides an overview of programmable logic controllers (PLCs) for manufacturing control systems. It discusses the history and purpose of PLCs, types of control systems, components that PLCs interact with like input/output devices, switches, relays, counters, timers, and the basic functions of PLC programming using ladder logic diagrams. An example is also provided to demonstrate how a PLC could be programmed to control the filling of an oil tank using input sensors and output devices.
ie450pp10.ppt
The document provides an overview of programmable logic controllers (PLCs) and their use in manufacturing control systems. It discusses the history and purpose of PLCs, the components that PLCs interact with including input/output devices, and basic PLC programming concepts such as ladder logic, instructions, and logic states. It also provides an example of how a PLC could be programmed and wired to control the filling of an oil tank based on input from two level sensors.
PLC.ppt
The document provides an overview of programmable logic controllers (PLCs) and their use in manufacturing control systems. It discusses the history and purpose of PLCs, the components that PLCs interact with including input/output devices, and basic PLC programming concepts such as ladder logic, instructions, and logic states. It also provides an example of using ladder logic to program a PLC to control the filling of a tank based on input from two level sensors.
PLC good.ppt
This document provides an overview of programmable logic controllers (PLCs) for manufacturing control systems. It discusses the history and purpose of PLCs, types of control systems, PLC components including the processor, memory, I/O modules and power supply. The document also covers topics like ladder logic programming, input and output devices that interact with PLCs, switches, relays, counters, timers, and an example PLC program for traffic light control.
ie450pp10.ppt
The document provides an overview of programmable logic controllers (PLCs) and their use in manufacturing control systems. It discusses the history and purpose of PLCs, the components that PLCs interact with including input/output devices, and basic PLC programming concepts such as ladder logic, instructions, and logic states. It also provides an example of how a PLC could be programmed and wired to control the filling of an oil tank based on input from two level sensors.
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Lecture 46
This document discusses parallel processing and different types of parallel computers. It describes Flynn's classification of parallel computers based on the number of instruction and data streams as SISD, SIMD, MISD, and MIMD. It then provides details about each classification including characteristics, examples, and limitations. The document also covers topics like pipelining, interconnection networks, and how pipelining can improve the speed of computation.
Lecture 43
This document discusses memory organization and virtual memory. It describes how virtual memory uses a memory mapping table to map virtual addresses to physical addresses, giving the illusion of a larger memory. It discusses page tables and how they map address spaces to memory spaces using pages. It also covers page faults, how they are handled by the operating system, and different page replacement algorithms like FIFO, OPT, and LRU used when a page fault occurs and a frame needs to be selected for replacement.
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The document discusses different types of memory organization and caching techniques used in computer systems. It describes the memory hierarchy including main memory, auxiliary memory, and cache memory. It discusses the locality of reference property and how cache memory exploits this to improve performance. It then summarizes different cache mapping techniques like direct mapping, set-associative mapping, and associative mapping. It also covers cache operations and replacement policies. Finally, it discusses write policies for caches including write-through and write-back.
Lecture 41
This document discusses different types of computer memory organization. It covers memory hierarchy including main memory, auxiliary memory like magnetic tapes and disks, associative memory, cache memory, and virtual memory. It provides details on how information is organized on magnetic tapes and disks. Associative memory, also called content addressable memory (CAM), allows data to be accessed by its content rather than an address. Each word in CAM is compared in parallel to the argument register, and the match register indicates which words match.
Lecture 40
The document discusses computer memory organization. It describes the memory hierarchy from fastest to slowest as registers, cache memory, main memory, and auxiliary memory such as magnetic disks and tapes. The main memory section explains RAM and ROM chips, how they are connected to the CPU via address and data buses, and how the address lines select individual bytes or chips. It provides an example memory map assigning address ranges to different RAM and ROM chips and shows how a decoder chip selects the appropriate chip.
Lecture 38
This document discusses input/output organization and interrupt handling. It covers peripheral devices, input-output interfaces, asynchronous data transfer, direct memory access, interrupt priorities, interrupt service routines, and serial communication. Parallel priority interrupts are handled through an interrupt register, mask register, priority encoder, and interrupt acknowledgement signal from the CPU. When an interrupt occurs, the CPU saves its state, reads the vector address, and jumps to the interrupt service routine before restoring its context.
Lecture 37
The document discusses different methods of implementing priority interrupts in computer systems, including software polling, hardware priority interrupts, and daisy chain hardware priority interrupts. Software polling establishes priority by the order devices are polled but is flexible and low cost, though slow. Hardware priority interrupts use a priority interrupt manager to identify the highest priority interrupt request quickly in hardware. Daisy chain hardware priority interrupts work by having devices connected in a serial chain, with the closest interrupting device to the CPU getting access to interrupt the CPU when multiple interrupts occur simultaneously.
Lecture 36
This document provides an overview of input/output organization and various input/output techniques including peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer such as programmed I/O, interrupt-initiated I/O, and direct memory access. It also discusses universal asynchronous receiver transmitter chips, first-in first-out buffers, and compares different modes of transfer including their advantages and disadvantages.
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This document discusses various methods of input/output organization and asynchronous data transfer. It covers peripheral devices, input-output interfaces, asynchronous and synchronous data transfer, strobe control using a single control line, handshaking using two control signals, source and destination initiated transfers, and asynchronous serial transfer using start and stop bits.
Lecture 34
This document provides an overview of input/output organization. It discusses peripheral devices, input and output interfaces, asynchronous data transfer, modes of transfer, interrupts, direct memory access, I/O processors, and serial communication. It describes common input devices like keyboards and optical scanners and output devices like printers and displays. It also covers I/O interfaces, buses, isolated versus memory mapped I/O, and programmable I/O interfaces.
Lecture 28
This document discusses computer processor architecture and organization. It covers complex instruction set computers (CISC) and reduced instruction set computers (RISC). CISC processors have complex, variable-length instructions that can directly access memory, while RISC processors have simpler, fixed-length instructions that only use registers except for load and store instructions. The document outlines criticisms of CISC related to complexity and inefficiency, and how RISC aims to simplify instruction sets and execution to improve performance.
Lecture 25
This document discusses different addressing modes used in computer architecture. It defines addressing modes as rules for interpreting or modifying the address field of an instruction before referencing the operand. Seven common addressing modes are described: implied, immediate, register, register indirect, autoincrement/autodecrement, direct, and indirect. Examples are provided to illustrate how the effective address is calculated for each mode.
Lecture 22
This document discusses the central processing unit (CPU) and its major components. It describes the CPU's storage components like registers and flags, execution components like the arithmetic logic unit (ALU), transfer components like buses, and control components like the control unit. It provides details on register organization, instruction formats, addressing modes, and data transfer and manipulation instructions. It also explains the operation of the control unit in directing information flow and selecting CPU components.
Lecture 21
The document discusses the control unit of a computer. It covers control memory, microinstruction sequencing, the microinstruction format, design of the control unit, and the address sequencer. The address sequencer uses a multiplexer to select the next address from various sources like incrementing the current address, returning from a subroutine, branching to a new address, or mapping from the machine instruction.
Lecture 20
The document discusses control units and their implementation in computers. Control units can be implemented either using hardwired logic circuits or using microprogrammed control with a control memory storing microinstructions. A microprogrammed control unit contains a control storage which holds the microprogram consisting of microinstructions. Each microinstruction contains a control word to generate control signals and a sequencing word to determine the next microinstruction address. The control unit implements instruction set execution through microinstructions stored in its control storage and addressed by a microprogram sequencer.
Lecture 15
The document describes the basic instruction cycle of a computer. It explains that an instruction is executed in four steps: 1) fetching the instruction from memory, 2) decoding the instruction, 3) reading the effective address from memory if needed, and 4) executing the instruction. It then repeats this cycle for the next instruction. The document also provides more details on the fetch and decode portion of the cycle, showing how the program counter addresses memory to fetch the instruction and load it into the instruction register for decoding.
Lecture 14
This document summarizes a lecture on computer organization and design. It discusses the control unit and how it translates machine instructions into microoperations through either hardwired control or microprogrammed control. It then focuses on the timing and control of the basic computer's control unit. Specifically, it describes how an instruction register, decoders, sequence counter, and combinational logic are used to generate the necessary control signals through a clock and timing signals.
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Lecture 1
- 1. Review of Basics of Digital Electronics 1 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Overview Introduction Logic Gates Flip Flops Registers Counters Multiplexer/ Demultiplexer Decoder/ Encoder
- 2. Review of Basics of Digital Electronics 2 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Introduction Digital Computer A computer that stores data in terms of digits (numbers) and proceeds in discrete steps from one state to the next Binary digits The states of a digital computer typically involve binary digits. A binary digit is called a bit RAM CPU O/P Device I/P Device IOP Block diagram of a digital computer
- 3. Review of Basics of Digital Electronics 3 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Logic Gates A X X = (A + B)’ B Name Symbol Function Truth Table AND A X = A • B X or B X = AB 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR A X X = A + B B I A X X = A 0 1 1 0 Buffer A X X = A A X 0 0 1 1 NAND A X X = (AB)’ B 0 0 1 0 1 1 1 0 1 1 1 0 NOR 0 0 1 0 1 0 1 0 0 1 1 0 XOR Exclusive OR A X = A B X or B X = A’B + AB’ 0 0 0 0 1 1 1 0 1 1 1 0 A X = (A B)’ X or B X = A’B’+ AB 0 0 1 0 1 0 1 0 0 1 1 1 XNOR Exclusive NOR or Equivalence A B X A B X A X A B X A B X A B X A B X
- 4. Review of Basics of Digital Electronics 4 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Flip Flops Characteristics - 2 stable states - Memory capability - Operation is specified by a Characteristic Table The Storage elements employed in clocked sequential circuits, capable of storing one bit of information, are called Flip Flops The most common types of flip flops are SR (Set Reset) D (Data) JK T (Toggle)
- 5. Review of Basics of Digital Electronics 5 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Clocked Flip Flops In a large digital system with many flip flops, operations of individual flip flops are required to be synchronized to a clock pulse. Otherwise, the operations of the system may be unpredictable. S Q c R Q’ S Q c R Q’ Clock pulse allows the flip flop to change state only when there is a clock pulse appearing at the c terminal (as shown in fig). Edge Triggered Flip Flops operates when operates when clock is high clock is low State transition occurs at the rising edge or falling edge of the clock pulse
- 6. Review of Basics of Digital Electronics 6 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT S Q c R Q’ S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 indeterminate (forbidden) Flip Flop GraphicalSymbol Characteristic Table SR (Set Reset) D (Data) D Q(t+1) 0 0 1 1 J Q C K Q' Flip Flops
- 7. Review of Basics of Digital Electronics 7 Lecture 1 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT J Q c R Q’ S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 indeterminate (forbidden) Flip Flop GraphicalSymbol Characteristic Table J-K T (Toggle) T Q c T Q(t+1) 0 Q(t) 1 Q’(t) J Q C K Q' J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t) Flip Flops