The document provides an overview of memory reference instructions, detailing the types and functions of seven specific instructions used in computer architecture. It explains the process of executing these instructions, including the roles of microoperations, effective addresses, and various registers. Additionally, examples of the instructions such as add, load, store, and branching operations are illustrated, emphasizing their significance in accessing and manipulating memory data.

1. MEMORYREFERENCE
INSTRUCTIONS
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Presented by: Rabin BK
BSc.CSIT 3rd Semester

2. Introduction to Memory Reference Instructions
Some terminologies
Memory Reference Instructions
References
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3. There are seven different memory-reference instructions
Actual execution of the instruction in the bus system requires a sequence of
microoperations as data in memory cannot be processed directly
Microoperations are needed for the data to be read from memory to a
register to operate them on logic circuits
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Introduction to Memory Reference Instructions
Symbol Operation Decoder
AND D0
ADD D1
LDA D2
STA D3
BUN D4
BSA D5
ISZ D6

4. Effective address (EA)
• Any operand to an instruction which references memory
• Basically enclosed inside a square brackets
• Calculated as: EA = Base + (Index*Scale) + Displacement
• Displacement — An 8-, 16-, or 32-bit value.
• Base — The value in a general-purpose register
• Index — The value in a general-purpose register
• Scale factor — A value of 2, 4, or 8 that is multiplied by the index value
DR → Data Register
AR → Address Register
IR → Instruction Register
PC → Program Counter
AC→ Accumulator
SC → Sequence Counter
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Some terminologies

5. AND to AC
 Performs the AND logic operations on pairs of bits in AC and the
memory word specified by the effective address
 Two timing signals are needed
• In T4 transfering operand from memory into DR
• In T5 transfering result of AND logic operation between the contents
of DR and AC
• In T5 SC is cleared to 0 and control is transfered to T0 to start a new
instruction cycle
 Example:
• D0T4: DR←M[AR]
• D0T5: AC←AC∧ DR, SC←0
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Instructions

6. ADD to AC
 Adds the contents of memory word specified by the effective
address to the value of AC
 Sum is transferred into AC and the output carry Cout is transferred to
the E(extended accumulator) flip flop
 Two timing signals are needed but decoder D1 instead of D0
 Example:
• D1T4: DR←M[AR]
• D1T5: AC←AC+DR, E←Cout SC←0
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Instructions cont...

7. LDA:Load to AC
 Tranfers the memory word specified by the effective address to AC
 Necessary to read the memory word into DR first and transfer the
contents of DR into AC
 there is no direct path from bus into AC
 to maintain one clock cycle as well
 Example:
 D2T4: DR←M[AR]
 D2T5: AC←DR SC←0
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Instructions cont...

8. STA:Store AC
Stores the content of AC into the memory word specified by the
effective address
 The output of AC is applied to the bus and the data input of
memory is connected to the bus
 Example:
 D3T4: M[AR]←AC, SC←0
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Instructions cont...

9. BUN:Branch Unconditionally
 PC is incremented at time T1 to prepare it for the address of the next
instruction in the program sequence
 BUN transfers the program to the instruction specified by the
effective address
 Allows the programmer to specify an instruction out of sequence
and we say that the program branches (jumps) unconditionally
 Example:
 D4T4: PC←AR SC←0 (resetting SC transfers control to T4)
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Instructions cont...

10. BSA:Branch and Save Return Address
 Useful for branching to a portion of the program called a subroutine
or procedure
 When executed, it stores the address of the next instruction in
sequence (which is available in PC) into a memory location
specified by the effective address
 (Effective address + 1) is then transferred to PC to serve as the
address of the first instruction in the subroutine
 The return to the original program is accomplished by the BUN
instruction placed at the end of the subroutine
 Example:
 D5T4: M[AR]←PC, AR←AR+1
 D5T5: PC ← AR, SC←0
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Instructions cont...

11. ISZ:Increment and Skip if Zero
 Increments the word specified by the effective address
 If the incremented value is equal to 0, PC is incremented by 1
 When a negative number(in 2's compelement) stored in memory word is
repeatedy incremented by 1 it eventually reaches zero
 At this time PC is incremented by one in order to skip the next
instruction in the program
 It is necessary to read the word into DR, increment DR and store the
word back into memory since it is not possible to increment a word
inside the memory
 Example:
 D6T4: DR←M[AR]
 D6T5: DR←DR+1
 D6T6: M[AR] ← DR, if (DR=0) then (PC←PC+1), SC←0
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Instructions cont...

12. References
• Dasgupta, S., Computer Architecture: A Modern Synthersis, Vol. 2 New
York: John Wiley, 1989
• M.Morris Mano, Computer System Architecture, Pearson, Third Edition
• https://www.tortall.net/projects/yasm/manual/html/nasm-effaddr.html
• http://faculty.cs.niu.edu/~berezin/463/notes/addrmode.html
• https://everything2.com/title/Effective+address
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13. Queries
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