Lecture 42
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The document discusses different types of memory organization and caching techniques used in computer systems. It describes the memory hierarchy including main memory, auxiliary memory, and cache memory. It discusses the locality of reference property and how cache memory exploits this to improve performance. It then summarizes different cache mapping techniques like direct mapping, set-associative mapping, and associative mapping. It also covers cache operations and replacement policies. Finally, it discusses write policies for caches including write-through and write-back.
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This document discusses memory organization and management techniques. It covers memory hierarchy including main memory, auxiliary memory, cache memory and virtual memory. It then describes memory management hardware and its basic functions like dynamic storage relocation and memory protection. The document explains segmentation as a memory management scheme that supports variable sized segments. It provides an example to illustrate segmentation and how multiple users can share segments. Finally, it discusses combining segmentation with paging to create a segmented page system and how page and segment tables are implemented.
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This document contains information about cache memory provided by multiple students:
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This document discusses memory management techniques used in operating systems, including:
- Base and limit registers that define the logical address space and protect memory accesses.
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- The memory management unit (MMU) that maps virtual to physical addresses using base/limit registers.
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This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
OS_Ch9
This document discusses different memory management techniques including:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation. Paging and segmentation address this by allowing non-contiguous allocation.
2. Paging maps logical addresses to physical frames through a page table. It supports non-contiguous allocation but has translation overhead that is reduced using translation lookaside buffers.
3. Segmentation divides memory into logical segments and uses a segment table to map logical to physical addresses. It matches the user's view of memory but external fragmentation remained an issue until combined with paging.
Main memory os - prashant odhavani- 160920107003
This document describes various memory management techniques used in computer systems, including swapping, contiguous allocation, paging, segmentation, and the memory architecture of the Intel Pentium CPU. It discusses how paging uses a page table to map logical addresses to physical frames through an address translation process. Segmentation divides memory into variable-length segments and uses segment tables. The Pentium supports both pure segmentation and a hybrid of segmentation and paging to translate logical addresses to physical memory locations.
Memory management
Memory management is the act of managing computer memory. The essential requirement of memory management is to provide ways to dynamically allocate portions of memory to programs at their request, and free it for reuse when no longer needed. This is critical to any advanced computer system where more than a single process might be underway at any time
Unit-4 swapping.pptx
Main memory is used to store programs and data for the CPU to access directly. Paging is a memory management technique that divides main memory into fixed-sized blocks called frames and divides logical memory into same-sized blocks called pages. The page table maps logical page numbers to physical frame numbers, with translation lookaside buffers caching these mappings to improve performance. Protection bits in page table entries enforce access permissions on individual pages.
Memory Managment(OS).pptx
The document discusses memory management techniques. It begins by explaining logical vs physical address spaces and the need for memory protection when multiple processes reside in memory. It then covers various memory allocation schemes like contiguous allocation, paging, and segmentation. Paging divides memory into fixed-sized frames and logical memory into pages. Address translation uses a page table to map logical to physical addresses. Hierarchical paging is introduced to reduce the size of large page tables.
hierarchical memory technology.pptx
This document discusses optimizations to cache memory hierarchies to improve performance. It introduces the concepts of multi-level caches, where adding a second-level cache can reduce the miss penalty from the first-level cache. The average memory access time equation is extended to account for multiple cache levels. Examples are provided to show how a second-level cache can lower the average memory access time and reduce stalls per instruction compared to a single-level cache.
DLCA-UNIT-5-Memory Organization-Cache.pdf
The document discusses cache memory organization. It describes how cache memory uses the principle of locality of reference to improve memory access time. It is placed between the CPU and main memory and is 10-100 times faster. The document introduces cache hit ratio and average memory access time formulas. It then covers different cache mapping techniques - direct mapping, associative mapping, and set-associative mapping which map blocks of main memory to blocks of cache memory. Examples of 2-way set associative mapping are provided.
04 Cache Memory
The document summarizes key characteristics of cache memory including location, capacity, unit of transfer, access methods, performance, physical types, organization, and hierarchy. It discusses cache memory in terms of where it is located (internal or external to the CPU), its typical sizes (word, block), access techniques (sequential, random, associative), performance metrics (access time, transfer rate), common physical implementations (SRAM, disk), and organizational aspects like mapping functions, replacement algorithms, and write policies. A cache sits between the CPU and main memory, using fast but small memory to speed up access to frequently used data from larger but slower main memory.
Os presentation
segmentation technique meomery mangement used in opreating system different between paging and segmentation
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Lecture 47
This document discusses parallel processing and different types of multiprocessor systems. It describes tightly and loosely coupled systems, as well as coarse-grained, medium-grained, and fine-grained parallelism. Shared memory and distributed memory architectures are covered, along with interconnection structures like buses, crossbar switches, and multistage networks. Memory organization and communication in parallel systems concludes the document.
Lecture 46
This document discusses parallel processing and different types of parallel computers. It describes Flynn's classification of parallel computers based on the number of instruction and data streams as SISD, SIMD, MISD, and MIMD. It then provides details about each classification including characteristics, examples, and limitations. The document also covers topics like pipelining, interconnection networks, and how pipelining can improve the speed of computation.
Lecture 43
This document discusses memory organization and virtual memory. It describes how virtual memory uses a memory mapping table to map virtual addresses to physical addresses, giving the illusion of a larger memory. It discusses page tables and how they map address spaces to memory spaces using pages. It also covers page faults, how they are handled by the operating system, and different page replacement algorithms like FIFO, OPT, and LRU used when a page fault occurs and a frame needs to be selected for replacement.
Lecture 39
This document discusses input/output organization and direct memory access. It describes how a DMA controller allows I/O devices to directly access main memory without involving the CPU, freeing it up for other tasks. The DMA controller uses cycle stealing to interweave memory accesses with the CPU. I/O processors called channels can also perform direct memory access and execute channel programs stored in memory to control I/O devices.
Lecture 38
This document discusses input/output organization and interrupt handling. It covers peripheral devices, input-output interfaces, asynchronous data transfer, direct memory access, interrupt priorities, interrupt service routines, and serial communication. Parallel priority interrupts are handled through an interrupt register, mask register, priority encoder, and interrupt acknowledgement signal from the CPU. When an interrupt occurs, the CPU saves its state, reads the vector address, and jumps to the interrupt service routine before restoring its context.
Lecture 37
The document discusses different methods of implementing priority interrupts in computer systems, including software polling, hardware priority interrupts, and daisy chain hardware priority interrupts. Software polling establishes priority by the order devices are polled but is flexible and low cost, though slow. Hardware priority interrupts use a priority interrupt manager to identify the highest priority interrupt request quickly in hardware. Daisy chain hardware priority interrupts work by having devices connected in a serial chain, with the closest interrupting device to the CPU getting access to interrupt the CPU when multiple interrupts occur simultaneously.
Lecture 36
This document provides an overview of input/output organization and various input/output techniques including peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer such as programmed I/O, interrupt-initiated I/O, and direct memory access. It also discusses universal asynchronous receiver transmitter chips, first-in first-out buffers, and compares different modes of transfer including their advantages and disadvantages.
Lecture 35
This document discusses various methods of input/output organization and asynchronous data transfer. It covers peripheral devices, input-output interfaces, asynchronous and synchronous data transfer, strobe control using a single control line, handshaking using two control signals, source and destination initiated transfers, and asynchronous serial transfer using start and stop bits.
Lecture 34
This document provides an overview of input/output organization. It discusses peripheral devices, input and output interfaces, asynchronous data transfer, modes of transfer, interrupts, direct memory access, I/O processors, and serial communication. It describes common input devices like keyboards and optical scanners and output devices like printers and displays. It also covers I/O interfaces, buses, isolated versus memory mapped I/O, and programmable I/O interfaces.
Lecture 28
This document discusses computer processor architecture and organization. It covers complex instruction set computers (CISC) and reduced instruction set computers (RISC). CISC processors have complex, variable-length instructions that can directly access memory, while RISC processors have simpler, fixed-length instructions that only use registers except for load and store instructions. The document outlines criticisms of CISC related to complexity and inefficiency, and how RISC aims to simplify instruction sets and execution to improve performance.
Lecture 27
The document discusses program control in central processing units. It covers instruction formats, addressing modes, data transfer and manipulation. It describes program control instructions like branch, jump, skip, call, and return. Conditional branch instructions are also explained. Subroutine call and return operations involve branching to the subroutine and saving the return address. Processor flags and status words are used to indicate information about the processor state.
Lecture 26
This document discusses different types of instructions used in a central processing unit. It covers data transfer instructions like load, store, move, input and output. It also discusses data manipulation instructions, which are divided into arithmetic instructions, logical and bit manipulation instructions, and shift instructions. Specific instructions in each category are provided along with their mnemonics. Addressing modes that can be used with data transfer instructions are also explained.
Lecture 25
This document discusses different addressing modes used in computer architecture. It defines addressing modes as rules for interpreting or modifying the address field of an instruction before referencing the operand. Seven common addressing modes are described: implied, immediate, register, register indirect, autoincrement/autodecrement, direct, and indirect. Examples are provided to illustrate how the effective address is calculated for each mode.
Lecture 24
This document discusses different CPU organizations and instruction formats. It describes single accumulator, general register, and stack organizations. Instruction formats contain operation code, address, and mode fields. Three-address, two-address, one-address, and zero-address instruction formats are explained along with examples. Various addressing modes allow operands to be accessed from memory or registers.
Lecture 23
This document discusses different CPU organizations including general register organization, stack organization, instruction formats, and addressing modes. It specifically describes register stack organization and memory stack organization. Register stack organization uses push and pop operations to manage a stack using registers, while memory stack organization uses a portion of memory as a stack managed by a stack pointer register. It also discusses using reverse polish notation for stack-based evaluation of arithmetic expressions and the three main types of processor organization: single register, general register, and stack-based.
Lecture 22
This document discusses the central processing unit (CPU) and its major components. It describes the CPU's storage components like registers and flags, execution components like the arithmetic logic unit (ALU), transfer components like buses, and control components like the control unit. It provides details on register organization, instruction formats, addressing modes, and data transfer and manipulation instructions. It also explains the operation of the control unit in directing information flow and selecting CPU components.
Lecture 21
The document discusses the control unit of a computer. It covers control memory, microinstruction sequencing, the microinstruction format, design of the control unit, and the address sequencer. The address sequencer uses a multiplexer to select the next address from various sources like incrementing the current address, returning from a subroutine, branching to a new address, or mapping from the machine instruction.
Lecture 20
The document discusses control units and their implementation in computers. Control units can be implemented either using hardwired logic circuits or using microprogrammed control with a control memory storing microinstructions. A microprogrammed control unit contains a control storage which holds the microprogram consisting of microinstructions. Each microinstruction contains a control word to generate control signals and a sequencing word to determine the next microinstruction address. The control unit implements instruction set execution through microinstructions stored in its control storage and addressed by a microprogram sequencer.
Lecture 19
This document describes the design of a basic computer. It includes:
- The hardware components, which are a 4096 x 16 memory unit, various registers like the program counter and accumulator, status flip-flops, decoders, and a common bus.
- The control logic gates which control the registers, memory read/write, flip-flops, bus selection, accumulator, and adder/logic circuit.
- Details of the instruction set like fetch, decode, execute stages and timings, as well as register-reference, memory reference, I/O, and interrupt instructions.
Lecture 18
This document discusses input/output and interrupt handling in a basic computer system. It describes the I/O configuration including input and output registers and flags. It explains programmed and interrupt-initiated I/O, with the interrupt cycle storing the return address and branching to an interrupt service routine before returning to the main program. Input/output and interrupt instructions are also outlined.
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Lecture 42
- 1. Memory Organization 1 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Overview Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory Memory Mgt Hardware
- 2. Memory Organization 2 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Cache Memory Locality of Reference - The references to memory at any given time interval tend to be confined within a localized areas - This area contains a set of information and the membership changes gradually as time goes by - Temporal Locality The information which will be used in near future is likely to be in use already( e.g. Reuse of information in loops) - Spatial Locality If a word is accessed, adjacent(near) words are likely accessed soon (e.g. Related data items (arrays) are usually stored together; instructions are executed sequentially) Cache - The property of Locality of Reference makes the cache memory systems work - Cache is a fast small capacity memory that should hold those information which are most likely to be accessed Main memory Cache memory CPU
- 3. Memory Organization 3 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Performance of Cache All the memory accesses are directed first to Cache If the word is in Cache; Access cache to provide it to CPU If the word is not in Cache; Bring a block (or a line) including that word to replace a block now in Cache - How can we know if the word that is required is there ? - If a new block is to replace one of the old blocks, which one should we choose ? Memory Access Performance of Cache Memory System Hit Ratio - % of memory accesses satisfied by Cache memory system Te: Effective memory access time in Cache memory system Tc: Cache access time Tm: Main memory access time Te = Tc + (1 - h) Tm Example: Tc = 0.4 s, Tm = 1.2s, h = 0.85% Te = 0.4 + (1 - 0.85) * 1.2 = 0.58s
- 4. Memory Organization 4 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Memory and Cache Mapping – (Associative Mapping) Associative mapping Direct mapping Set-associative mappingAssociative Mapping Mapping Function Specification of correspondence between main memory blocks and cache blocks - Any block location in Cache can store any block in memory -> Most flexible - Mapping Table is implemented in an associative memory -> Fast, very Expensive - Mapping Table Stores both address and the content of the memory word address (15 bits) Argument register Address Data 0 1 0 0 0 0 2 7 7 7 2 2 2 3 5 3 4 5 0 6 7 1 0 1 2 3 4 CAM
- 5. Memory Organization 5 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Cache Mapping – direct mapping - Each memory block has only one place to load in Cache - Mapping Table is made of RAM instead of CAM - n-bit memory address consists of 2 parts; k bits of Index field and n-k bits of Tag field - n-bit addresses are used to access main memory and k-bit Index is used to access the Cache Addressing Relationships Direct Mapping Cache Organization Memory address Memory data 00000 1 2 2 0 00777 01000 01777 02000 02777 2 3 4 0 3 4 5 0 4 5 6 0 5 6 7 0 6 7 1 0 Index address Tag Data 000 0 0 1 2 2 0 0 2 6 7 1 0777 Cache memory Tag(6) Index(9) 32K x 12 Main memory Address = 15 bits Data = 12 bits 512 x 12 Cache memory Address = 9 bits Data = 12 bits 00 000 77 777 000 777
- 6. Memory Organization 6 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Cache Mapping – direct mapping Operation - CPU generates a memory request with (TAG;INDEX) - Access Cache using INDEX ; (tag; data) Compare TAG and tag - If matches -> Hit Provide Cache[INDEX](data) to CPU - If not match -> Miss M[tag;INDEX] <- Cache[INDEX](data) Cache[INDEX] <- (TAG;M[TAG; INDEX]) CPU <- Cache[INDEX](data) Direct Mapping with block size of 8 words 000 0 1 3 4 5 0 007 0 1 6 5 7 8 010 017 770 0 2 777 0 2 6 7 1 0 Block 0 Block 1 Block 63 Tag Block Word INDEX
- 7. Memory Organization 7 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Cache Mapping – Set Associative Mapping Set Associative Mapping Cache with set size of two - Each memory block has a set of locations in the Cache to load Index Tag Data 000 0 1 3 4 5 0 0 2 5 6 7 0 Tag Data 777 0 2 6 7 1 0 0 0 2 3 4 0 Operation - CPU generates a memory address(TAG; INDEX) - Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1, data 1)) - Compare TAG and tag 0 and then tag 1 - If tag i = TAG -> Hit, CPU <- data i - If tag i TAG -> Miss, Replace either (tag 0, data 0) or (tag 1, data 1), Assume (tag 0, data 0) is selected for replacement, (Why (tag 0, data 0) instead of (tag 1, data 1) ?) M[tag 0, INDEX] <- Cache[INDEX](data 0) Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]), CPU <- Cache[INDEX](data 0)
- 8. Memory Organization 8 Lecture 42 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Cache Write Write Through When writing into memory If Hit, both Cache and memory is written in parallel If Miss, Memory is written For a read miss, missing block may be overloaded onto a cache block Memory is always updated -> Important when CPU and DMA I/O are both executing Slow, due to the memory access time Write-Back (Copy-Back) When writing into memory If Hit, only Cache is written If Miss, missing block is brought to Cache and write into Cache For a read miss, candidate block must be written back to the memory Memory is not up-to-date, i.e., the same item in Cache and memory may have different value