This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
State-space averaged modeling and transfer function derivation of DC-DC boost...TELKOMNIKA JOURNAL
This paper presents dynamic analysis of a boost type DC-DC converter for high-brightness LED (HBLED) driving applications. The steady state operation in presence of all system parasitics has been discussed for continuous conduction mode (CCM). The state-space averaging, energy conservation principle and standard linearization are used to derive ac small signal control to inductor current open-loop transfer function of the converter. The derived transfer function can be further used in designing a robust feed-back control network for the system. In the end frequency and transient responses of the derived transfer function are obtained for a given set of component values, hence to provide a useful guide for control design engineers.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses optimal placement of flexible AC transmission system (FACTS) devices on transmission lines to maximize power transfer capability while maintaining stability. It presents a two-stage approach using conventional methods and fuzzy logic. In the first stage, optimal location of a shunt FACTS device is determined for a series-compensated transmission line. In the second stage, fuzzy logic determines the optimal placement. The method is applied to a 13.8kV, 6*350MVA, 360km transmission line. It is observed that the optimal shunt FACTS device location shifts towards the generator side as the level of series compensation increases.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
State-space averaged modeling and transfer function derivation of DC-DC boost...TELKOMNIKA JOURNAL
This paper presents dynamic analysis of a boost type DC-DC converter for high-brightness LED (HBLED) driving applications. The steady state operation in presence of all system parasitics has been discussed for continuous conduction mode (CCM). The state-space averaging, energy conservation principle and standard linearization are used to derive ac small signal control to inductor current open-loop transfer function of the converter. The derived transfer function can be further used in designing a robust feed-back control network for the system. In the end frequency and transient responses of the derived transfer function are obtained for a given set of component values, hence to provide a useful guide for control design engineers.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses optimal placement of flexible AC transmission system (FACTS) devices on transmission lines to maximize power transfer capability while maintaining stability. It presents a two-stage approach using conventional methods and fuzzy logic. In the first stage, optimal location of a shunt FACTS device is determined for a series-compensated transmission line. In the second stage, fuzzy logic determines the optimal placement. The method is applied to a 13.8kV, 6*350MVA, 360km transmission line. It is observed that the optimal shunt FACTS device location shifts towards the generator side as the level of series compensation increases.
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Analysis of multiport dc dc converter in renewable energy sourceseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The effect of ripple steering on control loop stability for ac cm pfc boost c...Murray Edington
This document discusses the effect of ripple steering on control loop stability for continuous conduction mode (CCM) power factor correction (PFC) boost converters. It presents an average switch model approach to modeling the power stage, feedback compensation, and dynamics. Transfer functions are derived for a conventional boost converter and then a PFC boost converter with coupled magnetic filter. Experimental and simulation results from a 1.8 kW prototype verify the analytical work and model's ability to predict steady-state and dynamic behavior of CCM PFC boost converters with coupled magnetic filters. Ripple steering is shown to improve EMI filtering and reduce component sizes while allowing similar control strategies to conventional boost converters.
This document describes a class-G headphone amplifier designed in 65nm CMOS technology. The class-G amplifier uses two voltage supply rails and switches between them based on the output voltage level to improve efficiency. A novel switching technique called "switching currents injection" is used to enable a smooth transition between the supply rails with low distortion. The integrated circuit operates from 1.4V and 0.35V supplies. It achieves over 80dB THD+N for outputs over 16mW into 32 ohms headphones while consuming only 0.41mW of quiescent power. The active die area is 0.14mm2.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
The document proposes a bus encoder design to reduce crosstalk and power dissipation in RLC modeled VLSI interconnects. It introduces a modified bus invert encoding method using counters to count different types of crosstalk couplings. The encoder divides the data bus into clusters of 4 data bits and 1 control bit. It uses counters to count type-0, type-1 couplings with original and inverted data. The counts are compared and the control bit determines if original or inverted data is transmitted, reducing switching activity and crosstalk. Simulation results show the proposed encoder reduces power dissipation and crosstalk induced delay by 55.43% and 45.87% respectively compared to previous designs.
An Enhanced Flying Capacitor Multilevel Inverter fed Induction Motor DriveIDES Editor
This paper focused on the development of
capacitor voltage balancing methods in a flying capacitor
multilevel inverter (FCMLI) fed induction motor drive.
For improving the performance of flying capacitor
multilevel inverter, a switching pattern selection scheme
is implemented. The proposed method has been designed
a nine -level flying capacitor multilevel inverter by using
sinusoidal pulse width modulation technique. The selected
pattern has been exposed to give superior performance in
load voltage, total harmonics distortion and capacitor
voltage fluctuation. The performance of proposed
strategies is confirmed through simulation investigations.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel I...IJPEDS-IAES
This paper proposes a switching control for a cascaded H-bridge inverter
structure with reduced switches which is used to improve the THD
performance of a single phase five level CHB MLI. The multi level inverter
is simulated for the conventional carrier overlapping APOD and the proposed
carrier overlapping APOD pulse width modulation (PWM) switching control
technique. The total harmonic distortion (THD) of the output voltages are
observed for both PWM control techniques. The performance of the
symmetric CHB MLI is simulated using MATLAB/Simulink. It is observed
that the proposed carrier overlapping APODPWM provides output with
relatively low THD as compared to the conventional carrier overlapping
APODPWM.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Full IEDM paper version - as last submittedDavid Goren
This paper proposes an air-core slab inductor structure to achieve ultra-high Q for on-chip power conversion circuits with over 90% efficiency. The structure uses a wide, thick metal slab with specially designed current return paths on either side to minimize DC resistance. Experiments demonstrate Q values as high as 25-35 at 200-300MHz, achieving 96.6% estimated inductor efficiency. Simulations of buck converters using the proposed inductor design show over 90% conversion efficiency for 2:1 voltage ratios. The structure can be implemented in a standard CMOS backend process without thin-film magnetics.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Multilevel inverters have become more popular over the years in electric high power application
with the promise of less disturbances and the possibility to function at lower switching frequencies than
ordinary two-level inverters. This paper presents information about several multilevel inverter topologies,
such as the Neutral-Point Clamped Inverter and the Cascaded Multi cell Inverter. These multilevel
inverters will also be compared with two-level inverters in simulations to investigate the advantages of
using multilevel inverters. Modulation strategies, component comparison and solutions to the multilevel
voltage source balancing problem will also be presented in this work.
Keywords — multilevel, Neutral-clamped, PWM.
In high power DC applications, the single-phase DC-DC converter will face large voltage and current stress in each control switch and thereby the power handling capacity is less. To overcome this problem, three-phase DC-DC converter is used and it is suitable for high power applications with reduced number of switches as compared with the conventional topologies. The asymmetrical duty cycle control is considered to operate the switches under soft switching and hence the switching losses are reduced. The transformer leakage inductances are used along with junction capacitances in order to form resonance and hence ZVS commutation is possible in a wider load range. The modified phase shift control method is used for the proposed converter.The operational modes and design equations of the proposed converter have been observed. The simulation is carried out with a load of 1000W for validating the proposed work.
Synchronous Rectification for Forward Converters_SMappus_June 4 2010Steve Mappus
This document summarizes techniques for improving the efficiency of power converters by replacing diode rectifiers with synchronous rectifiers (SRs) using MOSFETs. SRs can reduce conduction losses by lowering the equivalent forward voltage drop compared to diodes. However, SRs introduce additional losses related to their body diode and switching operation that must be minimized through proper gate driving and timing. Integrating a Schottky diode with the SR MOSFET in a single package helps reduce body diode losses and reverse recovery effects. Optimizing the gate driving method and timing is critical for SR performance in forward converters.
This document summarizes a research paper that proposes a soft-switched PWM zero-voltage switching (ZVS) full bridge DC-DC converter. It introduces a circuit with an auxiliary transformer to achieve ZVS over a wide load range with minimal circulating energy. The auxiliary transformer provides a path for current through a primary inductor used to store ZVS energy. This adaptive energy storage allows ZVS even at no load, reducing component sizes and secondary-side duty cycle losses compared to conventional phase-shift full bridge converters. The document examines the circuit design and operation in detail.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
IRJET- Review on Cascaded Quasi-Z-Source NetworkIRJET Journal
1) The document proposes a cascaded quasi-Z-source converter that can be used as a power conditioning unit to connect low voltage renewable energy sources like fuel cells and solar panels to residential loads.
2) A cascaded quasi-Z-source network is presented that can reduce component values and minimize energy loss compared to a traditional single-stage quasi-Z-source converter.
3) Simulation results show the effectiveness of the proposed cascaded quasi-Z-source inverter, and two potential applications are discussed: a solar water pumping system and connecting a PV system to a microgrid.
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Analysis of multiport dc dc converter in renewable energy sourceseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The effect of ripple steering on control loop stability for ac cm pfc boost c...Murray Edington
This document discusses the effect of ripple steering on control loop stability for continuous conduction mode (CCM) power factor correction (PFC) boost converters. It presents an average switch model approach to modeling the power stage, feedback compensation, and dynamics. Transfer functions are derived for a conventional boost converter and then a PFC boost converter with coupled magnetic filter. Experimental and simulation results from a 1.8 kW prototype verify the analytical work and model's ability to predict steady-state and dynamic behavior of CCM PFC boost converters with coupled magnetic filters. Ripple steering is shown to improve EMI filtering and reduce component sizes while allowing similar control strategies to conventional boost converters.
This document describes a class-G headphone amplifier designed in 65nm CMOS technology. The class-G amplifier uses two voltage supply rails and switches between them based on the output voltage level to improve efficiency. A novel switching technique called "switching currents injection" is used to enable a smooth transition between the supply rails with low distortion. The integrated circuit operates from 1.4V and 0.35V supplies. It achieves over 80dB THD+N for outputs over 16mW into 32 ohms headphones while consuming only 0.41mW of quiescent power. The active die area is 0.14mm2.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
The document proposes a bus encoder design to reduce crosstalk and power dissipation in RLC modeled VLSI interconnects. It introduces a modified bus invert encoding method using counters to count different types of crosstalk couplings. The encoder divides the data bus into clusters of 4 data bits and 1 control bit. It uses counters to count type-0, type-1 couplings with original and inverted data. The counts are compared and the control bit determines if original or inverted data is transmitted, reducing switching activity and crosstalk. Simulation results show the proposed encoder reduces power dissipation and crosstalk induced delay by 55.43% and 45.87% respectively compared to previous designs.
An Enhanced Flying Capacitor Multilevel Inverter fed Induction Motor DriveIDES Editor
This paper focused on the development of
capacitor voltage balancing methods in a flying capacitor
multilevel inverter (FCMLI) fed induction motor drive.
For improving the performance of flying capacitor
multilevel inverter, a switching pattern selection scheme
is implemented. The proposed method has been designed
a nine -level flying capacitor multilevel inverter by using
sinusoidal pulse width modulation technique. The selected
pattern has been exposed to give superior performance in
load voltage, total harmonics distortion and capacitor
voltage fluctuation. The performance of proposed
strategies is confirmed through simulation investigations.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel I...IJPEDS-IAES
This paper proposes a switching control for a cascaded H-bridge inverter
structure with reduced switches which is used to improve the THD
performance of a single phase five level CHB MLI. The multi level inverter
is simulated for the conventional carrier overlapping APOD and the proposed
carrier overlapping APOD pulse width modulation (PWM) switching control
technique. The total harmonic distortion (THD) of the output voltages are
observed for both PWM control techniques. The performance of the
symmetric CHB MLI is simulated using MATLAB/Simulink. It is observed
that the proposed carrier overlapping APODPWM provides output with
relatively low THD as compared to the conventional carrier overlapping
APODPWM.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Full IEDM paper version - as last submittedDavid Goren
This paper proposes an air-core slab inductor structure to achieve ultra-high Q for on-chip power conversion circuits with over 90% efficiency. The structure uses a wide, thick metal slab with specially designed current return paths on either side to minimize DC resistance. Experiments demonstrate Q values as high as 25-35 at 200-300MHz, achieving 96.6% estimated inductor efficiency. Simulations of buck converters using the proposed inductor design show over 90% conversion efficiency for 2:1 voltage ratios. The structure can be implemented in a standard CMOS backend process without thin-film magnetics.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Multilevel inverters have become more popular over the years in electric high power application
with the promise of less disturbances and the possibility to function at lower switching frequencies than
ordinary two-level inverters. This paper presents information about several multilevel inverter topologies,
such as the Neutral-Point Clamped Inverter and the Cascaded Multi cell Inverter. These multilevel
inverters will also be compared with two-level inverters in simulations to investigate the advantages of
using multilevel inverters. Modulation strategies, component comparison and solutions to the multilevel
voltage source balancing problem will also be presented in this work.
Keywords — multilevel, Neutral-clamped, PWM.
In high power DC applications, the single-phase DC-DC converter will face large voltage and current stress in each control switch and thereby the power handling capacity is less. To overcome this problem, three-phase DC-DC converter is used and it is suitable for high power applications with reduced number of switches as compared with the conventional topologies. The asymmetrical duty cycle control is considered to operate the switches under soft switching and hence the switching losses are reduced. The transformer leakage inductances are used along with junction capacitances in order to form resonance and hence ZVS commutation is possible in a wider load range. The modified phase shift control method is used for the proposed converter.The operational modes and design equations of the proposed converter have been observed. The simulation is carried out with a load of 1000W for validating the proposed work.
Synchronous Rectification for Forward Converters_SMappus_June 4 2010Steve Mappus
This document summarizes techniques for improving the efficiency of power converters by replacing diode rectifiers with synchronous rectifiers (SRs) using MOSFETs. SRs can reduce conduction losses by lowering the equivalent forward voltage drop compared to diodes. However, SRs introduce additional losses related to their body diode and switching operation that must be minimized through proper gate driving and timing. Integrating a Schottky diode with the SR MOSFET in a single package helps reduce body diode losses and reverse recovery effects. Optimizing the gate driving method and timing is critical for SR performance in forward converters.
This document summarizes a research paper that proposes a soft-switched PWM zero-voltage switching (ZVS) full bridge DC-DC converter. It introduces a circuit with an auxiliary transformer to achieve ZVS over a wide load range with minimal circulating energy. The auxiliary transformer provides a path for current through a primary inductor used to store ZVS energy. This adaptive energy storage allows ZVS even at no load, reducing component sizes and secondary-side duty cycle losses compared to conventional phase-shift full bridge converters. The document examines the circuit design and operation in detail.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
IRJET- Review on Cascaded Quasi-Z-Source NetworkIRJET Journal
1) The document proposes a cascaded quasi-Z-source converter that can be used as a power conditioning unit to connect low voltage renewable energy sources like fuel cells and solar panels to residential loads.
2) A cascaded quasi-Z-source network is presented that can reduce component values and minimize energy loss compared to a traditional single-stage quasi-Z-source converter.
3) Simulation results show the effectiveness of the proposed cascaded quasi-Z-source inverter, and two potential applications are discussed: a solar water pumping system and connecting a PV system to a microgrid.
Application of PWM Control Strategy on Z-Source Isolated Dual active bridge D...IJMER
This project presents a Z-source with bidirectional dc–dc converter. The switching count is
reduced by adding a passive element. Thus, we are improving the output voltage level. The voltage
regulation range of proposed converter is better than that of the traditional bidirectional dc–dc
converter. The fully bridge symmetrical circuit configuration, is neither a high-voltage side nor a lowvoltage
side in the circuit structure, and the sources connected to the dc side of each H-bridge circuit
with voltage sources and current sources. This method can reduce current stress and improves the
system efficiency.
In this paper we are presenting a dual active bridge (DAB) dc–dc converter is also known as
Bidirectional DC-DC converter. Both simulation results are shown by using MATLAB software.
IRJET - Comparative Study of Different AC-DC Converter for High Step DownIRJET Journal
This document compares a single-stage three-phase AC-DC converter using SiC MOSFETs to a conventional two-stage AC-DC converter. The single-stage converter removes the need for a separate DC-DC stage by using a high frequency transformer to directly step down the voltage from the PFC stage. This makes the design more compact and efficient with lower costs compared to the conventional two-stage approach with its 10 switches and separate DC-DC stage. Simulation results show the THD is reduced to 10% and efficiency increased to 95% with the proposed single-stage design.
This paper addresses the approach to improve the efficiency of the quasi Z-source inverter. In order to increase the efficiency the reduction of conduction losses is one way to approach. Sequentially to decrease the conduction losses in the quasi z-source inverter the replacement of diode is replacing with switches is proposed which is also called as synchronous rectification. The paper represents basics of the approach, analysis and comparison of the power losses of the traditional and proposed designs of the grid connected PV-system with quasi z-source inverter system. The proposed approach validated on the computer simulations in the MATLAB environment.
THREE-PHASE OF BI-DIRECTIONAL Z-SOURCE CONVERTERS FOR VEHICLE-TO-GRID APPLICA...IRJET Journal
This document discusses a closed-loop control method for three-phase bi-directional Z-source converters used in vehicle-to-grid applications. It proposes using a PI voltage regulator with a fuzzy logic-tuned hysteresis current regulator. Simulations show this combination provides improved performance with total harmonic distortion of 0.93% for the source current and near unity power factor. The control scheme maintains total harmonic distortion below 5% for load variations between 25-100% and ensures stable output voltage regulation even when load resistance changes.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
This document presents a comparative investigation of a 7-level cascaded multilevel inverter using different multicarrier pulse width modulation techniques. It discusses the classification, operation, and modulation strategies of multilevel inverters including diode clamped, flying capacitor, and cascaded H-bridge topologies. Simulation results in MATLAB/Simulink are presented to analyze the total harmonic distortion for a 7-level cascaded H-bridge multilevel inverter using phase disposition, alternate phase opposition disposition, and phase opposition disposition pulse width modulation techniques. The research aims to improve the output waveform quality and reduce switching losses of the 7-level inverter.
Transformerless Topology for Grid-Conected Inverters With Unipolar PWM ControlIJERA Editor
Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having good efficiency. To overcome these problems, transformer less PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformer less inverters like H5, H6, HERIC, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformer less inverter is to address two key issues: One key issue for a transformer less inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.
1) The document presents a new zero-voltage switching (ZVS) topology for a three-phase grid-connected inverter. The topology uses an additional active clamping leg to achieve ZVS for all the main switches.
2) A new space vector modulation scheme is proposed to control the inverter such that the auxiliary switch operates at the same frequency as the main switches. This ensures ZVS turn-on of the main switches.
3) Simulation results on a 30kW prototype verify that the ZVS topology reduces switching losses, improves efficiency, and makes the inverter suitable for practical high power applications.
IRJET- Power Quality Improvement by Harmonic Reduction using Compact Desi...IRJET Journal
This document summarizes a research paper that proposes a new multilevel inverter design with reduced number of switches to improve power quality by reducing harmonic distortion. The proposed design is a 21-level cascaded H-bridge inverter topology that uses only 24 switches compared to other multilevel inverter designs. The performance of the proposed inverter is validated through MATLAB simulation, which shows it can generate a 21-level output voltage waveform with 10.65% total harmonic distortion under no load conditions.
Simulation of H6 full bridge Inverter for grid connected PV system using SPWM...IRJET Journal
This document proposes a new H6 full bridge inverter topology for grid-connected photovoltaic systems using sinusoidal pulse width modulation (SPWM) technique. It aims to reduce common mode leakage currents compared to existing H5 and HERIC inverter topologies. The H6 topology adds two additional switches to the DC side of the full bridge inverter. SPWM pulses for the additional switches are designed to keep the common mode voltage constant during all operating modes, which effectively reduces leakage currents. The MATLAB simulation software is used to simulate the proposed H6 inverter topology and validate the concept.
Zero-Current-Switching Current-Fed Half-Bridge Isolated DC/DC Converter for F...IRJET Journal
This document presents a dual inductor based current-fed bidirectional isolated DC/DC converter for fuel cell and photovoltaic applications. The proposed converter provides higher voltage conversion and zero voltage switching without a snubber circuit. It eliminates voltage spikes by adding soft-switching features. A mathematical design is discussed for a 300W prototype. Key benefits include reduced component count, lower cost, compact size, and higher efficiency compared to hard-switched converters through zero-current switching. The converter is suitable for applications like fuel cells and electric vehicles due to its bidirectional capability.
IRJET - A Zero Voltage Switching Pulse Width Modulated Multilevel Buck ConverterIRJET Journal
This document presents a new five-level zero voltage switching pulse width modulated multilevel buck converter. The proposed converter uses a multilevel topology to reduce voltage stresses on switches without adding extra voltage. It achieves zero voltage switching for all switches by utilizing active clamping and circulating reactive energy throughout the converter. Simulations in MATLAB were used to verify the performance of the proposed converter. The converter design and operating principles are explained, including modes of operation, component sizing equations, and simulation details.
Analysis of Impedance Source Inverter Topologies for Grid Integration of PV I...IJPEDS-IAES
In this paper, the performance of different Impedance Source Inverter (ZSI)
topologies in implementing single stage power conversion for grid
ingetertion of PV power converters is discussed. Unlike the traditional
inverters, ZSI employs a distinctive impedance network, there by making
shoot-through state is possible. The independent control variables are shootthrough
duty ratio and modulation index. Simple Boost Control pulse width
modulation technique was used in this work to vary the modulation index.
Here the basic operation, simple boost control method, characteristics,
requirements and harmonic analysis of the classical Z-Source Inverter (ZSI),
TZ-Source Inverter (TZSI), Trans-Z-Source Inverter (Trans-ZSI) and
Improved ZSI (IMZSI) topologies were compared for interfacing the wide
range variable input energy to utility supply system. The performances were
compared based on its MATLAB/SIMULINK simulation model and featured
results are shown to confirm its validity.
Reduction of common mode voltage for cascaded multilevel inverters using phas...nooriasukmaningtyas
Demand of cascaded multilevel inverters in industries of electric drives and
renewable energy is increasing due to their large-scale capacity and high
voltage. The modulation technique of inverters significantly affects the
power quality of the inverter output voltage. This paper proposes a new
method of carrier wave modulation using the phase shift keying technique for
cascaded multilevel inverters. The phase of a constant frequency carrier wave
is changed at an accurate time by an input sinusoidal control signal. This
modulation technique is simply implemented and only needs a small
memory. It also helps reduce the common mode voltage of inverters in order
to suppress the output voltage harmonics. Moreover, the ability to reduce
switching count also helps the inverters decrease switching loss. The
simulated and experienced results on a cascaded 9-level 3-phase inverter and
an F28379D DSP kit have validated the performance of the proposed
technique compared with that of the APOD and POD methods.
A DC Inrush Current Minimisation Method using Modified Z-Source Inverter in A...IAES-IJPEDS
The adjustable speed drives employ PWM converter-inverter system in order
to obtain unity power factor. The DC inrush current in DC link capacitors of
the rectifier limits the operation of power devices. Hence, this paper proposes
a new approach to reduce the DC inrush current by employing modified
Z-source inverter in a Adjustable Speed Drive system. The operating
principles, design procedure and simulation results are shown and compared
with the conventional Z-Source inverter.
IRJET- An Inclusive Review on Various Multilevel Converter Topologies for a G...IRJET Journal
This document reviews various multilevel inverter topologies that can be used for grid-connected photovoltaic systems. It discusses four main topologies: diode-clamped, flying capacitor, cascaded, and Z-source inverters. For each topology, the document outlines their construction, advantages, and disadvantages when used in renewable energy power systems. It finds that cascaded inverters require fewer components than other topologies but many separate DC sources, while diode-clamped and flying capacitor inverters can share a single DC source but have more complex voltage balancing requirements. The review aims to help selection of the appropriate multilevel inverter topology based on specific system needs and tradeoffs between component counts and control complexity
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Artificial intelligence (AI) | Definitio