This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
This paper presents a low-voltage CMOS voltage-mode divider circuit that can operate with a low supply voltage and low power dissipation. The proposed divider circuit was fabricated in a 0.5 μm CMOS process and can operate with a 2.5 V supply voltage. Experimental results show the divider has less than 1.18% linearity error and consumes only 102 μW of power. The divider circuit is also used to realize a pseudo-exponential function generator with a 15 dB output dynamic range and less than 1.54% linear error. Both circuits are suitable for analog signal processing applications requiring low voltage and low power operation.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Single-Switch Soft-Switched Boost Power Factor Corrector for Modular Applicat...IAES-IJPEDS
Modern dc power supplies provide power factor correction but the classical two-stage approach,
using hard-switched preregulators, has detrimental effects on efficiency and reliability,
particularly for high power applications. With some circuit modifications and the
addition of a few magnetic components, diodes and capacitors, we have turned a classical
boost power factor corrector into a high efficiency soft-switched version. The proposed
converter turns on its single switch with zero current and turns it off with zero voltage. In
this paper we explain the proposed changes, we study the waveforms and equations and we
verify them with an experimental prototype. We also show how the converter can be used
for modular single- and three-phase high power applications.
High Speed, Low Power Current Comparators with HysteresisVLSICS Design
This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
This document describes several alternative dual-bridge matrix converter topologies that have a reduced number of switches compared to a conventional matrix converter. It discusses how the dual-bridge topology avoids commutation problems of the conventional design. It then introduces several dual-bridge topologies with fewer switches, including 18-, 15-, 12-, and 9-switch variations. It analyzes the characteristics and operation of these topologies, and presents simulation and experimental results for the 9-switch design to validate its feasibility.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
This paper presents a low-voltage CMOS voltage-mode divider circuit that can operate with a low supply voltage and low power dissipation. The proposed divider circuit was fabricated in a 0.5 μm CMOS process and can operate with a 2.5 V supply voltage. Experimental results show the divider has less than 1.18% linearity error and consumes only 102 μW of power. The divider circuit is also used to realize a pseudo-exponential function generator with a 15 dB output dynamic range and less than 1.54% linear error. Both circuits are suitable for analog signal processing applications requiring low voltage and low power operation.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Single-Switch Soft-Switched Boost Power Factor Corrector for Modular Applicat...IAES-IJPEDS
Modern dc power supplies provide power factor correction but the classical two-stage approach,
using hard-switched preregulators, has detrimental effects on efficiency and reliability,
particularly for high power applications. With some circuit modifications and the
addition of a few magnetic components, diodes and capacitors, we have turned a classical
boost power factor corrector into a high efficiency soft-switched version. The proposed
converter turns on its single switch with zero current and turns it off with zero voltage. In
this paper we explain the proposed changes, we study the waveforms and equations and we
verify them with an experimental prototype. We also show how the converter can be used
for modular single- and three-phase high power applications.
High Speed, Low Power Current Comparators with HysteresisVLSICS Design
This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...IRJET Journal
This document summarizes a wireless power transfer system that uses a pulse density modulation based full bridge converter. The converter employs a zero-voltage switching technique to provide soft switching and improve efficiency. The existing pulse density modulation strategy for the converter has limitations like large low frequency subharmonics, a narrow modulation range, and large modulation delay. The document proposes a new pulse density modulation strategy that allows for asymmetric zero-voltage switching currents to overcome these limitations. Simulation results show the proposed strategy reduces subharmonics, achieves a wider modulation range, and faster response compared to the existing strategy.
This document describes several alternative dual-bridge matrix converter topologies that have a reduced number of switches compared to a conventional matrix converter. It discusses how the dual-bridge topology avoids commutation problems of the conventional design. It then introduces several dual-bridge topologies with fewer switches, including 18-, 15-, 12-, and 9-switch variations. It analyzes the characteristics and operation of these topologies, and presents simulation and experimental results for the 9-switch design to validate its feasibility.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
1) The document discusses power flow analysis of a three bus power system using circuit theory concepts. It introduces notation for generation (q) and load (x) at each bus and derives an equation relating power flow between two buses to the generation and loads.
2) It models the system as an electric circuit with current sources representing generation (q) and loads (x) at each node. Through techniques like current division and superposition, the document derives the same power flow equation relating the flow between two buses to the differences in generation and loads at those buses.
3) It introduces the concept of "Ohm's law for real power flow" which relates the real power flow on a line to the difference in voltage
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C.
Closed Loop Analysis of Single-Inductor Dual-Output Buck Converters with Mix-...IOSR Journals
This document presents an analysis of closed loop operation of single-inductor dual-output buck converters. It begins with an overview of these converters and their applications. It then analyzes the circuit operation in both continuous and discontinuous conduction modes, developing equations for voltage gains, duty cycles, and other parameters. Most importantly, it identifies a new "mix-voltage" operation mode where the input voltage can be lower than one output voltage. Experimental results are presented to validate the analytical equations and this new operating mode.
This document analyzes diode emulation in synchronous buck converters operating under light load conditions. It discusses how diode emulation reduces output voltage ripple and inductor current ripple compared to continuous conduction mode. It also examines transient response and power losses. While diode emulation improves efficiency by reducing losses, extra transitions can cause overshoot during load changes. The document proposes a scheme to separate diode emulation transitions from regular load transients to reduce overshoot. Experimental results are presented to validate the analysis and effectiveness of the proposed scheme.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
A New Configuration of a High Output Voltage 2.45 GHz Rectifier for Wireless ...TELKOMNIKA JOURNAL
This work deals with the design, simulation, fabrication and experimentation of a novel 2.45 GHz rectifier for wireless power transmission applications. We have designed a voltage multiplier topology rectifier including 5 Schottky diodes known by their low threshold. This rectifier could perform a wireless power supply for many cases where the use of batteries or wires is impossible due to many limitations. The circuit was analyzed and optimized with the Harmonic Balance method provided by the Advanced Design System (ADS). Good performances are observed through the simulated results and confirmed by the fabrication tests in terms of RF-DC conversion efficiency, DC output voltage level and matching input impedance.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
EE456_NWPUD Transmission Reinforcement Planningki hei chan
The document presents two design options for upgrading the transmission system to accommodate load growth and a new wind farm. The first design connects the wind farm to bus 4 and costs $37.2 million with annual costs of $1.657 million. It requires upgrading 64.5 miles of conductors and adding 43 miles of new lines. The second design connects the wind farm to buses 14 and 27 using three transmission lines and costs $43.9 million with annual costs of $1.889 million. It requires more materials and right of way. A cost-benefit analysis determined the first design to be the most cost-effective option.
TOWARDS TEMPERATURE-INSENSITIVE NANOSCALE CMOS CIRCUITS WITH ADAPTIVELY REGUL...VLSICS Design
In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuitscan be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage limiteris integrated into the proposed power supply to cap the supply voltage. Using this proposed adaptive voltage source to power individual CMOS logic gates and/or subsystems will free the chips from using expensive high-precision temperature sensors for thermal management and performance tuning. Experiments on various benchmark circuits, which are implemented with a 45nm CMOS technology, have confirmed that the circuit delay variation can be reduced to 15%~30% over a wide temperature range (0℃ to 90℃), a sharp contrast to the large delay variations(50%~75%)observed in most IC designs where a
constant power supply is employed.
HARMONICS AND INTERHARMONICS ESTIMATION OF A PASSIVE MAGNETIC FAULT CURRENT L...cscpconf
This paper presents the harmonics and interharmonics analysis of a passive magnetic fault current limiter (MFCL). This device limits the current at post fault without affecting the pre-fault state of the system. The harmonics and interharmonics estimation of a non-stationary signal generated by MFCL has been investigated using Morlet Wavelet transform and FFT.Continous wavelet transform (CWT) have been applied for estimation of harmonics and
interharmonics in MFCL under normal and faulted condition.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
1) The document discusses power flow analysis of a three bus power system using circuit theory concepts. It introduces notation for generation (q) and load (x) at each bus and derives an equation relating power flow between two buses to the generation and loads.
2) It models the system as an electric circuit with current sources representing generation (q) and loads (x) at each node. Through techniques like current division and superposition, the document derives the same power flow equation relating the flow between two buses to the differences in generation and loads at those buses.
3) It introduces the concept of "Ohm's law for real power flow" which relates the real power flow on a line to the difference in voltage
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C.
Closed Loop Analysis of Single-Inductor Dual-Output Buck Converters with Mix-...IOSR Journals
This document presents an analysis of closed loop operation of single-inductor dual-output buck converters. It begins with an overview of these converters and their applications. It then analyzes the circuit operation in both continuous and discontinuous conduction modes, developing equations for voltage gains, duty cycles, and other parameters. Most importantly, it identifies a new "mix-voltage" operation mode where the input voltage can be lower than one output voltage. Experimental results are presented to validate the analytical equations and this new operating mode.
This document analyzes diode emulation in synchronous buck converters operating under light load conditions. It discusses how diode emulation reduces output voltage ripple and inductor current ripple compared to continuous conduction mode. It also examines transient response and power losses. While diode emulation improves efficiency by reducing losses, extra transitions can cause overshoot during load changes. The document proposes a scheme to separate diode emulation transitions from regular load transients to reduce overshoot. Experimental results are presented to validate the analysis and effectiveness of the proposed scheme.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
A New Configuration of a High Output Voltage 2.45 GHz Rectifier for Wireless ...TELKOMNIKA JOURNAL
This work deals with the design, simulation, fabrication and experimentation of a novel 2.45 GHz rectifier for wireless power transmission applications. We have designed a voltage multiplier topology rectifier including 5 Schottky diodes known by their low threshold. This rectifier could perform a wireless power supply for many cases where the use of batteries or wires is impossible due to many limitations. The circuit was analyzed and optimized with the Harmonic Balance method provided by the Advanced Design System (ADS). Good performances are observed through the simulated results and confirmed by the fabrication tests in terms of RF-DC conversion efficiency, DC output voltage level and matching input impedance.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
EE456_NWPUD Transmission Reinforcement Planningki hei chan
The document presents two design options for upgrading the transmission system to accommodate load growth and a new wind farm. The first design connects the wind farm to bus 4 and costs $37.2 million with annual costs of $1.657 million. It requires upgrading 64.5 miles of conductors and adding 43 miles of new lines. The second design connects the wind farm to buses 14 and 27 using three transmission lines and costs $43.9 million with annual costs of $1.889 million. It requires more materials and right of way. A cost-benefit analysis determined the first design to be the most cost-effective option.
TOWARDS TEMPERATURE-INSENSITIVE NANOSCALE CMOS CIRCUITS WITH ADAPTIVELY REGUL...VLSICS Design
In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuitscan be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage limiteris integrated into the proposed power supply to cap the supply voltage. Using this proposed adaptive voltage source to power individual CMOS logic gates and/or subsystems will free the chips from using expensive high-precision temperature sensors for thermal management and performance tuning. Experiments on various benchmark circuits, which are implemented with a 45nm CMOS technology, have confirmed that the circuit delay variation can be reduced to 15%~30% over a wide temperature range (0℃ to 90℃), a sharp contrast to the large delay variations(50%~75%)observed in most IC designs where a
constant power supply is employed.
HARMONICS AND INTERHARMONICS ESTIMATION OF A PASSIVE MAGNETIC FAULT CURRENT L...cscpconf
This paper presents the harmonics and interharmonics analysis of a passive magnetic fault current limiter (MFCL). This device limits the current at post fault without affecting the pre-fault state of the system. The harmonics and interharmonics estimation of a non-stationary signal generated by MFCL has been investigated using Morlet Wavelet transform and FFT.Continous wavelet transform (CWT) have been applied for estimation of harmonics and
interharmonics in MFCL under normal and faulted condition.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
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ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODELVLSICS Design
This document summarizes a research paper on implementing a low power design methodology for recursive encoders and decoders. It discusses how recursive coding can achieve better error correction performance at low signal-to-noise ratios compared to other codes. It then describes the design of a recursive decoder that uses the log-MAP algorithm to minimize power consumption. The decoder uses five main computational steps - branch metric calculation, forward metric computation, backward metric computation, log-likelihood ratio calculation, and extrinsic information calculation. It also compares the implementation of four-state and eight-state recursive encoders. The goal of the design is to optimize the power and area of recursive encoders and decoders.
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
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Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
This document summarizes a research paper that proposes a new low-power full adder cell design using carbon nanotube field-effect transistors (CNTFETs) in 32 nanometer technology. Simulation results show that the design, which uses 24 CNTFETs, reduces power consumption compared to previous CNTFET full adder designs. The power and power-delay product increase with supply voltage but are largely unaffected by temperature. Compared to previous designs, the proposed cell has lower power, delay, and power-delay product, especially at 0.65V supply voltage, demonstrating its improved energy efficiency.
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUITVLSICS Design
This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
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Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
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A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.Suchitra goudar
The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
This document summarizes the design and simulation of a low power, low voltage bulk driven balanced operational transconductance amplifier (OTA) in a 130nm CMOS process with a 0.9V supply. The OTA uses bulk driven NMOS transistors at the input stage to avoid threshold voltage limitations. Simulation results show the OTA achieves a power consumption of 3.9uW with a 550mV output voltage swing. Key performance metrics like gain, bandwidth, slew rate and noise are provided and meet expectations for low power analog circuit design in modern CMOS processes. The bulk driven approach allows designing circuits for voltages lower than transistor thresholds and maintains reasonable performance for low power analog applications.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
This document summarizes a research paper on implementing hysteresis control for space vector pulse width modulation (SVPWM) inverters. It begins by introducing SVPWM and total harmonic distortion (THD). It then describes the principles of SVPWM, including determining switching times and patterns. Next, it defines the hysteresis band control method using a relay function. The document proceeds to model the inverter and describe the switching interval generator and control signal generator blocks. Finally, it provides an overview of the simulation model, which combines hysteresis control with SVPWM.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
The document describes a low power, low phase noise CMOS LC oscillator designed and simulated using a 180nm CMOS technology. Key results include:
1) The oscillator achieves a phase noise of -96 dBc/Hz at 1MHz with a tuning range of 4.8-8.3 GHz by varying the control voltage from 0-2V.
2) It consumes 3.8mW of power at an output power of -8.92dBm.
3) Simulation results show the tuning range, output waveform, and phase noise performance meet design goals for a low power VCO for wireless applications like 5G.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The document presents a novel approach called "stacking with sleepy keeper" for reducing leakage power in 65nm CMOS technologies. It combines transistor stacking, sleep transistors, and sleepy keeper techniques. Simulation results show the proposed approach significantly reduces average and static power compared to basic NAND gates and other techniques. For a 2-input NAND gate, the proposed approach with high Vth transistors reduces average power by 97.32% and static power by 99.24% compared to a basic NAND gate. When implemented in an SRAM cell, the proposed approach also improves power, delay, and power-delay product metrics.
Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power IJECEIAES
This document summarizes a research paper that proposes a Variable Body Biasing (VBB) technique to reduce static power consumption in VLSI design. It describes how VBB works by applying a DC bias to the body terminal of MOSFETs to dynamically control their threshold voltage. A 1-bit full adder circuit was designed using the conventional static CMOS approach and the proposed VBB technique. Simulation results showed that the VBB technique achieved a reduction in peak power and average power compared to the conventional design.
Synaptic memristor bridge circuit with pulse width based programable weights ...inventionjournals
Memristor bridge circuit linearly generates synaptic weights in the range [-1; 1]. A long width pulse programs the synaptic weights and a short width pulse computes multiplication results in ANN model. Each digit is sampled by 10 times, forming 5x4 matrix. Thecharacter recognition rate achieves 100% for digits from 1 through 5 . 5%, 10%, and 15% noisy patterns is added to consider the recognition rate.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Similar to Design of a novel current balanced voltage controlled delay element (20)
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
Generating privacy-protected synthetic data using Secludy and MilvusZilliz
During this demo, the founders of Secludy will demonstrate how their system utilizes Milvus to store and manipulate embeddings for generating privacy-protected synthetic data. Their approach not only maintains the confidentiality of the original data but also enhances the utility and scalability of LLMs under privacy constraints. Attendees, including machine learning engineers, data scientists, and data managers, will witness first-hand how Secludy's integration with Milvus empowers organizations to harness the power of LLMs securely and efficiently.
Driving Business Innovation: Latest Generative AI Advancements & Success StorySafe Software
Are you ready to revolutionize how you handle data? Join us for a webinar where we’ll bring you up to speed with the latest advancements in Generative AI technology and discover how leveraging FME with tools from giants like Google Gemini, Amazon, and Microsoft OpenAI can supercharge your workflow efficiency.
During the hour, we’ll take you through:
Guest Speaker Segment with Hannah Barrington: Dive into the world of dynamic real estate marketing with Hannah, the Marketing Manager at Workspace Group. Hear firsthand how their team generates engaging descriptions for thousands of office units by integrating diverse data sources—from PDF floorplans to web pages—using FME transformers, like OpenAIVisionConnector and AnthropicVisionConnector. This use case will show you how GenAI can streamline content creation for marketing across the board.
Ollama Use Case: Learn how Scenario Specialist Dmitri Bagh has utilized Ollama within FME to input data, create custom models, and enhance security protocols. This segment will include demos to illustrate the full capabilities of FME in AI-driven processes.
Custom AI Models: Discover how to leverage FME to build personalized AI models using your data. Whether it’s populating a model with local data for added security or integrating public AI tools, find out how FME facilitates a versatile and secure approach to AI.
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In his public lecture, Christian Timmerer provides insights into the fascinating history of video streaming, starting from its humble beginnings before YouTube to the groundbreaking technologies that now dominate platforms like Netflix and ORF ON. Timmerer also presents provocative contributions of his own that have significantly influenced the industry. He concludes by looking at future challenges and invites the audience to join in a discussion.
Infrastructure Challenges in Scaling RAG with Custom AI modelsZilliz
Building Retrieval-Augmented Generation (RAG) systems with open-source and custom AI models is a complex task. This talk explores the challenges in productionizing RAG systems, including retrieval performance, response synthesis, and evaluation. We’ll discuss how to leverage open-source models like text embeddings, language models, and custom fine-tuned models to enhance RAG performance. Additionally, we’ll cover how BentoML can help orchestrate and scale these AI components efficiently, ensuring seamless deployment and management of RAG systems in the cloud.
CAKE: Sharing Slices of Confidential Data on BlockchainClaudio Di Ciccio
Presented at the CAiSE 2024 Forum, Intelligent Information Systems, June 6th, Limassol, Cyprus.
Synopsis: Cooperative information systems typically involve various entities in a collaborative process within a distributed environment. Blockchain technology offers a mechanism for automating such processes, even when only partial trust exists among participants. The data stored on the blockchain is replicated across all nodes in the network, ensuring accessibility to all participants. While this aspect facilitates traceability, integrity, and persistence, it poses challenges for adopting public blockchains in enterprise settings due to confidentiality issues. In this paper, we present a software tool named Control Access via Key Encryption (CAKE), designed to ensure data confidentiality in scenarios involving public blockchains. After outlining its core components and functionalities, we showcase the application of CAKE in the context of a real-world cyber-security project within the logistics domain.
Paper: https://doi.org/10.1007/978-3-031-61000-4_16
Monitoring and Managing Anomaly Detection on OpenShift.pdfTosin Akinosho
Monitoring and Managing Anomaly Detection on OpenShift
Overview
Dive into the world of anomaly detection on edge devices with our comprehensive hands-on tutorial. This SlideShare presentation will guide you through the entire process, from data collection and model training to edge deployment and real-time monitoring. Perfect for those looking to implement robust anomaly detection systems on resource-constrained IoT/edge devices.
Key Topics Covered
1. Introduction to Anomaly Detection
- Understand the fundamentals of anomaly detection and its importance in identifying unusual behavior or failures in systems.
2. Understanding Edge (IoT)
- Learn about edge computing and IoT, and how they enable real-time data processing and decision-making at the source.
3. What is ArgoCD?
- Discover ArgoCD, a declarative, GitOps continuous delivery tool for Kubernetes, and its role in deploying applications on edge devices.
4. Deployment Using ArgoCD for Edge Devices
- Step-by-step guide on deploying anomaly detection models on edge devices using ArgoCD.
5. Introduction to Apache Kafka and S3
- Explore Apache Kafka for real-time data streaming and Amazon S3 for scalable storage solutions.
6. Viewing Kafka Messages in the Data Lake
- Learn how to view and analyze Kafka messages stored in a data lake for better insights.
7. What is Prometheus?
- Get to know Prometheus, an open-source monitoring and alerting toolkit, and its application in monitoring edge devices.
8. Monitoring Application Metrics with Prometheus
- Detailed instructions on setting up Prometheus to monitor the performance and health of your anomaly detection system.
9. What is Camel K?
- Introduction to Camel K, a lightweight integration framework built on Apache Camel, designed for Kubernetes.
10. Configuring Camel K Integrations for Data Pipelines
- Learn how to configure Camel K for seamless data pipeline integrations in your anomaly detection workflow.
11. What is a Jupyter Notebook?
- Overview of Jupyter Notebooks, an open-source web application for creating and sharing documents with live code, equations, visualizations, and narrative text.
12. Jupyter Notebooks with Code Examples
- Hands-on examples and code snippets in Jupyter Notebooks to help you implement and test anomaly detection models.
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Design of a novel current balanced voltage controlled delay element
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
DOI : 10.5121/vlsic.2014.5304 37
DESIGN OF A NOVEL CURRENT BALANCED
VOLTAGE CONTROLLED DELAY ELEMENT
Pooja Saxena1
, Sudheer K. M2
, V. B. Chandratre2
1
Homi Bhabha National Institute, Mumbai 400094
2
Electronics Division, Bhabha Atomic Research Center, Trombay, Mumbai 400085
ABSTRACT
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
KEYWORDS
Current Balanced Logic (CBL), Source Coupled Logic (SCL), Current Starved Inverter (CSI), Delay Lock
Loop (DLL), Phase Lock Loop (PLL)
1. INTRODUCTION
Delay Element (DE) is a vital block in Delay Lock Loop (DLL) [1], Phase Lock Loop (PLL) [2],
microprocessor and memory circuits [3] and Time-to-Digital Converters [4]. The aim is to design
a delay element, which assists in time interval (TI) measurement [4] with high resolution (< 200
ps) for High Energy Physics (HEP) experiments. A variety of DEs already has been reported in
the literature [5] with their merits and limitations. The Current Starved Inverter (CSI) is used as a
delay element in time measurement circuits. This structure ensures wide delay regulation range
and low power consumption. The reported delay using CSI is 244 ps [6] in 0.35 µm CMOS
process.
Transmission gate based delay element [5] is fast due to relatively low resistive path between
input and output. It is power and area efficient and has full swing output. However, the delay
increases quadratically with the number of cascaded transmission gates [7]. Differential DE based
on low noise Source Coupled Logic (SCL) [8] [9] [10] mitigates the common mode noise, which
is prevalent in CSI. They are fast but have partial output swing and are power inefficient due to
the high static current. In addition, they require a complex bias circuitry for delay variation.
This paper presents a design of voltage controlled delay element based on modified version of
Current Balanced Logic (CBL) [11] and is referred here as Modified CBL (MCBL) delay
element. The salient features of this delay element are identical delays in the rising and falling
edge transitions, high speed, area efficient, less contribution in the generation of ‘di/dt’ switching
noise and low power consumption as compared to other architectures of differential delay
elements.
The paper is organized in the following sections: In section 2, an overview of current balanced
logic and architecture of MCBL DE is presented. A detailed analysis of the circuit is also
provided. The simulation results are compared with the analytical results. In section 3, a design of
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
38
Delay Lock Loop (DLL) has been presented using MCBL delay element. In Section 4, post
layout simulation results are presented. In section 5, conclusions are drawn.
2. CURRENT BALANCED LOGIC (CBL)
Figure 1. Current Balanced Logic Circuit
Current Balanced Logic (CBL) [10] is the low noise logic family that reduces ‘di/dt’ switching
noise. The noise reduction technique aims to keep the supply current steady. This scheme
modifies pseudo NMOS logic by adding the NMOS transistor ‘M2’ as shown in Figure 1. When
NMOS logic block is on, the output node ‘Out’ is pulled down, which keeps M2 in cut-off
operating region and there is a static supply current through M1. When NMOS logic block is off,
M2 is in saturation and draws the same supply current assuming M1 and M2 are well matched.
2.1. Architecture of MCBL delay element
Figure 2. MCBL Delay element (a) Schematic Diagram (b) Timing Diagram
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
39
Figure 2 represents the schematic and timing diagram of MCBL delay element. The amount of
charging current ‘Icp’ through PMOS transistors ‘M3’ and ‘M4’ controls the rising and falling edge
propagation delays respectively. The current ‘Icp’ is determined by the control voltage ‘Vctrl’. Both
rising ‘Tpr’ and falling ‘Tpf’ edge delays are identical as PMOS ‘M3’ and ‘M4’ as well as NMOS
‘M1’ and ‘M2’ are matched transistors, the nodes ‘Out’ and ‘Outb’ face the same capacitive load
(Cload).
As shown in Figure 2(b), when rising edge transition of ‘Vin’ clock is applied, the ‘Outb’ node
pulls down. The NMOS transistor M2 enters in the cut-off region and PMOS ‘M3’ starts pulling
up the node ‘Out’ by charging the load capacitance ‘Cload’ using ‘Icp’. When falling edge
transition of Vin is applied, ‘M1’ is turned off. Subsequently ‘M4’ starts pulling up the node
‘Outb’. This turns on ‘M2’, which pulls down the node ‘Out’. The pull down is fast as aspect ratio
‘W/L’ of NMOS is designed to be higher than PMOS transistors. The signals Vin and Vout are of
same polarity with identical rising ‘Tpr’ and falling ‘Tpf’ edge delays. The variation in the supply
current is small as equal current path is maintained in rising and falling edge transitions. This
ensures the current balancing.
This MCBL DE can be interfaced to the standard cells available in the PDK (Process Design Kit)
owing to its large output swing. It is fast as compared to CSI, shown in Figure 3, as the resistance
of charging path of capacitive load ‘Cload’ is less. There is only one transistor ‘M3’ in the charging
path for MCBL while in CSI, there are two series connected transistors M7 and M8. In the
cascaded delay line, the MCBL DE faces a single transistor (M1) load (gate capacitance) as
compared to two transistors (M6 and M7) load in CSI. This further reduces the propagation delay
of MCBL DE. The static current is small as compared to differential delay elements. Further, this
DE has wide delay tuning range with respect to control voltage.
Figure 3. Schematic Diagram of CSI
2.2. Analysis of the MCBL delay element
This section describes the equation for propagation delay as well as output voltages VOL
(maximum output voltage in logic ‘0’) and VOH (minimum output voltage in logic ‘1’).
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
40
2.2.1. Calculation of VOL and VOH
To ensure the compatibility of DE to be interfaced with the standard cells, it is required to
calculate VOL and VOH over a control voltage range. In the calculation of VOL, it is assumed that
Vin is less than the threshold voltage ‘Vtn’ of M1 (Vin< Vtn) (Figure 2(a)). The NMOS transistor M1
is turned off and subsequently M2 is turned on. There is a static current through M3 and M2. The
expression of VOL is derived by applying KCL at node ‘Out’:
ܫெଷሺ௦௧௨௧ሻ = ܫெଶሺሻ (1)
ଵ
ଶ
ሺߤሻሺܥ௫ሻ ቀ
ௐ
ቁ
ெଷ
൫ܸ௧ − ܸ − ܸ௧൯
ଶ
= ሺߤሻሺܥ௫ሻ ቀ
ௐ
ቁ
ெଶ
ሺሺܸ − ܸ௧ሻܸ௨௧ −
ೠ
మ
ଶ
ሻ (2)
where, µn and µp are the mobility of electrons and holes in cm2
/Volt-sec, Cox is oxide capacitance
per unit area, W/L is aspect ratio of transistors, and Vtn and Vtp are threshold voltage of NMOS
and PMOS transistors respectively. On simplification, equation (2) can be written as-
ܣ൫ܸ௧ − ܸ − ܸ௧൯
ଶ
= 2ሺܸ − ܸ௧ሻܸ௨௧ − ܸ௨௧
ଶ
(3)
Where, ܣ =
ఓቀ
ೈ
ಽ
ቁ
ಾయ
ఓ ሺ
ೈ
ಽ
ሻಾమ
On simplifying, we get a quadratic equation (4) in terms of Vout :
ܸ௨௧
ଶ
− 2ܸ௨௧ሺܸ − ܸ௧ሻ + ܣ ൫ܸ௧ − ܸ − ܸ௧൯
ଶ
= 0 (4)
The roots of quadratic equation ax2
+bx+c=0 are given by:
ݔ =
ି± √మିସ
ଶ
(5)
Equating the corresponding coefficients of equation (4) and (5) we get:
ܸ௨௧ = [ܸ − ܸ௧ ± ܵ] Where, S = ටሺܸ − ܸ௧ሻଶ − ܣ ሺܸ௧ − ܸ − ܸ௧ሻଶ
Expression for VOL is given with negative root of above quadratic equation as value of VOL should
be in between 0 to VDD.
ܸ௨௧ = ܸை = ܸ − ܸ௧ − ܵ (6)
VOL is designed to be low by keeping the aspect ratio of NMOS transistors (M1 and M2) higher
than PMOS transistors (M3 and M4). To calculate VOH, the assumption is Vin > Vtn. Consequently
‘M2’ is turned off so that IM2= 0. By applying KCL at node ‘Out’, we get:
ܫெଷ = ܫெଶ = 0
=>
ௐ
ଶ
൛2൫ܸ௧ − ܸ − ܸ௧൯ሺܸ௨௧ − ܸ൯ − ሺܸ௨௧ − ܸሻଶ
} = 0 (7)
The only valid solution of equation (7) is Vout = VOH =VDD. In order to verify the analytical
equations for VOL, technological and operating parameters, as shown in Table (1) are used. Figure
4 (a) shows the comparison of simulated and analytical data for VOL over the control voltage
‘Vctrl’. The maximum deviation is 20 mV. The values of VOL over the entire range of control
voltage are small. Therefore, they can be interfaced with the standard cells in the design of DL
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
41
2.2.2 Propagation Delay equation
The aim is to find the rising edge propagation delay ‘Tpr’ (Figure 2(b)) of the circuit with respect
to control voltage ‘Vctrl’. When Vin is at logic ‘1’, Voutb pulls down to VOL. Consequently, the
NMOS transistor M2 enters in the cut-off region. In the calculation explained below, it is assumed
that M2 enters in cut-off after a constant delay. It is not modeled to avoid the complexity in the
calculation. Assuming negligible current through M2, the current ‘Icp’ through M3 is used to
charge the load capacitance ‘Cload’. The relation between the current ‘Icp’ and delay ‘Tpr’ is given
by equation (8).
ܶ = ܥௗ
ௗೠ
ூሺೠሻ
ವವ/ଶ
ೀಽ
(8)
The channel length ‘L’ of PMOS transistor M3 is designed to be 0.35 µm. The value of VDSAT is
1.7 V in 0.35 µm AMS CMOS process. It is a good approximation to assume velocity saturated
behavior from VOL to VDD/2. The current Icp in velocity saturation operating region is given by
equation (9), where Kp is the gain factor for PMOS transistor and λ is channel length modulation
factor.
ܫ = ܫ௦ௗ = −ܫௗ௦ = −
ଶ
൫ܸ௧ − ܸ − ܸ௧൯ሺ1 + λ ሺV୭୳୲ − Vୈୈሻሻ
=
ଶ
൫ܸ − ܸ௧ + ܸ௧൯ሺ1 + λ ሺV୭୳୲ − Vୈୈሻ (9)
This equation holds for the transition time of ‘Out’ node when it attains the voltage VDD/2.
Substituting this value of current in (8):
ܶ =
ଶ×ೌ
ௗೠ
൫ವವିೝା൯ሺଵାఒ ሺೠିವವሻሻ
ವವ/ଶ
ೀಽ
ܶ =
ଶ×ೌ
×൫ವವିೝା൯
ௗೠ
ሺଵାఒ ሺೠିವವሻሻ
ವವ/ଶ
ೀಽ
ܶ = ܭଵ [lnሺ1 + λ ሺܸ௨௧ − ܸሻ]ೀಽ
ವವ/ଶ
Where, ܭଵ =
ଶ×ೌ
λ൫ವವିೝା൯
ܶ = ܭଵ ݈݊[
൬ଵାఒቀ
ೇವವ
మ
ିವವቁ൰
ሺଵାఒሺೀಽିವವሻሻ
] (10)
Figure 4(b) shows the comparison of simulated and analytical data for delay Tpr over control
voltage. There is sufficient matching in the analytical and simulated data for usable range of
control voltage from 0 V to 2.1 V.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
42
Figure 4. (a) VOL versus Control Voltage (b) Delay versus Control Voltage of MCBL delay
element for simulated and analytical model
Table 1. Parameters and their values
3. DESIGN OF DLL USING THE MCBL DELAY ELEMENT
In this section, the functionality of MCBL delay element has been verified by realizing a DLL.
The block diagram of DLL is shown in Figure 5 (a), where the designed key building blocks are
Voltage Controlled Delay Line (VCDL), bias circuit, Phase Detector (PD), Charge Pump (CP),
loop filter capacitor (16 pF) and start control circuit.
Figure 5. (a) Block diagram of DLL (b) Schematic diagram of start control circuit
µn = 475E-4 m2
/V-Sec µp = 148E-4 m2
/V-Sec
Vtn= 0.5V Vtp = -0.69V
Cox =4.4fF/µm2
VDD = 3.3V
T=270
C=300K Kp= 0.000651.2 F/V-sec
λ = 0.13V-1
Cload = 14 fF
(W/L)M3=(W/L)M4=1µ/0.35µ (W/L)M1=(W/L)M2=1.5 µ/0.35µ
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
43
The VCDL is realised by N cascaded MCBL delay elements. The number N = 33 is calculated
using equation (11), where, Tref = 10 ns is the reference clock period and Td = 150 ps is unit target
delay. The delay elements are loaded with standard cell buffers. To provide the identical load
environment, two dummy delay elements at the beginning and end of VCDL are used.
ܰ =
்ೝ
ଶ×்
(11)
The start control circuit shown in Figure 5(b) is designed to avoid false harmonic locking of DLL.
It sets the initial voltage ‘Vpv’ (preset voltage) of loop filter capacitor before the commencement
of locking process. Initially, the preset switch ‘S’ is on. It sets the voltage across loop filter
capacitor ‘C’ to the voltage ‘Vpv’ = 0.5 V for unit delay of 170 ps. The value of ‘Vpv’ is deduced
from delay characteristic of DE with bias circuit as shown in Figure 7(b).The bias circuit shown
in Figure 6(a) modifies delay versus control voltage characteristic. It improves the range of
control voltage and makes the delay a monotonic function with respect to control voltage.
The operation of DLL starts with the assertion of ‘Start’ signal. It turns off the preset switch ‘S’
and enables the reference clock ‘Ref_Clk’ inside VCDL. The delayed output clock ‘D34’ from
VCDL is applied to PD shown in Figure 6(b), where its rising edge is compared with the rising
edge of reference clock Aref (Figure 5(a)). The PD converts the phase error into equivalent time
duration pulse ‘UP’ and ‘DN’. The output of PD controls the charge pump [12]. If phase error is
positive, the time duration error is given by UP signal, which controls the discharging of filter
capacitor. If phase error is negative, it is given by DN signal, which controls the charging of filter
capacitor. For the applied Vpv, the control voltage ‘Vctrl’ decreases by the correction of loop and
stabilizes at 0.3 V for unit delay of 150 ps as shown in Figure 8(a). After iterations of 20 clock
cycles, the DLL locks the delay of VCDL to half clock period (5 ns) of reference clock.
The advantage of this delay element is that, only one control loop (including PD, charge pump,
filter capacitor, and bias circuit) is required to control both rising and falling edge delays. The
output of VCDL provides delayed replicas ‘D1’ to ‘D34’ of Clk_VCDL with time interval of 150
ps.
Figure 6. Schematic Diagram of (a) Bias Circuit (b) Phase Detector
4. SIMULATION RESULTS
The MCBL delay element is implemented using 0.35 µm CMOS technology. The results
presented in this section are based on post layout simulation by Spectre using device models of
standard CMOS process. The area of unit delay cell is 10×10 µm2
. The static current of single DE
is 140 µA at 0.5 V control voltage. The static current reduces with the increment in control
voltage.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
44
A linear sweep of control voltage in the range of 0 V to 3.3 V with a step size of 0.1 V is applied
to bias circuit. Figure 7(a) shows the bias voltage over the range of control voltage from 0 V to
3.3 V. The bias voltages applied to delay element causes identical variation in rising and falling
edge delays of delay element. Figure 7(b) shows the plot of delay versus control voltage on
typical corner.
The transient response of control voltage on typical corner is shown in Figure 8(a). Figure 8(b)
depicts the consecutive uniformly delayed replicas of clock D1 to D9 generated from VCDL. In
Table 2, the performance of delay element is compared with the other existing architectures in
0.35µm CMOS technology.
Figure 7. (a) Bias voltage (Vbias) with respect to control voltage (b) Delay with respect to control
voltage
Figure 8. (a) Profile of Control Voltage ‘Vctrl’ of DLL (b) Delayed clocks generated from VCDL
Table 2. Performance Comparison
DE
This
Work
[6] [8] [10]
Type MCBL with bias
circuit
Current Starved
INV
Differential Differential
(SCL)
Tmin (ps) 140 244 2500 29.3
Tmax (ps) 680 ---- 16000 ----
Power with
DLL
25 mW @ 100
MHz
14 mW @ 32
MHz
132 mW @130
MHz
675mW @ 3 V
(without DLL)
N 33 128 10 64
Swing Full Full Partial Partial
Process 0.35 µm 0.35 µm 0.35 µm 0.35 µm
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
45
5. CONCLUSION
In this paper, a MCBL delay element and its analysis is presented. The analytical delays
sufficiently match with the simulated ones. This delay element attains small propagation delays
147 ps with large swing and relatively low static current (140 µA @ 0.5 V). It provides identical
rising and falling edge delays, which enables us to control both delays with a single control loop.
This DE can be interfaced with the standard cells as the maximum value of VOL is 0.25 V at 0.1 V
control voltage. This delay element has potential to be incorporated in the mixed signal design
due to MCBL logic.
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[1] S. Eto, H. Akita, et al., (2000), “A 333MHz, 20mW, 18ps resolution digital DLL using current
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