1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Hardware Analysis of Resonant Frequency Converter Using Isolated Circuits And...IJERD Editor
-LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region[5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits.
An Enhanced Flying Capacitor Multilevel Inverter fed Induction Motor DriveIDES Editor
This paper focused on the development of
capacitor voltage balancing methods in a flying capacitor
multilevel inverter (FCMLI) fed induction motor drive.
For improving the performance of flying capacitor
multilevel inverter, a switching pattern selection scheme
is implemented. The proposed method has been designed
a nine -level flying capacitor multilevel inverter by using
sinusoidal pulse width modulation technique. The selected
pattern has been exposed to give superior performance in
load voltage, total harmonics distortion and capacitor
voltage fluctuation. The performance of proposed
strategies is confirmed through simulation investigations.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Hardware Analysis of Resonant Frequency Converter Using Isolated Circuits And...IJERD Editor
-LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region[5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits.
An Enhanced Flying Capacitor Multilevel Inverter fed Induction Motor DriveIDES Editor
This paper focused on the development of
capacitor voltage balancing methods in a flying capacitor
multilevel inverter (FCMLI) fed induction motor drive.
For improving the performance of flying capacitor
multilevel inverter, a switching pattern selection scheme
is implemented. The proposed method has been designed
a nine -level flying capacitor multilevel inverter by using
sinusoidal pulse width modulation technique. The selected
pattern has been exposed to give superior performance in
load voltage, total harmonics distortion and capacitor
voltage fluctuation. The performance of proposed
strategies is confirmed through simulation investigations.
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
DESIGN AND IMPLEMENTATION OF ANALOG MULTIPLIER WITH IMPROVED LINEARITY VLSICS Design
Analog multipliers are used for frequency conversion and are critical components in modern radio frequency (RF) systems. RF systems must process analog signals with a wide dynamic range at high frequencies. A mixer converts RF power at one frequency into power at another frequency to make signal processing easier and also inexpensive. A fundamental reason for frequency conversion is to allow amplification of the received signal at a frequency other than the RF, or the audio, frequency. This paper deals with two such multipliers using MOSFETs which can be used in communication systems. They were designed and implemented using 0.5 micron CMOS process. The two multipliers were characterized for power consumption, linearity, noise and harmonic distortion. The initial circuit simulated is a basic Gilbert cell whose gain is fairly high but shows more power consumption and high total harmonic distortion. Our paper aims in reducing both power consumption and total harmonic distortion. The second multiplier is a new architecture that consumes 43.07 percent less power and shows 22.69 percent less total harmonic distortion when compared to the basic Gilbert cell. The common centroid layouts of both the circuits have also been developed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Novel Voltage Mode Multifunction Filter based on Current Conveyor Transconduc...IDES Editor
This paper presents a novel voltage mode (VM) first
order Single input three output multi function filter employing
second generation current conveyor transconductance
amplifier (CCII-TA). The proposed circuit employs only one
active element, one grounded capacitor and three resistors.
The angular pole frequency of the proposed circuits can be
tuned electronically with the help of bias current. The proposed
circuit is very appropriate to further develop into an integrated
circuit. Sensitivity study is provided and SPICE simulations
have been included which verify the workability of the circuit
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Optimized Hybrid Phase Disposition PWM Control Method for Multilevel InverterIDES Editor
This paper presents a new variation of hybrid
phase disposition pulse width modulation technique suitable
for cascaded multilevel inverter. A hybrid PDPWM is
developed based on low frequency PWM and high
frequency Sinusoidal PWM. An optimized sequential
switching scheme introduced in this proposed method to
equalize electro static and electro magnetic stress among the
power devices. It is confirmed that the proposed technique
offers significantly lower switching losses and switching
transitions. Furthermore, the proposed hybrid PDPWM
offers better harmonic performance compared to its
conventional PWM counterpart. Simulation results are
included in this paper in order to confirm the effectiveness
of the proposed technique.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
DESIGN AND IMPLEMENTATION OF ANALOG MULTIPLIER WITH IMPROVED LINEARITY VLSICS Design
Analog multipliers are used for frequency conversion and are critical components in modern radio frequency (RF) systems. RF systems must process analog signals with a wide dynamic range at high frequencies. A mixer converts RF power at one frequency into power at another frequency to make signal processing easier and also inexpensive. A fundamental reason for frequency conversion is to allow amplification of the received signal at a frequency other than the RF, or the audio, frequency. This paper deals with two such multipliers using MOSFETs which can be used in communication systems. They were designed and implemented using 0.5 micron CMOS process. The two multipliers were characterized for power consumption, linearity, noise and harmonic distortion. The initial circuit simulated is a basic Gilbert cell whose gain is fairly high but shows more power consumption and high total harmonic distortion. Our paper aims in reducing both power consumption and total harmonic distortion. The second multiplier is a new architecture that consumes 43.07 percent less power and shows 22.69 percent less total harmonic distortion when compared to the basic Gilbert cell. The common centroid layouts of both the circuits have also been developed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Novel Voltage Mode Multifunction Filter based on Current Conveyor Transconduc...IDES Editor
This paper presents a novel voltage mode (VM) first
order Single input three output multi function filter employing
second generation current conveyor transconductance
amplifier (CCII-TA). The proposed circuit employs only one
active element, one grounded capacitor and three resistors.
The angular pole frequency of the proposed circuits can be
tuned electronically with the help of bias current. The proposed
circuit is very appropriate to further develop into an integrated
circuit. Sensitivity study is provided and SPICE simulations
have been included which verify the workability of the circuit
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Power quality improvement using impedance network based invertereSAT Journals
Abstract Inverters are suited for applications where DC supply is converted to AC signal with desired waveform & adequate quality of power. Recently proposed Trans Z –source inverters and T –source inverters characterize improved power quality with the help of coupled inductors with turn’s ratio higher than one. This paper presents the concept of LC network based inverter. The built in DC current blocking capacitors connected in series with transformer windings and therefore prevent the transformer core from saturation. The novel LC network based inverter topology proposed in this paper characterize available continuous input current which is the advantage compared to TZSI and TSI. Simulations have been carried out in PSIM platform and results are presented to validate the proposed topology of the inverter system. Index Terms: Power quality, LC network, Impedance source inverter, Boost control, Shoot through state.
Power quality improvement using impedance network based invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
Comparative Evaluation of Three Phase Three Level Neutral Point Clamped Z-So...NAGARAJARAOS
The Z-impedance network coThree-level Z-source inverters are recent single-stage topological solutions
proposed for buck-boost energy conversion with all favorable advantages of
three-level switching retained. Despite their effectiveness in achieving voltage
buck-boost conversion, existing three-level Z-source inverters use two
impedance networks and two isolated dc sources, which can significantly
increase the overall system cost and require a more complex modulator for
balancing the network inductive voltage boosting. Offering a number of less
costly alternatives, this paper presents the design and control of two threelevel Z-source inverters, whose output voltage can be stepped down or up
using only a single impedance network connected between the dc input source
and either a neutral-point-clamped (NPC) or dc-link cascaded inverter
circuitry.
This paper investigates the carrier based modulation schemes (SPWM and
Modified SVPWM) of three-level three phase Z-source inverters with either
two Z-source networks or single Z-source network connected between the dc
sources and inverter circuitry. With the proper offset added for achieving both
optimized harmonic performance and fundamental output voltage, the
proposed modulation schemes of three-level Z-source inverters can satisfy the
expected boost operation under unbalanced modulation conditions. The
Simulation has been performed through Matlab/Simulink and relative
simulation results with conventional method have been presented to validate
the proposed methodnsists of L and C components connected in an X fashion.
The firing control of the Z-source inverter includes the shoot through states. The Zsource inverter advantageously utilizes the shoot-through state to boost the DC bus
voltage by gating on both the upper and lower switches of a phase leg. Three-level
neutral-point-clamped (NPC) inverters, having many inherent advantages, are
commonly used as the preferred topology for medium voltage ac drives [1], and have
recently been explored for other low-voltage applications including grid-interfacing
power converters and high-speed drive converters [2], [3]. Despite their generally
favorable output performance, NPC inverters are constrained by their ability to
perform only voltage-buck operation with buck-boost energy conversion, usually
achieved by connecting various dc-dc boost converters to the front ends of the dc-ac
inverters. These two-stage solutions are usually more costly and can be harder to
control, since they involve more active and passive components. Offering a singlestage solution, [4], [5] propose the buck-boost Z-source NPC inverter, whose
topology is illustrated in Fig. 1 (can be viewed as an extension from the two-level Zsource inverter proposed in [6]).
Design and simulation hybrid filter for 17 level multilevel inverterjournalBEEI
The increasing of renewable energy applications such as solar cells, wind power, ocean thermal and HVDC (high voltage direct current) cause increment in the use of the inverter circuit. Harmonics that are generated by the inverter have negative impacts on the electrical equipment; harmonics cause excessive heat and may shorten the life of electrical equipment. A multilevel inverter is an arranged of cascaded inverters which aims to reduce total harmonic distortion (THD). This paper proposes the design of 17 levels of a single-phase cascaded multilevel inverter with a hybrid filter insertion. By using PSIM simulator, the hybrid filter is proven reducing THD better than single pulse width modulation (SPWM) inverter. Installation of the hybrid filter is able to fix a maximum of 0.23% THDv and a maximum of 1.05% THDi. Hybrid filter installation reduces the value of THD to comply with IEEE 519-2014 standard.
The Performance of an Integrated Transformer in a DC/DC ConverterTELKOMNIKA JOURNAL
The separation between the low-voltage part and high-voltage part of the converter is formed by a
transformer that transfers power while jamming the DC ring. The resonant mode power oscillator is utilized
to allow elevated competence power transfer. The on-chip transformer is probable to have elevated value
inductance, elevated quality factors and elevated coupling coefficient to decrease the loss in the
oscillation. The performance of a transformer is extremely dependent on the structure, topology and other
essential structures that create it compatible with the integrated circuits IC process such as patterned
ground shield (PGS). Different types of transformers are modeled and simulated in MATLAB; the
performances are compared to select the optimum design. The on-chip transformer model is simulated
and the Results of MATLAB simulation are exposed, showing an excellent agreement in radio frequency
RF.
Design Topology of Low Profile Transformer forSlim AdaptorIJRES Journal
This paper presents the implementation of a topologyfor low profile transformer using an LLC
resonant converter. A new structure of the slim-type transformer is proposed, which is composed of copper wire
as the primary winding and printed circuit-board winding on the outer layer as the secondary winding.The
proposed circuit operates at high switching frequency to increase power density. The proposed structure is
suitable for a slim and high-efficiency converter because it has advantages of easy utilization and wide
conductive cross-sectional area. In addition, the voltage-doubler rectifier is applied to the secondary side due to
its simple structure of secondary winding, and a CLC filter is adopted to reduce the output filter size.The
specification are to design input voltage 400v,power 120w with 17ms hold time.
Electronics and Communication Engineering is the Branch of Engineering. Electronics and Communication Engineering field requires an understanding of core areas including Engineering Graphics, Computer Programming,Electronics Devices and Circuits-I, Network Analysis, Signals and Systems, Communication Systems, Electromagnetics Engineering, Digital Signal Processing, Embedded Systems, Microprocessor and Computer Architecture. Ekeeda offers Online Mechanical Engineering Courses for all the Subjects as per the Syllabus. Visit : https://ekeeda.com/streamdetails/stream/Electronics-and-Communication-Engineering
Single-Input Double Output High Efficient Boost Dc–Dc ConverterIJMER
The aim of this project is to develop a high-efficiency single-input multiple-output (SIMO) dc–dc converter. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage dc bus and middle-voltage output terminals. The high-voltage dc bus can take as the main power for a high-voltage dc load or the front terminal of a dc–ac inverter.Moreover, middle-voltage output terminals can supply powers for individual middle-voltage dc loads or for charging auxiliary power sources (e.g., battery modules). In this project, a coupled-inductor based dc–dc converter scheme utilizes only one power switch with the properties of voltage clamping and soft switching, and the corresponding device specifications are adequately designed. As a result, the objectives of high-efficiency power conversion, high step up ratio, and various output voltages with different levels can be obtained
Soft Switched Multi-Output Flyback Converter with Voltage DoublerIJPEDS-IAES
A novel multi-output voltage doubler circuit with resonant switching
technique is proposed in this paper. The resonant topology in the primary
side of the flyback transformer switches the device either at zero voltage or
current thus optimizing the switching devices by mitigating the losses. The
voltage doubler circuit introduced in the load side increases the voltage by
twice the value thereby increasing the load power and density. The proposed
Multi-output Isolated Converter removes the need for mutiple SMPS units
for a particular application. This reduces the size and weight of the
converters considerably leading to a greater payload. This paper aims at
optimizing the proposed converter with some design changes. The results
obtained from the hardware prototype are given in a comprehensive manner
for a 3.5W converter operating at output voltages of 5V and 3.3V at 50 kHz
switching frequency. The converter output is regulated with the PI controller
designed with SG3523 IC. The effects of load and line regulation for ±20%
variations are analyzed in detail.
Soft Switched Multi-Output Flyback Converter with Voltage Doubler
Project
1. Review of a Differential Tunable Active Inductor
LC-tank VCO
Peter Sinko, X139: Advanced Analog Microelectronics, UC Berkeley Extension
Abstract – Discussions of inductor replacement
techniques by Yuan [1] are the basis to present a
wide tuning-range CMOS voltage-controlled
oscillator (VCO) with a differential tunable active
inductor LC-tank as proposed by Lu et al. [2].
Resulting VCO coarse frequency tuning is achieved
by varying the equivalent inductance through a
voltage controlled resistor. Fine tuning is by a
varactor. This topology achieved 143% extended
tuning range and significant size reduction.
I. INTRODUCTION
The recent exponential growth of wireless
communications industries demanded improved
wireless solutions supporting multiple bands and
multiple standards, along with better
performances in power and frequency coverage
while satisfying more compacting trends. The
essential building blocks serving such functions
are the frequency generating devices or voltage-
controlled oscillators (VCO). To address these
requirements, alternative reconfigurable
topologies of VCOs have been explored, some
using separate VCOs covering the separate
required frequency bands. Such strategies
resulted in undesirable increase in cost and size
of devices. Other proposed architectures
employed various switching techniques of
capacitors and inductors that yielded adequate
results, however utilizing spiral capacitors and
inductors that lent themselves to considerable
space on an IC chip and with complex control
mechanisms. The switching has usually been
performed by diodes whose forward current
carried electrical noise affecting VCO
frequencies. To overcome such limiting factors,
the concept of frequency tuning by active
inductors has been introduced. Employing
inductor replacement techniques tunable active
inductors achieved frequency tuning ranges of up
to 120%.
The current paper discusses such inductor
replacement techniques and presents the proposed
circuit topology by Lu et al. that further improves
the performance of the wide tuning-range VCOs
with active inductors. By utilizing a differential
active inductor and a varactor for the LC-tank, the
circuit produces a very wide frequency tuning
range.
II. THE GYRATOR TOPOLOGY
A gyrator is a passive, linear, lossless, two-port
electrical network element proposed in 1948 by
Bernard D.H. Tellegen as a hypothetical fifth
linear element after the resistor, capacitor,
inductor and ideal transformer. Using the circuit
symbol of Fig.1, it is governed by the equations:
Fig.1
An important property of a gyrator is that it
inverts the current-voltage characteristic of an
electrical component or network. A gyrator can
make a capacitive circuit behave inductively, a
series LC circuit behave like a parallel LC circuit
etc. When terminated at one port with a
capacitance, the ideal gyrator produces an
2. inductor at the other port. Therefore the gyrator is
used to emulate devices built from basic
electronic elements and is primarily used in active
filter design and miniaturization.
The basic gyrator topology consists of two back-
to-back connected transconductors. When
one port of the gyrator is connected to a capacitor
as in Fig.2, the network is called a gyrator-C
network [1, p.23]:
Fig.2
Gyrator-C networks are used to synthesize
gyrator-C active inductors. The inductance
of a gyrator-C active inductor is directly
proportional to the load capacitance C and
inversely proportional to the product of the
transconductances of the transconductors of the
gyrator. In Fig.2 the transconductor in the
forward path has a positive transconductance
while the transconductor in the feedback path has
a negative transconductance. Alternately, the
transconductor in the forward path can be
configured as a negative transconductance and the
transconductor in the feedback path as a positive
transconductance by simple exchange of
connections to the positive and negative ports of
both opamps.
Floating gyrator-C active inductor is floating if
both terminals of the inductor are not connected
to either Vdd or Gnd of the circuits containing
them. They are constructed by replacing single
ended transconductors with differentially
configured transconductors as in Fig.3 [1, p.25]:
Fig.3
The advantage of a floating gyrator-C active
inductor over its single-ended counterpart is in its
differential configuration, namely it rejects the
common-mode disturbances present in the
network and is characterised by its Common
Mode Rejection Ratio (CMRR). This will be
considered a desirable feature of a VCO and
indexed as (F1).
Lossy floating gyrator-C active inductors [1, p.28-
31] have finite input and output impedances that
are represented by the additional equivalent
transconductances at either port, and can be
analyzed in a similar way as lossy single-ended
gyrator-C active inductors. Considering the lossy
floating gyrator-C network of Fig.4,
Fig.4
3. with admittance looking into port 2
Go1 and Go2 represent the total conductances at
nodes 1 and 2, respectively. Go1 is a
superposition of the finite output impedance of
transconductor 1 and the finite input impedance
of transconductor 2.
The equivalent RLC network is obtained from the
manipulation of KCL equations at nodes 1 and 2
[1, p.28] combining respective parameters into the
parasitic parallel ohmic resistance Rp, series
ohmic resistance Rs, and parallel capacitance Cp.
The frequency range of a lossy active inductor
can be obtained from the impedance equation of
the RLC equivalent circuit with pole resonant
frequency and zero resonant frequency defining
the resistive, inductive and capacitive nature of a
gyrator's frequency dependent behavior as marked
on the Bode plots of Fig.5. In addition, the
inductive behavior of the gyrator is manifested by
the 90 degree phase lag of the output current
relative to input voltage [1, p.31].
Fig.5
Gyrator-C networks synthesized from transistors
are some of the simplest designs, and the
frequency ranges of gyration depend on the cutoff
frequencies of the transistors. Common-gate,
common-drain, and differential-pair
configurations having positive transconductance
and common-source configuration with negative
transconductance are illustrated in Fig. 6.
CG CD DP CS
Fig. 6
Considering the common-gate transconductor i(o)
= g(m)v(in) an increase in v(in) will lead to an
increase in i(o). Because an increase in v(in) will
lead to a decrease in iD, but i(o) = J − iD then
i(o) will increase accordingly, therefore the
transconductance of the common-gate
transconductor is positive. For the differential-
pair an increase in v(in) will result in an increase
in iD1, but iD2 = J3 − iD1 therefore iD2 will
decrease. For i(o) = J2 − iD2, i(o) will increase.
The differential-pair transconductor thus has a
positive transconductance.
Tunability
It is readily seen from equation L=C/Gm1Gm2 of
Fig.2 that the inductance of gyrator-C active
inductors can be tuned by either changing the load
capacitance C or varying the transconductances
Gm1 and Gm2. Early circuits of gyrators
consisting of transistors such as differential pairs
were terminated in capacitors with much larger
values than the parasitic capacitance of the
transistors, offering good control of simulated
inductances but occupying considerable silicon
space. Modern gyrators eliminate the gyration
(load) capacitance and rely on the intrinsic
4. capacitances of the transistors themselves. These
capacitances do not terminate the output port but
rather exist between internal nodes and result in
simulated inductances that are close to the
inductance of capacitively terminated gyrators.
Additional tunability of VCOs is achieved by
connecting accumulation-mode varactors in
parallel to active inductors (F2). These are MOS
devices creating an electron accumulation layer
under the gate resulting in the desired gate-oxide
capacitance Cgs. The voltages applied to the gate
being small, capacitance tuning is a fine-tuning
mechanism of inductance and is constrained by
the range of the control voltage Vgs.
Conductance tuning of VCOs is achieved by
varying both positive and negative
transconductances Gm1 and Gm2 via the DC
operating points of the transistors. The operating
point ranges being large translate to large
inductance tuning ranges provided the transistors
remain in saturation. Therefore coarse tuning of
inductance is achieved by conductance tuning,
constrained only by the pinch-off condition and
corner frequency of the transistors (F3).
Quality factor
The finite input and output impedances of
transconductors will cause the quality factor of an
active inductor to be finite also. High Q factor
being a specification, Q enhancement techniques
have received special attention. Defined as the
ratio of the net magnetic energy stored in the
inductor to its ohmic loss per oscillation cycle [1,
p.36], quantified for a linear active inductor in
Fig.7(a) and derived for a lossy gyrator-C active
inductor as in Fig.7(b) results in Q=Q1*Q2*Q3:
(a)
(b)
Fig.7
where
By inspection the above expression reveals the
dominance of Q1 at low frequencies and therefore
the dependence of overall Q factor on Rs.
Increasing the quality factor of an active inductor
by minimizing Rs will reduce losses in the RLC
network. According to the definition of Rs in
Fig.4, reducing Go1 is a direct method to reduce
Rs and is most effective in a differential-pair
transconductor since it has positive
transonductance and the output impedance is
given by r(o2) < 1/g(m) of a common-drain
transconductor. Therefore the use of a
differential-pair is preferable to a single common-
drain transistor (F4). Increasing
transconductances Gm1,2 is undesirable by
increasing the DC bias currents or increasing
transistor sizes.
Compensating for loss in the active inductor is
another approach to lower Rs and involves
connecting a negative resistor at the output of the
positive transconductor to cancel out the parasitic
resistances Rs and Rp. Reconsidering the RLC
network previously discussed, replacing the series
RL network with an equivalent parallel RL
network of same terminal impedance yields the
circuit in Fig.8 with parallel resistances combined
into the total parasitic parallel resistance Rtotal =
Rp//ˆRp. Then a negative resistor of resistance
Rcomp = −Rtotal and input capacitance Ccomp
connected in parallel with Cp will cancel out the
parasitic effect of both Rp and Rs. If Rcomp is a
variable resistor then it can be adjusted to the
exact value of Rtotal to achieve a complete
cancellation of Rs (F5) [1,p.43].
5. Fig.8
Linearity
The operation of discussed gyrator-C inductors
assumes all transistors to be biased to saturation
unless otherwise noted. Therefore pinch-off
condition is one of the constraints on voltage
swings across transistors. When v(DS) falls
below this level the transistor(s) will enter the
triode region thereby decreasing their
transconductances non-linearly from g(m) in
saturation to g(ds) in triode region according to
the iDS-vDS relationship. The inductance Leq
will follow this non-linearity as it increases from
L=C/Gm1Gm2 to L=C/Gds1Gds2 (F6).
Noise
Active inductors generate high levels of noise that
is a primary concern in the design of VCOs.
Noise analysis involves the representation of
noise sources in small signal equivalent circuits as
input-referred noise-voltage generators, input-
referred noise-current generators, and the
resulting output noise power.
The represented noise is thermal noise generated
in the channel and by the gate series resistance of
MOS devices. Using conventional noise analysis
techniques the generated noise at the output due
to individual noise sources is calculated and
added up.
III. MOS IMPLEMENTATION
As previously mentioned, gyrator-C active
inductors usually employ common-source,
common-gate, source follower or differential pair
configurations of MOS transistors. Specifically
the parameters of the RLC network equivalent to
the differential-pair of Fig.9 are:
Fig.9
Compensation using negative resistors to cancel
the effects of parasitic resistances Rs and Rp in
the case of differential-pair active inductors is
realized using the differential negative impedance
network of Fig. 10 (F7):
Fig.10
The current source in this differential
configuration can be removed if the biasing
currents are provided by the circuit connected to
the negative resistor. However the resistor will no
longer be adjustable and design rule-of-thumb is
utilized in sizing the transistors based on the
required currents by the active inductor.
IV. A VCO IMPLEMENTATION
Combining features indexed F1-7, Lu et al.
proposed the simple and elegant implementation
of a wide tuning-range CMOS VCO of Fig.11:
6. A differential-pair, differentially configured
gyrator-C active inductor with MOS varactors
connected in parallel, using a differential
negative impedance gain compensation network
with current re-use.
Fig.11
By inspection the VCO is composed of three
blocks: the tunable active inductor, the varactor
and the negative gain stage. The output of the
VCO is taken differentially at Vout+ and Vout-.
Transistors M1 and M2 realize the cross-coupled
pair gyrator topology with M3-4 in common-drain
configuration. M1-4 are biased in saturation
mode. Transistors M5-6 behave as voltage-
controlled resistors whose resistances are
controlled by the gate voltage Vctrl1, therefore
M5-6 will operate in both triode and saturation
mode. By controlling the bias currents for M1-2
they provide the transcondctance control by
biasing M1-2. Therefore the equivalent
inductance of the active inductor is controlled by
Vctrl1 and is the coarse tuning control of the
equivalent inductance. The varactors parallel to
the active inductor are accumulation-mode MOS
devices whose capacitances are controlled by
Vctrl2 for fine tuning of Leq. Transistors M7-8
realize the differential negative impedance
network and provide the gain compensation due
to the lossy inductor network. M7-8 are biased by
being cascoded with the differential pairs M1-4.
The negative feedback of the active inductor and
the biasing of M7-8 is inspected as follows: an
increase in M1 source node voltage v(S1) and a
decrease in v(S2) will result in an increase in
v(G4) and a decrease in v(G3). M3-4 will then
adjust their v(S) accordingly by reducing v(S3)
and increasing v(S4) by approximately the same
amount. Since M7-8 are biased by the active
inductor, their saturated mode is set by the design
rule of sizing the transistors to three times the
value of the required transconductance for the
bias currents supplied by the active inductor.
Buffers M9-10 are used in open drain
configuration as output ports Vout+ and Vout- to
drive the usually 50 Ohm loads of connected
devices.
Circuit analysis and operation
The small signal equivalent circuit of the active
inductor is shown in Fig.12(a). Since M5 and M6
are biased either in triode or saturation, they are
represented by their drain conductances g(ds5)
and g(ds6).
(a)
Fig.12 (b)
7. From the small signal equivalent circuit the
differential input impedance has been derived as
[2, p.3463]:
For the approximation
the small signal circuit of Fig12(a) can be reduced
to Fig.12(b), where
By inspection Leq depends on a directly
controllable parameter g(ds5), therefore an
applied voltage Vcntrl1 becomes the controlling
mechanism of the active inductance.
The Q-factor has been evaluated based on the
definition in Fig.7(a) from the above differential
input impedance Zin to be [2, p.3464]:
Setting the first derivative of Q to zero the
maximum Q factor has been evaluated as
at the maximum frequency
The Q-factor of the active inductor can be
optimized by manipulating transistor parameters
according to this equation.
To start oscillation the design rule for sizing
transistors M7-8 is necessary and sufficient, the
VCO will begin oscillation at the resonant
frequency of the LC tank. The frequency of
oscillation of the VCO is determined by the value
of Leq which depends on g(ds5) of M5. The
drain conductance g(ds5) is a function of the
applied voltage Vcntrl1, which is then used for
controlling the value of the inductance and
subsequently the frequency of oscillation of the
VCO.
Assuming Vctrl1 to be very small as initial
condition, the transistors M5 and M6 will be
biased in triode region. As Vctrl1 increases, M5-
6 will enter saturation and the values of g(ds5)
and g(ds6) will decrease accordingly. Based on
the equation of Leq, the value of equivalent
inductance will increase that will result in a
decrease of the VCO output frequency according
to the pole and zero resonant frequency equations
of Fig.5. Owing to the large range of voltages of
Vctrl1, the output frequency of the VCO will also
have large ranges accordingly, and Vctrl1 is
therefore the coarse tuning mechanism of the
VCO. Fine tuning of the VCO oscillation
frequency is achieved by varactor control voltage
Vctrl2. The resulting capacitance Cgs of the
varactor is small and is greatly affected by
loading parasitic capacitances thus reducing the
operating range of the varactors. It is therefore a
short-range small-change tuning mechanism.
Noise analysis involves the representation of all
noise sources in the small signal equivalent circuit
of the active inductor as shown in Fig.13, where
the contributions from transistors M1-6 are
included as independent noise-currents
[2,p.3465]:
Fig.13
8. Summing up the individual noise-currents results
in the noise contribution from the LC-tank.
Similarly, the cross-coupled pair noise currents
are added together, and the total noise current at
the output becomes a superposition of the two
total noise currents of the form
Examining the resulting equation for excess phase
[2, p.3467] yields insights regarding operation
and design of a VCO: for a wide frequency range
Leq must be minimized. This leads to design
trade-offs since transistors M1-4 are biased at
high transconductances. Transistor pair M1-2
contribute largely to output noise that can be
improved by increasing the channel-length of the
transistors. M7-8 are determined by design rule-
of-thumb, but the bias currents of M1-2 decrease
as oscillation frequency decreases. The lowest
frequency will then be determined by the negative
conductance of the pair M7-8 when it can no
longer compensate for the losses in the LC-tank.
This is another trade-off in designing a VCO with
desired lower cut-off frequency vs. its size.
V. CONCLUSION
The discussion of inductor replacement
techniques by Yuan [1] formed the basis to
present the wide tuning-range CMOS VCO
proposed by Lu et al. [2] utilizing a differential
tunable active inductor. The proposed VCO is a
differential-pair, differentially configured gyrator-
C active inductor with MOS varactors in parallel,
using a differential negative impedance gain
compensation network with current re-use.
Employing a differentially configured MOS
cross-coupled pair as an active inductor, the VCO
oscillation frequency is tuned by varying the
equivalent inductance Leq of the active LC-tank.
Leq is inversely proportional function of the
transconductance g(ds5) of the parallel voltage-
controlled resistor, therefore changing g(ds5)
varies the value of Leq. The transconductance is
a function of the gate voltage of the voltage-
controlled resistor, then g(ds5) is directly
controlled by the applied voltage Vcntrl1, that
results in coarse tuning of frequency of
oscillation of the VCO. The fine tuning is
achieved by a varactor in parallel to the inductor.
A differential negative impedance gain
compensation network offsets the LC-tank
incurred losses. Noise analysis concludes that
the lowest frequency of oscillation is determined
by the negative feedback network's lower limit of
compensation. Experimental results confirm a
143% improvement in tuning range from
500MHz to 3 GHz and a significant reduction in
silicon size due to the absence of physical
inductors.
REFERENCES
[1] F. Yuan, “CMOS Active Inductors and
Transformers, Principle, Implementation, and
Applications,” 2008, XVIII, pp. 21-99, ISBN:
978-0-387-76477-1.
[2] L. H. Lu, H. H. Hsieh, Y. T. Liao, “A Wide
Tuning-Range CMOS VCO With a Differential
Tunable Active Inductor,” in IEEE Transactions
On Microwave Theory And Techniques, Vol. 54,
No. 9, September 2006.
March 18, 2013