Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Due to increasing complexity, space and cost of communication network, the Electric Power Network has been considered a great option for the solution of all problems. Power line communications (PLC) term stands for the technologies for the data communication over the electrical power supply network. Existing power system is not designed for having data transfer. In this paper we have developed a simulation model of power-line for low voltage distribution network in home. Impulse response of the channel is generated in order to characterize the behavior of power line channel for high speed data communication purpose. To represent Multi-branch network mathematically, ABCD matrix parameters are used. Load mismatching is experimented on three parameters multiple loading, multi branch and different cable length and analysis is presented of its effect on impulse response. All the simulation work has been done using MATLAB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Fault detection and diagnosis ingears using wavelet enveloped power spectrum ...eSAT Journals
Abstract In this work, automatic detection and diagnosis of gear condition monitoring technique is presented. The vibration signals in time domain wereobtained from a fault simulator apparatus from a healthy gear and an induced faulty gear. These time domain signals were processed using Laplace and Morlet wavelet based enveloped power spectrum to detect the faults in gears. The vibration signals obtained were filtered to enhance the signal components before the application of wavelet analysis. The time and frequency domain features extracted from Laplace wavelet based wavelet transform are used as input to ANN for gear fault classification. Genetic algorithm was used to optimize the wavelet and ANN classification parameters. The result shows the successful classification of ANN test process. Index Terms:Continuous wavelet transform, Envelope power spectrum, Wavelet, Filtering, ANN.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
AN EFFICIENT APPROACH TO DELAY ESTIMATION MODEL FOR VLSI INTERCONNECTBUKYABALAJI
Abstract: In recent days there is huge demand for high
speed VLSI networks. In order to judge the behavior of
on-chip interconnects the coupling capacitances and
interconnect delays plays a major role. As we switch to
lower technology there is on-chip inductance effect that
leads to interconnect delay. In this paper we try to apply
second order transfer function designed with finite
difference equation and Laplace transform at the source
and load termination ends. Analysis shows that current
mode signaling in VLSI interconnects provides times
better delay performance than voltage mode.
1 ijaems oct-2015-3-design and development of novel matrix converter performanceINFOGAIN PUBLICATION
Matrix converter is a direct AC-AC converter topology that directly converts energy from an AC source to an AC load without the need of a bulky and limited lifetime energy storage element. Due to the significant advantages offered by matrix converter, such as adjustable power factor, capability of regeneration and high quality sinusoidal input/output waveforms. Matrix converter has been one of the AC–AC topologies that hasreceived extensive research attention for being an alternative to replace traditional AC-DC-AC converters in the variable voltage and variable frequency AC drive applications. In the present paper an indirect space vector modulated matrix converter is proposed. The basic idea of an indirect modulation scheme is to separately apply SVM to the rectification and inversion stages, before combining their switching states to produce the final gating signals. The paper encompasses development of a laboratory prototype of 230V, 250VA three phase to three phase DSP controlled matrix converter fed induction motor drive. The observations and real time testings have been carried out to evaluate and improve the stability of system under various typical abnormal input voltage conditions
Due to increasing complexity, space and cost of communication network, the Electric Power Network has been considered a great option for the solution of all problems. Power line communications (PLC) term stands for the technologies for the data communication over the electrical power supply network. Existing power system is not designed for having data transfer. In this paper we have developed a simulation model of power-line for low voltage distribution network in home. Impulse response of the channel is generated in order to characterize the behavior of power line channel for high speed data communication purpose. To represent Multi-branch network mathematically, ABCD matrix parameters are used. Load mismatching is experimented on three parameters multiple loading, multi branch and different cable length and analysis is presented of its effect on impulse response. All the simulation work has been done using MATLAB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Fault detection and diagnosis ingears using wavelet enveloped power spectrum ...eSAT Journals
Abstract In this work, automatic detection and diagnosis of gear condition monitoring technique is presented. The vibration signals in time domain wereobtained from a fault simulator apparatus from a healthy gear and an induced faulty gear. These time domain signals were processed using Laplace and Morlet wavelet based enveloped power spectrum to detect the faults in gears. The vibration signals obtained were filtered to enhance the signal components before the application of wavelet analysis. The time and frequency domain features extracted from Laplace wavelet based wavelet transform are used as input to ANN for gear fault classification. Genetic algorithm was used to optimize the wavelet and ANN classification parameters. The result shows the successful classification of ANN test process. Index Terms:Continuous wavelet transform, Envelope power spectrum, Wavelet, Filtering, ANN.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
AN EFFICIENT APPROACH TO DELAY ESTIMATION MODEL FOR VLSI INTERCONNECTBUKYABALAJI
Abstract: In recent days there is huge demand for high
speed VLSI networks. In order to judge the behavior of
on-chip interconnects the coupling capacitances and
interconnect delays plays a major role. As we switch to
lower technology there is on-chip inductance effect that
leads to interconnect delay. In this paper we try to apply
second order transfer function designed with finite
difference equation and Laplace transform at the source
and load termination ends. Analysis shows that current
mode signaling in VLSI interconnects provides times
better delay performance than voltage mode.
1 ijaems oct-2015-3-design and development of novel matrix converter performanceINFOGAIN PUBLICATION
Matrix converter is a direct AC-AC converter topology that directly converts energy from an AC source to an AC load without the need of a bulky and limited lifetime energy storage element. Due to the significant advantages offered by matrix converter, such as adjustable power factor, capability of regeneration and high quality sinusoidal input/output waveforms. Matrix converter has been one of the AC–AC topologies that hasreceived extensive research attention for being an alternative to replace traditional AC-DC-AC converters in the variable voltage and variable frequency AC drive applications. In the present paper an indirect space vector modulated matrix converter is proposed. The basic idea of an indirect modulation scheme is to separately apply SVM to the rectification and inversion stages, before combining their switching states to produce the final gating signals. The paper encompasses development of a laboratory prototype of 230V, 250VA three phase to three phase DSP controlled matrix converter fed induction motor drive. The observations and real time testings have been carried out to evaluate and improve the stability of system under various typical abnormal input voltage conditions
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
A modified Cuk DC-DC converter for DC microgrid systemsTELKOMNIKA JOURNAL
A new efficient step-updirect current-direct current (DC-DC) power converter that is suitable for DC microgrid systems is proposed in this paper. The proposed step-up DC-DC converter is derived from the conventional Cuk DC-DC power converter. Output voltage analysis that is useful to predict the conduction losses is presented. It is shown that the proposed step-up DC-DC converter is more efficient than the conventional DC-DC boost power converter. Current ripple analysis that is useful to determine the required inductors and capacitors is also presented. Experimental results are included to show the validity of the proposed step-up DC-DC power converter.
EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN...VLSICS Design
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Signal-Energy Based Fault Classification of Unbalanced Network using S-Transf...idescitation
This paper presents a technique for diagnosis of the type of fault and the faulty
phase on overhead transmission line. The proposed method is based on the multiresolution
S-Transform and Parseval’s theorem. S-Transform is used to produce instantaneous
frequency vectors of the voltage signals of the three phases, and then the energies of these
vectors, based on the Parseval’s theorem, are utilized as inputs to a Probabilistic Neural
Network (PNN). The power system network considered in this study is three phase
Transmission line with unbalanced loading simulated in the PowerSim Toolbox of
MATLAB. The fault conditions are simulated by the variation of fault location, fault
resistance, fault inception angle. The training is conducted by programming in MATLAB.
The robustness of the proposed scheme is investigated by synthetically polluting the
simulated voltage signals with White Gaussian Noise. The suggested method has produced
fast and accurate results. Estimation of fault location is intended to be conducted in future.
Index Terms—
This paper presents an analytical comparison between two-level inverter and three-level neutral point diode clamped inverters for electric vehicle traction purposes. The main objective of the research is to declare the main differences in the performance of the two inverter schemes in terms of the switching and conduction losses over an entire domain of the modulation index and the phase angle distribution, steady-state operation, transient operation at a wide range of speed variation, and the total harmonic distortion THD% of the line voltage output waveform. It also declares the analysis of the three-level neutral point diode clamped inverter (NPCI) obstacle and the unbalance of the DC-link capacitor voltages. The introduced scheme presents an Induction Motor (IM) drive for electric vehicle (EV) applications. Considering the dynamic operation of the EV, the speed of the three-phase induction motor is controlled using a scalar V/Hz control for the full range of the IM power factor (PF). A comprehensive MATLAB/Simulink model for the proposed scheme is established.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
State-space averaged modeling and transfer function derivation of DC-DC boost...TELKOMNIKA JOURNAL
This paper presents dynamic analysis of a boost type DC-DC converter for high-brightness LED (HBLED) driving applications. The steady state operation in presence of all system parasitics has been discussed for continuous conduction mode (CCM). The state-space averaging, energy conservation principle and standard linearization are used to derive ac small signal control to inductor current open-loop transfer function of the converter. The derived transfer function can be further used in designing a robust feed-back control network for the system. In the end frequency and transient responses of the derived transfer function are obtained for a given set of component values, hence to provide a useful guide for control design engineers.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Efficient Optimal Sizing And Allocation Of Capacitors In Radial Distribution ...IDES Editor
A distribution system is an interface between the
bulk power system and the consumers. The radial distribution
system is popular among these because of its low cost and
simple design. The voltage instability in the power system is
characterized by a monotonic voltage drop, which is slow at
first and becomes abrupt after some time when the system is
unable to meet the increasing power demand. Therefore to
overcome these problems capacitors are used. The installation
of the shunt capacitors on the radial distribution system is
essential for power flow control, improving system stability,
pf correction, voltage profile management and losses
minimization. But the placement of the capacitors with
appropriate size is always a challenge. Therefore for this
purpose, in this paper along with Differential Evolution (DE)
Algorithm, Dimension Reducing Distribution Load Flow
(DRDLF) is used. This load flow identifies the location of the
capacitors and the Differential Algorithm determines the size
of the capacitors such that the cost of the energy loss and the
capacitor to be minimum. In this problem the installation
cost of the capacitors is also included. The above method is
tested on IEEE 69 bus system and was found to be better
compared to other methods like Genetic Algorithm and PSO
Dynamic Performance of Distance Relayson Series Compensated Transmission Line...Premier Publishers
Series compensation is installed in power system networks to increase power transfer capacity, improve the system stability, reduce system losses, improve voltage regulation and for achieving flexible power flow control. Distance relays are widely used as main or backup protection of transmission lines including series-compensated transmission lines. The performance of conventional distance relays is affected by series capacitors and cause certain protection issues. This paper briefly discusses the problems like voltage inversion, current inversion, overreach and under reach during the fault conditions specific to series compensated lines. The behavior of capacitor protection techniques is discussed with simulations performed using Real Time Digital Simulator (RTDS) simulator for a typical 400 kV system having series compensation. The analysis is based on Transmission Line fault simulations, internal and external to the 400-transmission line where the Fixed Series Compensation (FSC)is installed.
Enabling relay selection in non-orthogonal multiple access networks: direct a...TELKOMNIKA JOURNAL
In this paper, we consider downlink non-orthogonal multiple access (NOMA) in which the relay selection (RS) scheme is enabled for cooperative networks. In particular, we investigate impact of the number of relays on system performance in term of outage probability. The main factors affecting on cooperative NOMA performance are fixed power allocations coefficients and the number of relay. This paper also indicate performance gap of the outage probabilities among two users the context of NOMA. To exhibit the exactness of derived formula, we match related results between simulation and analytical methods. Numerical results confirms that cooperative NOMA networks benefit from increasing the number of relay.
Dynamic model of A DC-DC quasi-Z-source converter (q-ZSC)IJECEIAES
Two quasi-Z-source DC-DC converters (q-ZSCs) with buck-boost converter gain were recently proposed. The converters have advantages of continuous gain curve, higher gain magnitude and buck-boost operation at efficient duty ratio range when compared with existing q-ZSCs. Accurate dynamic models of these converters are needed for global and detailed overview by understanding their operation limits and effects of components sizes. A dynamic model of one of these converters is proposed here by first deriving the gain equation, state equations and state space model. A generalized small signal model was also derived before localizing it to this topology. The transfer functions (TF) were all derived, the poles and zeros analyzed with the boundaries for stable operations presented and discussed. Some of the findings include existence of right-hand plane (RHP) zero in the duty ratio to output capacitor voltage TF. This is common to the Z-source and quasi-Z-source topologies and implies control limitations. Parasitic resistances of the capacitors and inductors affect the nature and positions of the poles and zeros. It was also found and verified that rather than symmetric components, use of carefully selected smaller asymmetric components L1 and C1 produces less parasitic voltage drop, higher output voltage and current under the same conditions, thus better efficiency and performance at reduced cost, size and weight.
Multilevel inverters play a crucial part in the
areas of high and medium voltage applications. Among the three
main multilevel inverters used, the capacitor clamped multilevel
inverter(CCMLI) has advantage with respect to voltage
redundancies. This work proposes a switching pattern to improve
the performance of chosen H-bridge type CCMLI over
conventional CCMLI. The PWM technique used in this work is
Phase Opposition Disposition PWM(PODPWM). The
performance of proposed H-bridge type CCMLI is verified
through MATLAB-Simulink based simulation. It has been
observed that the THD is low in chosen CCMLI compared to
conventional CCMLI.
MATHEMATICAL MODELING OF MAHESHWAR HYDRO-ELECTRIC PLANT AT NARMADA RIVERelelijjournal
Economic hydropower plant generation scheduling is an important feature from the utility point of view,
this scheduling is more important in that case when the plants are at the same river stream & owned by the
different utilities. Various Conventional & Artificial intelligence methods have been used earlier for the
hydro generation scheduling reported through researches and more, all are of them required the
mathematical modeling of each & every hydro power plant.
Theoretical account of problem solving in general and especially methodology to develop the mathematical
models of the hydroelectric power plants has been described in this paper. Reservoir elevation model, tail
race elevation model and hydro turbine model have been developed for Rani Avanti Bai Sagar river bed
hydroelectric power plants by collating actual plant data from competent authorities. Modeling of canal
head hydroelectric power plants have been also included in this paper. This hydro power project is a part
of cascade scheme at Narmada River in Madhya Pradesh, India.
Electro-Mechanical Batteries for low earth orbit satellite with hallow cylind...elelijjournal
Electromechanical batteries overcome many problems that may occur when chemical batteries in low orbit satellites (LEO) , In such a configuration of motor generator mode coupling with flywheel is used to store kinetic energy in motor mode through the flywheel during sunlight and supply electrical power from the stored kinetic energy by generator mode.In this paper design of design of Permanent magnet synchronous machine (PMSM) using hollow cylindrical flywheel for motor generator mode have been done.Flywheel dimensions and material selection are presented in the paper to achieve optimum weight with the required supplied power.
NOVEL PSO STRATEGY FOR TRANSMISSION CONGESTION MANAGEMENTelelijjournal
In post deregulated era of power system load characteristics become more erratic. Unplanned transactions
of electrical power through transmission lines of particular path may occur due to low cost offered by
generating companies. As a consequence those lines driven close to their operating limits and becomes
congested as the lines are originally designed for traditional vertically integrated structure of power
system. This congestion in transmission lines is unpredictable with deterministic load flow strategy.
Rescheduling active and reactive power output of generators is the promising way to manage congestion.
In this paper Particle Swarm Optimization (PSO) with varying inertia weight strategy, with two variants
e1-PSO and e-2 PSO is applied for optimal solution of active and reactive power rescheduling for
managing congestion. The generators sensitivity technique is opted for identifying participating generators
for managing congestion. Proposed algorithm is tested on IEEE 30 bus system. Comparison is made
between results obtained from proposed techniques to that of results reported in previous literature.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
A modified Cuk DC-DC converter for DC microgrid systemsTELKOMNIKA JOURNAL
A new efficient step-updirect current-direct current (DC-DC) power converter that is suitable for DC microgrid systems is proposed in this paper. The proposed step-up DC-DC converter is derived from the conventional Cuk DC-DC power converter. Output voltage analysis that is useful to predict the conduction losses is presented. It is shown that the proposed step-up DC-DC converter is more efficient than the conventional DC-DC boost power converter. Current ripple analysis that is useful to determine the required inductors and capacitors is also presented. Experimental results are included to show the validity of the proposed step-up DC-DC power converter.
EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN...VLSICS Design
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Signal-Energy Based Fault Classification of Unbalanced Network using S-Transf...idescitation
This paper presents a technique for diagnosis of the type of fault and the faulty
phase on overhead transmission line. The proposed method is based on the multiresolution
S-Transform and Parseval’s theorem. S-Transform is used to produce instantaneous
frequency vectors of the voltage signals of the three phases, and then the energies of these
vectors, based on the Parseval’s theorem, are utilized as inputs to a Probabilistic Neural
Network (PNN). The power system network considered in this study is three phase
Transmission line with unbalanced loading simulated in the PowerSim Toolbox of
MATLAB. The fault conditions are simulated by the variation of fault location, fault
resistance, fault inception angle. The training is conducted by programming in MATLAB.
The robustness of the proposed scheme is investigated by synthetically polluting the
simulated voltage signals with White Gaussian Noise. The suggested method has produced
fast and accurate results. Estimation of fault location is intended to be conducted in future.
Index Terms—
This paper presents an analytical comparison between two-level inverter and three-level neutral point diode clamped inverters for electric vehicle traction purposes. The main objective of the research is to declare the main differences in the performance of the two inverter schemes in terms of the switching and conduction losses over an entire domain of the modulation index and the phase angle distribution, steady-state operation, transient operation at a wide range of speed variation, and the total harmonic distortion THD% of the line voltage output waveform. It also declares the analysis of the three-level neutral point diode clamped inverter (NPCI) obstacle and the unbalance of the DC-link capacitor voltages. The introduced scheme presents an Induction Motor (IM) drive for electric vehicle (EV) applications. Considering the dynamic operation of the EV, the speed of the three-phase induction motor is controlled using a scalar V/Hz control for the full range of the IM power factor (PF). A comprehensive MATLAB/Simulink model for the proposed scheme is established.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
State-space averaged modeling and transfer function derivation of DC-DC boost...TELKOMNIKA JOURNAL
This paper presents dynamic analysis of a boost type DC-DC converter for high-brightness LED (HBLED) driving applications. The steady state operation in presence of all system parasitics has been discussed for continuous conduction mode (CCM). The state-space averaging, energy conservation principle and standard linearization are used to derive ac small signal control to inductor current open-loop transfer function of the converter. The derived transfer function can be further used in designing a robust feed-back control network for the system. In the end frequency and transient responses of the derived transfer function are obtained for a given set of component values, hence to provide a useful guide for control design engineers.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Efficient Optimal Sizing And Allocation Of Capacitors In Radial Distribution ...IDES Editor
A distribution system is an interface between the
bulk power system and the consumers. The radial distribution
system is popular among these because of its low cost and
simple design. The voltage instability in the power system is
characterized by a monotonic voltage drop, which is slow at
first and becomes abrupt after some time when the system is
unable to meet the increasing power demand. Therefore to
overcome these problems capacitors are used. The installation
of the shunt capacitors on the radial distribution system is
essential for power flow control, improving system stability,
pf correction, voltage profile management and losses
minimization. But the placement of the capacitors with
appropriate size is always a challenge. Therefore for this
purpose, in this paper along with Differential Evolution (DE)
Algorithm, Dimension Reducing Distribution Load Flow
(DRDLF) is used. This load flow identifies the location of the
capacitors and the Differential Algorithm determines the size
of the capacitors such that the cost of the energy loss and the
capacitor to be minimum. In this problem the installation
cost of the capacitors is also included. The above method is
tested on IEEE 69 bus system and was found to be better
compared to other methods like Genetic Algorithm and PSO
Dynamic Performance of Distance Relayson Series Compensated Transmission Line...Premier Publishers
Series compensation is installed in power system networks to increase power transfer capacity, improve the system stability, reduce system losses, improve voltage regulation and for achieving flexible power flow control. Distance relays are widely used as main or backup protection of transmission lines including series-compensated transmission lines. The performance of conventional distance relays is affected by series capacitors and cause certain protection issues. This paper briefly discusses the problems like voltage inversion, current inversion, overreach and under reach during the fault conditions specific to series compensated lines. The behavior of capacitor protection techniques is discussed with simulations performed using Real Time Digital Simulator (RTDS) simulator for a typical 400 kV system having series compensation. The analysis is based on Transmission Line fault simulations, internal and external to the 400-transmission line where the Fixed Series Compensation (FSC)is installed.
Enabling relay selection in non-orthogonal multiple access networks: direct a...TELKOMNIKA JOURNAL
In this paper, we consider downlink non-orthogonal multiple access (NOMA) in which the relay selection (RS) scheme is enabled for cooperative networks. In particular, we investigate impact of the number of relays on system performance in term of outage probability. The main factors affecting on cooperative NOMA performance are fixed power allocations coefficients and the number of relay. This paper also indicate performance gap of the outage probabilities among two users the context of NOMA. To exhibit the exactness of derived formula, we match related results between simulation and analytical methods. Numerical results confirms that cooperative NOMA networks benefit from increasing the number of relay.
Dynamic model of A DC-DC quasi-Z-source converter (q-ZSC)IJECEIAES
Two quasi-Z-source DC-DC converters (q-ZSCs) with buck-boost converter gain were recently proposed. The converters have advantages of continuous gain curve, higher gain magnitude and buck-boost operation at efficient duty ratio range when compared with existing q-ZSCs. Accurate dynamic models of these converters are needed for global and detailed overview by understanding their operation limits and effects of components sizes. A dynamic model of one of these converters is proposed here by first deriving the gain equation, state equations and state space model. A generalized small signal model was also derived before localizing it to this topology. The transfer functions (TF) were all derived, the poles and zeros analyzed with the boundaries for stable operations presented and discussed. Some of the findings include existence of right-hand plane (RHP) zero in the duty ratio to output capacitor voltage TF. This is common to the Z-source and quasi-Z-source topologies and implies control limitations. Parasitic resistances of the capacitors and inductors affect the nature and positions of the poles and zeros. It was also found and verified that rather than symmetric components, use of carefully selected smaller asymmetric components L1 and C1 produces less parasitic voltage drop, higher output voltage and current under the same conditions, thus better efficiency and performance at reduced cost, size and weight.
Multilevel inverters play a crucial part in the
areas of high and medium voltage applications. Among the three
main multilevel inverters used, the capacitor clamped multilevel
inverter(CCMLI) has advantage with respect to voltage
redundancies. This work proposes a switching pattern to improve
the performance of chosen H-bridge type CCMLI over
conventional CCMLI. The PWM technique used in this work is
Phase Opposition Disposition PWM(PODPWM). The
performance of proposed H-bridge type CCMLI is verified
through MATLAB-Simulink based simulation. It has been
observed that the THD is low in chosen CCMLI compared to
conventional CCMLI.
MATHEMATICAL MODELING OF MAHESHWAR HYDRO-ELECTRIC PLANT AT NARMADA RIVERelelijjournal
Economic hydropower plant generation scheduling is an important feature from the utility point of view,
this scheduling is more important in that case when the plants are at the same river stream & owned by the
different utilities. Various Conventional & Artificial intelligence methods have been used earlier for the
hydro generation scheduling reported through researches and more, all are of them required the
mathematical modeling of each & every hydro power plant.
Theoretical account of problem solving in general and especially methodology to develop the mathematical
models of the hydroelectric power plants has been described in this paper. Reservoir elevation model, tail
race elevation model and hydro turbine model have been developed for Rani Avanti Bai Sagar river bed
hydroelectric power plants by collating actual plant data from competent authorities. Modeling of canal
head hydroelectric power plants have been also included in this paper. This hydro power project is a part
of cascade scheme at Narmada River in Madhya Pradesh, India.
Electro-Mechanical Batteries for low earth orbit satellite with hallow cylind...elelijjournal
Electromechanical batteries overcome many problems that may occur when chemical batteries in low orbit satellites (LEO) , In such a configuration of motor generator mode coupling with flywheel is used to store kinetic energy in motor mode through the flywheel during sunlight and supply electrical power from the stored kinetic energy by generator mode.In this paper design of design of Permanent magnet synchronous machine (PMSM) using hollow cylindrical flywheel for motor generator mode have been done.Flywheel dimensions and material selection are presented in the paper to achieve optimum weight with the required supplied power.
NOVEL PSO STRATEGY FOR TRANSMISSION CONGESTION MANAGEMENTelelijjournal
In post deregulated era of power system load characteristics become more erratic. Unplanned transactions
of electrical power through transmission lines of particular path may occur due to low cost offered by
generating companies. As a consequence those lines driven close to their operating limits and becomes
congested as the lines are originally designed for traditional vertically integrated structure of power
system. This congestion in transmission lines is unpredictable with deterministic load flow strategy.
Rescheduling active and reactive power output of generators is the promising way to manage congestion.
In this paper Particle Swarm Optimization (PSO) with varying inertia weight strategy, with two variants
e1-PSO and e-2 PSO is applied for optimal solution of active and reactive power rescheduling for
managing congestion. The generators sensitivity technique is opted for identifying participating generators
for managing congestion. Proposed algorithm is tested on IEEE 30 bus system. Comparison is made
between results obtained from proposed techniques to that of results reported in previous literature.
Fea of pcb multilayer stack up high voltage planar transformer for aerospace...elelijjournal
High voltage planar transformer is a technology which can replace conventional transformer with its distinct advantages of saturation and cost efficiency. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer
stack up of PCB Cu-tracks, producing High voltage power supply for aerospace application.With finite element analysis (FEA) simulations, different simulation outcomes are discussed for inspecting flux intensity and current density distribution with computing Electric field strength
and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines for
multilayer PCB stack up are discussed in this paper.
Design of matched filter for radar applicationselelijjournal
The aim of this paper is to present the details of signal processing techniques in Military RADARS . These
techniques are strongly based on mathematics and specially on stochastic processes. Detecting a target in
a noisy environment is a many folds sequential process. The signal processing chain only provides to the
overall system boolean indicators stating the presence (or not) of targets inside the coverage area. It is
part of the strategical operation of the radar. This paper mainly focuses on Design of Matched filter and
generation of chirp Signal.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
techTransmission usage and cost allocation using shapley value and tracing me...elelijjournal
In the deregulated power system, transmission pricing has become a very important task because it is necessary to develop an efficient, feasible and reliable pricing scheme that can generate the useful economic signals to network users such as generating companies, transmission companies, distribution companies and customers. The objective of this paper is to compare transmission usage and cost allocation scheme to loads (and/or generators) based on Shapley value method and power flow tracing method.Modified Kirchhoff matrix is used for power flow tracing. A comparison is done between the both methods.
A case study based on sample 6 bus power system is applied to check the feasibility and reliability of the proposed usage and cost allocation methodology.
EFFICIENT MULTIPLIERS FOR 1-OUT-OF-3 BINARY SIGNED-DIGIT NUMBER SYSTEMelelijjournal
This paper proposes new multipliers based on Binary Signed-Digit (BSD) operands. BSD number system has carry free capability in addition operation which causes high speed multiplication. In order to use the numbering system, BSD operand needs to be encoded into binary bits. 1-out-of-3 BSD encoding has been proposed as a subset of m-out-of-n codes which can be used for error detection and correction. However, a multiplier for 1-out-of-3 encoding has not yet been reported in the literature. In this paper, we propose
three different structures for 1-out-of-3 BSD multiplication for the first time to achieve an appropriate trade-off between area, delay, and power parameters. Our target implementation platform is Application Specific Circuits (ASIC).
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Under voltage load shedding for contingency analysis to optimize power loss ...elelijjournal
Power system contingency is a condition of operation which may be caused due to line outage in a system
and could lead to entire system voltage instability. This may further result in voltage collapse leading to total blackout of the system. Therefore, voltage collapse prediction and estimating voltage stability margin
is an important task in power system operation and planning. In this paper Line Stability Index Lij utilizing
the concept of power flow in a single line is adopted to determine the condition of voltage instability. The
purpose of Lij is to determine the point of voltage instability, the weakest bus in the system and the critical
line referred to a bus. Analytical approach based technique for load shedding has been developed as a solution for secured operation of power system under various contingency conditions to optimize the power
flow in order to minimize the system losses within acceptable limit. To validate the effectiveness of the
proposed method simulation has been carried out on IEEE 14 bus system.
OPTIMAL TORQUE RIPPLE CONTROL OF ASYNCHRONOUS DRIVE USING INTELLIGENT CONTROL...elelijjournal
The dynamic performance of an asynchronous machine when operated with cascaded Voltage Source Inverter using Space Vector Modulation (SVM) technique is presented in this paper. A classical model of Induction Motor Drive based on Direct Torque Control (DTC) method is considered which displays
appreciable run-time operation with very simple hysteresis control scheme. Direct control of the torque and flux variables is achieved by choosing suitable inverter voltage space vector from a lookup table. Under varying torque conditions the performance of the drive system is verified using MATLAB/Simulink software tool. The ripple content in the torque parameter is significant when traditional PI controller and Fuzzy approach are configured in the proposed system. Finally, by replacing the PI-Fuzzy controller with Hybrid Controller the torque ripple minimization can be achieved during no-load and loaded conditions.
Design and implementation of pll frequency synthesizer using pe3336 ic for ir...elelijjournal
The design and experimental verification of a low phase noise phase locked loop (PLL) frequency synthesizer using Peregrine’s PE83336 IC is presented. This PLL is used as frequency synthesizer which generates stable and low phase noise signal for space applications. A stable reference frequency of 22.8MHz is provided to the PLL through a temperature compensated crystal oscillator (TCXO). Experimental results of the PLL frequency synthesizer shows the excellent performance achieved at Xband. The PLL model implemented with frequency resolution of 5.8MHz, and phase noise better than -
81dBc/Hz @ 1 kHz offset at X-band. The complete model is fabricated on RT-duroid 6010 substrate
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, this research work introduces an efficient Bus Encoder using Bus Inverting (BI) method. The proposed design dramatically reduces both crosstalk and power dissipation in RLC modeled interconnects which makes it suitable for current high-speed low-power VLSI interconnects. The proposed model demonstrates an overall reduction of power dissipation and crosstalk induced delay by 55.43% and 45.87%, respectively.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
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Modeling of solar array and analyze the current transientEditor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
Modeling of solar array and analyze the current transient response of shunt s...Editor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Self-controllable Voltage Level Technique to reduce leakage current in DRAM 4×4IJERA Editor
As the technology improved to support very large chip sizes, system designers were faced with power
consumption problem and leakage current problem. CMOS technology has increased in level of importance to
the point where it now clearly holds center stage as the dominant VLSI technology The present work shows the
implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL)
technique. SVL technique is leakage current reduction technique. Simulation is done by using a micro wind 3.1
and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.
Self-controllable Voltage Level Technique to reduce leakage current in DRAM 4×4IJERA Editor
As the technology improved to support very large chip sizes, system designers were faced with power
consumption problem and leakage current problem. CMOS technology has increased in level of importance to
the point where it now clearly holds center stage as the dominant VLSI technology The present work shows the
implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL)
technique. SVL technique is leakage current reduction technique. Simulation is done by using a micro wind 3.1
and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
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JMeter webinar - integration with InfluxDB and Grafana
Carbon nano tube based delay model for high speed energy efficient on chip data transmission using current mode technique
1. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
DOI : 10.14810/elelij.2014.3404 31
CARBON NANOTUBE BASED DELAY MODEL FOR
HIGH SPEED ENERGY EFFICIENT ON CHIP DATA
TRANSMISSION USING: CURRENT MODE
TECHNIQUE
Sunil Jadav1
, Munish Vashistah2
, Rajeevan Chandel3
1,2
Electronics Engineering Department, YMCAUST, Faridabad, Haryana India-121006
3
Electronics & Communication Engineering, Department, N.I.T, Hamirpur India- 177005
Abstract: Speed is a major concern for high density VLSI networks. In this paper the closed form delay
model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.
RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.
The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this
model first order transfer function is designed using finite difference equation, and by applying the
boundary conditions at the source and load termination. It has been observed that the dominant pole
determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube
interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The
novel proposed current mode model superiority has been validated for CNT type of material. It superiority
factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ
energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Keywords: Current Mode, Voltage Mode, Equivalent resistance, VLSI Interconnect. CNIA, Nanotubes.
I. INTRODUCTION
Interconnects are one of the essential parts of the VLSI chips. As technology scales down, device
dimensions decreases but at the same time chip dimensions increases in order to embed more and
more devices on the same chip. As a result, global interconnects causes major delays in the
circuits. At deep sub micron technologies these delays are even more than the gate delays and
hence need to be reduced [1]. Various techniques to improves the performance of interconnects
has been proposed [2]. Repeater insertions method has been suggested by many researchers [3, 4].
But there is some practical limitations to the performance improvement [5]. Moreover repeaters
need to be proper sized and should be fixed at proper intervals to achieve optimum results. As an
alternative approach to improve the performance of interconnects, current mode signaling has
been proposed [6, 7, 8, 9,10,11,12 & 13].
A closed- form RC model for current mode interconnects has been derived using first order
moment approximation and boundary condition matching in Ref. [14]. However, as system
requirements push for the use of wider low resistance line, the inductance become increasingly
dominant under fast transitions in GHz frequency range. In this case a RC delay model in [14]
results in an error more than 20% compared to HSPICE simulations when operating in inductance
dominated regions. But this aspect is important for current mode interconnects and therefore has
been attempted in the present research work. An RLC interconnect line needs to be approximated
2. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
32
as a RC line model using inductance-resistance equivalent model. This helps in mitigating the
estimated error in [14, 15, and 16] for GHz frequency range. Due to this the overall system
performance gets improved in terms of speed, throughput, and energy consumption during
transmission of single bit and accuracy at GHz range.
The rest of the paper is organized as follows. In section II inductance equivalent resistance
concept is discussed. In section III the proposed problem is defined with analytical model and
mathematical formulation is presented for resistive load termination and damping factor is
considered for accuracy. Results and their discussion are presented in section IV. Finally
conclusions are drawn in section V.
II. INDUCTANCE-RESISTANCE EQUIVALENT MODEL
The current mode interconnect delay expression is derived through two main steps namely,
(i) Absorbing the line inductance into effective resistance.
(ii) Using transfer function Laplace operator approach and by applying boundary conditions at
source and load end of line.
The line inductance is converted into an effective resistance. In case of RC interconnects, the
equivalent line resistance is “ ܴ௦ + ்ܴ ”. However, when inductive effect is dominant the
equivalent resistance equals “்ܴ + 0.65ܴ௦ + 0.36ܼ” where the factors 0.65 and 0.36 reflect the
shielding effect of inductance [13, 15]. For delay computation the Ist
order transfer function
dominant pole is evaluated, because the dominant pole decides the delay of a distributed network.
Thus the equivalent resistance is given as
ݎ = 0.65ܴ௦ + 0.36ܼ + ்ܴ (1)
Where ܴ௦ is the source resistance and ܼ is the characteristic impedance (ܼ = ඥܮ் ܥ்⁄ ) and RT,
CT and LT represents total line resistance, capacitance and inductance discussed in table 1 for any
length of line.
III. FORMULATION OF BIT LINE DELAY FOR CURRENT MODE
SIGNALING IN LONG INTERCONNECT
All the applications of electronics and electrical system those contains digital integrated IC’s with
memory unit. The speed enhancement of on-chip memories/systems is an important area of
research, which is targeted in this work.
A. Problem Definition
In this work a bit line delay is modeled when a read operation performed on CMOS SRAM.
3. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
33
Fig.1 Equivalent circuit model for the proposed problem (when SRAM drives a bit line)
Current mode signaling technique is exploited for fast access/transfer of information to data line
of any microprocessor/microcontroller. For current mode signaling a system consist of a driver
circuitry, interconnect line and followed by receiver circuitry having a decoding unit. The
problem targeted in this work detailed in figure 1.
B. Mathematical formulation
In this paper, a case of SRAM cell drives the long interconnect lines is approximated in problem
definition section but it is approximated as inverter just for reducing the complexity level. as
shown in figure 2.
Fig.2 Long interconnect lines represented by distributed RLC transmission lines, and driven by an inverter
Fig. 3 Current mode interconnect model
And in the present work distributed RLC model for a current mode interconnects is shown in
figure 3. Line parameters are designated R, L, and C as unit length resistance, inductance and
capacitance respectively, ∆࢞ is the length of each lumped section and RS is the source resistance.
It is very much clear from literature that current mode signaling differs from voltage mode in that
interconnect terminates at a finite resistance in addition to capacitive load. In this work delay
model is proposed for resistive load. As shown in figure 3, the principle of current mode signaling
4. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
34
is that by loading the line with finite impedance, the dominant pole of the system shifts, results in
a smaller time constant and thus less delay.
Long transmission line is modeled as a linear time invariant distributed network. Furthermore, to
represent a constant current and voltage on the line the differential equations representation is
used, where voltage ࢂ(࢞, ࢚) and ࢂ((࢞ + ∆࢞), ࢚) and current ࡵ(࢞, ࢚) and ࡵ((࢞ + ∆࢞), ࢚), are
represented at the source and load ends at ࢞ = and ࢞ = ࢊ (length of line) respectively. Figure
4 shows the equivalent distributed rc interconnect model. Here ࢘ represent unit length equivalent
resistance and ࢉ represent unit length capacitance of the interconnect.
Fig.4 Distributed rc interconnect line model.
For Constant current
ܸ(,ݔ )ݐ − ܸ(ݔ + ∆,ݔ )ݐ
.ݎ ∆ ݔ
= ,ݔ(ܫ )ݐ
For ∆ݔ → 0
,ݔ(ܫ )ݐ = −
ଵ
డ(௫,௧)
డ௫
(2)
For Constant Voltage
,ݔ(ܫ )ݐ − ݔ(ܫ + ∆,ݔ )ݐ = ܿ∆ ݔ
߲ܸ(,ݔ )ݐ
߲ݐ
For ∆ݔ → 0
߲,ݔ(ܫ )ݐ
߲ݔ
= −ܿ
߲ܸ(,ݔ )ݐ
߲ݐ
(3)
Substituting (2) into (3), reduces to
߲ଶ
ܸ(,ݔ )ݐ
߲ݔଶ
= ܿݎ
߲ܸ(,ݔ )ݐ
߲ݐ
Thus
డమ(௫,௧)
డ௫మ − ܿݎ
డ(௫,௧)
డ௧
= 0 (4)
s- domain representation of (4) is
డమ(௫,௦)
డ௫మ − ,ݔ(ܸ ݏܿݎ )ݏ = 0 (5)
5. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
35
Figure 5 gives the rc distributed model of an interconnect line. ܸ()ݐ is the time varying input
signal, and RS is a source resistance with RL resistive load. .ݎ ∆ݔ and ܿ. ∆ݔ represent small
increments in the value of unit length resistance and capacitance down the interconnect line.
Fig. 5 Interconnect line modeled as a distributed line.
The solution of partial differential equation (5) in terms of voltage and current on the line is
given by
ܸ(,ݔ )ݏ = ܣଵଵ݊݅ݏℎ(√)ݔ ݎܿݏ + ܤଵଵܿݏℎ (√)ݔ ݎܿݏ (6)
,ݔ(ܫ )ݏ = −ට
௦
[ܣଵଵܿݏℎ (√)ݔ ݎܿݏ + ܤଵଵ݊݅ݏℎ(√])ݔ ݎܿݏ (7)
Applying the boundary conditions on (6) and (7), ܣଵଵ , ܤଵଵ with RL as resistive load termination
are obtained. And the boundary conditions are:
ܸ()ݏ = ܸ(ݔ = 0, )ݏ + ݔ(ܫ = 0, ܴ)ݏௌ
ܸ(ݔ = ݀, )ݏ = ݔ(ܫ = ݀, ܴ)ݏ
ܣଵଵ = −
ܸ(ݏܿ[)ݏℎ ൫√݀ ݎܿݏ൯ + ට
ܿݏ
ݎ
ܴ ݊݅ݏℎ൫√݀ ݎܿݏ൯]
ቀ
ܴܥݏܴௌ
ݎ + 1ቁ ݊݅ݏℎ൫√݀ ݎܿݏ൯ + ට
ܿݏ
ݎ (ܴ + ܴௌ)ܿݏℎ൫√݀ ݎܿݏ൯
ܤଵଵ =
ܸ(݊݅ݏ[)ݏℎ ൫√݀ ݎܿݏ൯ + ට
ܿݏ
ݎ ܴ ܿݏℎ൫√݀ ݎܿݏ൯]
ቀ
ܴܥݏܴௌ
ݎ + 1ቁ ݊݅ݏℎ൫√݀ ݎܿݏ൯ + ට
ܿݏ
ݎ (ܴ + ܴௌ)ܿݏℎ൫√݀ ݎܿݏ൯
Using the values of A11 and B11 at the load end (6) and (7) reduce to (8).
ܸ(ݔ = ݀, )ݏ
ܸ()ݏ
=
ට
ܿݏ
ݎ ܴ
ቀ
ܴܥݏܴௌ
ݎ
+ 1ቁ ݊݅ݏℎ൫√݀ ݎܿݏ൯ + ට
ܿݏ
ݎ
(ܴ + ܴௌ)ܿݏℎ൫√݀ ݎܿݏ൯
(8)
6. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
36
Let √݀ݎܿݏ = ݑ
This leads to
ܸ(ݔ = ݀, )ݏ
ܸ()ݏ
=
ݑ
݀ݎ
ܴ
൬1 +
ݑଶ
ݎଶ݀ଶ ܴܴௌ൰ ݊݅ݏℎ()ݑ +
ݑ
݀ݎ
(ܴ + ܴௌ)ܿݏℎ()ݑ
ܸ(ݔ = ݀, )ݏ
ܸ()ݏ
=
1
ቀ
݀ݎ
ܴݑ
+
ݑ
݀ݎ
ܴௌቁ (
݁௨ − ݁ି௨
2
) + ቀ1 +
ܴௌ
ܴ
ቁ (
݁௨ + ݁ି௨
2
)
(9)
Rewriting (8) as:
݂()ݑ = ቀ
ܽ
ݑ
+ ܾݑቁ ቆ
݁௨
− ݁ି௨
2
ቇ + ܿ ቆ
݁௨
+ ݁ି௨
2
ቇ
(10)
where, ܽ =
ௗ
ோಽ
=
ோభ
ோಽ
, ܾ =
ோೄ
ௗ
=
ோೄ
ோభ
, ܿ = (1 +
ோೄ
ோಽ
)
On simplifying equation (10), it gives:
݂()ݑ = 1/2[݁௨
ቀ
ܽ
ݑ
+ ܾݑ + ܿቁ + (ܿ − ܾݑ −
ܽ
ݑ
)݁ି௨
(11)
By solving (11), ݂( )ݑ finally reduces to
݂()ݑ = (ܽ + ܿ) + ቀܾ +
ଶ!
+
ଷ!
ቁ ݑଶ
+ ቀ
ଷ!
+
ସ!
+
ହ!
ቁ ݑସ
+ ቀ
ହ!
+
!
+
!
ቁ ݑ
+ ……..
(12)
Substituting the value of
ݑ = √݀ ݎܿݏ
ܿ݀ = ܥଵ, Total capacitance of interconnect line of length‘d’.
݀ݎ = ܴଵ, Total effective resistance of interconnect line of length‘d’, and (12) becomes:
݂()ݑ = (ܽ + ܿ) + ቀܾ +
ଶ!
+
ଷ!
ቁ ܥଵܴଵݏ + ቀ
ଷ!
+
ସ!
+
ହ!
ቁ (ܥଵܴଵ)ଶ
ݏଶ
+ ቀ
ହ!
+
!
+
!
ቁ (ܥଵܴଵ)ଷ
ݏଷ
+
⋯ … … …. (13)
Thereby the distributed network is further approximated to a first order transfer function as shown
below where ܽଵ is the dominant pole that determines the delay of the line.
ܸ(ݔ = ݀, )ݏ
ܸ()ݏ
=
1
(ܽ + ܿ) + ቀܾ +
ܿ
2! +
ܽ
3!ቁ ܥଵܴଵݏ
(14)
First order transfer function is equivalent to
ܸ(ݔ = ݀, )ݏ
ܸ()ݏ
=
ܭଵ
ݏ + ܽଵ
=
ܸௗௗ
ݏ
൬
ܭଵ
ݏ + ܽଵ
൰
(15)
7. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
37
Finally, system response is converted into time domain and gives:
ܸ(ݔ = ݀, )ݐ =
ܸௗௗ
ܽ + ܿ
[1 − ݁ିభ௧] )ݐ(ݑ
(16)
Hence the delay time is computed as:
߬ௗ =
1
ܽଵ
=
ቀܾ +
ܿ
2! +
ܽ
3!ቁ
ܽ + ܿ
ܥଵܴଵ
(17)
Substituting the values of value of a, b, and c, (17) reduces to:
߬ௗ =
[
ܴௌ
ܴଵ
+
1
2 ቀ1 +
ܴௌ
ܴ
ቁ +
1
6
ܴଵ
ܴ
]ܥଵܴଵ
[
ܴଵ
ܴ
+ ቀ1 +
ܴௌ
ܴ
ቁ]
(18)
The delay of the proposed system will be equal to (18) in which RS, R1, C1and RL represents a
source resistance, total line effective resistance, total line capacitance and Load resistance
respectively. Further this model is validated analytically & by performing simulations for
different length of interconnect with carbon nanotube (CNT) type of materials as interconnect and
results are calculated for various interconnect hierarchy and comparison with existing model is
also presented.
C. Damping Factor
For current mode signalling, a lumped system model can be used for the approximate evaluation
of the line inductance effect .This analysis of an RLC transmission line is compared to the
analysis of a lumped RLC circuit [20].
The interconnect is modelled as a single section RLC circuit with RT= R.d, LT= L.d, CT= C.d as
shown in figure 6.
Fig. 6 Simple lumped RLC circuit model of an
Interconnect line.
The poles of the circuit are
ܲଵ,ଶ = ߱[−ߦ ± ඥ(ߦଶ − 1)]
(19)
and the damping factor ߦ is
8. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
38
ߦ =
ܴ. ݀
2
ඨ
ܥ
ܮ
(20)
As (20) implies, if ߦ is greater than one, the poles are real and the effect of the inductance on the
circuit is small. The greater the value of ߦ, the more accurate the rc model become.
On the other hand, as ߦ become less than one, the poles become complex and oscillation occur. In
that case, the inductance cannot be neglected. This relationship is physically intuitive, since ߦ
represents the degree of attenuation the wave suffers as it propagates a distance equal to the
length of the line. As this attenuation increase, the effect of the reflections decrease and the rc
model becomes more accurate. Therefore ߦ is useful figure of merit that anticipates the
importance of considering in a particular interconnect line.
IV. RESULTS AND DISCUSSION
As the process technology downscales, smaller devices and wires come into picture. Also now the
performance and reliability issues matter more. The downscaling of technology makes the devices
faster but the wires get slow. The downscaling of wires increases their resistivity due to surface
roughness, grain boundary scattering and further, due to higher current densities, electromigration
problem becomes a headache. The wires’ parameters have to be taken account of to analyze the
performance of the chip. So the circuit parameters i.e. resistance, capacitance and inductance are
necessarily to be analyzed before introducing any new material as interconnect in the VLSI chips.
Carbon Nanotube Interconnect Analyzer (CNIA) [21, 22 & 23] has been used as the simulating
tool for CNT bundle interconnect. CNIA simulator has four windows for varying inputs named as
Geometry, Process, CNT and ambient. The interconnect dimensions that have been considered in
proportion to that provided by the PTM are given in table 1 at 45nm.
Table 1Simulation Parameters- Interconnect dimensions
Parameters
Technology node Width Thickness Spacing
Height Dielectric
const
45nm Local 68nm 136nm 68nm 136nm 2.1
Intermediate 95nm 240nm 95nm 136nm 2.1
Global 310nm 820nm 310nm 136nm 2.1
The various values of resistance, capacitance and inductance derived using the CNIA simulation
tools have been used and the results derived are detailed in table 2. Their implications are also
given. And table 2 presents the simulation and analytical results delay analysis of current mode
interconnects. Firstly, measurements for the delay have been done at 45nm technology node. The
gamma type network of transmission lines is used as an equivalent circuit to represent the
interconnects in the T-Spice tool of Tanner EDA Inc [19]. With increase in the length of
interconnect the total resistance of the line increases & magnitude of line delay increases. In table
2 the present work at CNT type of material provides a significant reduction in line delay, when
compared to [15] for local, intermediate & global interconnect average reduction factor is 30%,
23% and 23% respectively, whereas when present work is tested at aluminium (Al) & Copper
(Cu) material results are found to be close agreement to each other. These results are estimated
when no condition of deep submicron regime is applied on the interconnects. It means that gate
delay is greater than line delay and during calculation of (18) no assumption has been taken.
Further it is also verified by simulation results shown in table 3. There is always probability of
9. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
39
increase in error when data is transmitted over long length interconnects. Whereas same error
becomes 0.68% for global length of interconnect. Consequently, it is justified that the proposed
model is applicable for global length interconnects. The average error between the analytical and
simulated results remains 2.2% for local, intermediate and global length of interconnect. So it is
better at global length of interconnect. Figure.7 shows the variation of delay with interconnects
length. It is seen that delay increases with length of interconnect. This is in accordance with the
analytical model given by (18).
Fig. 7 Variation of delay with interconnects length for current mode
A very good agreement is seen between the analytical and SPICE simulation results. From figure
7 it is seen that delay obtained is lesser in case of proposed RLC interconnect when it is compared
to [15]. This improvement in delay factor is because of moment approximation method is used in
[15] while the proposed model overcomes the approximation.
Further the inductive effect is more prominent at lower technology node is presented. The delay
contribution due to self- inductance could be significant in this case needs to be considered. A
line 10mm long has an inductance of about 19.37nH, at 180nm node when combined with a line
resistance of 220Ω, and a source resistance of 2.5kΩ, the short circuit time constant is about 7ps.
Therefore the delay due to the line inductance will be negligible. This is finally limited by the
wave propagation delay, which is in the order of 102ps for 10mm long line when calculated for
180nm node. The rise of delay due to inductance is because inductance does not allow sudden
change of current on line. The delay introduced by inductance (table 4) when analyzed at 45nm
technology node the results are completely different. The inductance effect in case of CNT
materials cannot be neglected because inductance is dominating i.e 129.129nH for 10mm long
line. So, the line propagation delay is equal to line inductance delay. Throughput comparison of
proposed models is shown in figure. 8. It is decreasing with the length of interconnect. From this
throughput can be predicted for different length of interconnects.
0
0.05
0.1
0.15
0.2
-200 200 600 1000 1400 1800 2200 2600 3000
Delay(ns)
Interconnect length (um)
[15]
Proposed Analyical Model
Simulation Model
10. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
40
Fig. 8 Throughput variation with the length of interconnects for CNT material.
This all become possible due to change in signalling technique Throughput energy product can be
taken as figure of merit for current mode technique shown in figure 8. And energy dissipated in
transmission of a single bit across the interconnect is
ܧ௧ =
ଵ
ଶ
(ܥ௧)ܸௗௗ
ଶ
(21)
Where Ebit represent energy per bit, Vdd is the supply voltage, ܥ௧ is the equivalent capacitance
of the interconnect. The worst case power dissipated per line is the product of the throughput and
bit energy for a periodic pulse train. From figure 8 it is concluded that throughput energy product
of proposed is reduced to 66.71% when compared to voltage mode of interconnect & a
comparison between voltage mode and current mode is presented in table 4 with the condition of
DSM means line delay is greater than gate delay. After assumption the equation in (18) will
reduce to ߬ெ =
ோభభ
ଶ
for voltage mode (VM) and for current mode (CM) it will reduce to
߬ெ =
ோభభ
. It means that CM dissipates 0.015pJ energy where as VM consume 0.045pJ for a
single bit transmission across the interconnect over CNT material. So, the current mode
interconnect system is an energy efficient data transmission system. First important aspect of this
modelling is that when bit line is terminated by short circuit at load end. Then it is found that
current mode signalling is superior to voltage mode signalling with the condition of DSM on
interconnects. The superiority factor of current mode is 66.66% over voltage mode interconnects
shown in table 4 and graphically presented in figure 9 at the end.
0
1000
2000
3000
4000
5000
6000
7000
8000
0 100 200 300 400 500 600 700 800 900 1000
Throughput(Gbps)
Interconnect length
[15] Proposed model
11. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
41
Second important aspect of short circuit is that it will reduce the dynamic power consumption on
the line because of reduced voltage swing on interconnecting line. And reduced swing on the line
can be estimated using the step response analysis [17]. Third important aspect which we
concluded that due to short circuit the bit line delay is found to be independent of bit line
capacitance by simulation it is investigated as shown in figure 10. For a metal line of 2mm, 4mm,
6mm, 8mm and 10mm long, the value of RT, CT, is calculated using PTM [18] and for different
values bit line load capacitance i.e. 10fF, 20fF, 40fF, 60fF, 80fF the line delay is found to be
independent of bit line load capacitance. The simulation results shown in figure 10 confirm that
line delay is insensitive for extremely small value of load capacitance whereas it increases for
larger value of bit line load capacitance. Keeping in view the advantages shown by current mode
signaling once line is short circuited at termination end. And line delay variation with the load
resistance is shown in figure 11. It increases with the value of load resistance.
So in order to implement the proposed current mode technique, current transporting circuits are
needed with a low input resistance. Current gain is not needed at this stage, a unity gain transfer is
sufficient. Further circuitry can take care of any required amplification or conversion to voltage
mode. The circuit function can be identified as the current conveyor. This has been defined as
device having virtual short circuit input port, and a unity gain transfer characteristic from input to
output. Further possible current conveyor circuit is shown which can be used at termination end
shown below.
The circuit in figure 12 (a) [24] is based on unity current gain positive feedback. It keeps the input
terminal at Vref by matching the currents in the p-channel transistors. The output current is equal
12. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
42
to, or a multiple of, the input current, depending on the relative n-channel transistors sizes. The
circuit in figure 12(b) [24] and (c) [25] are based on negative feedback. For the circuit in figure
12 (b) the current transfers is limited to unity, while for the circuit in figure 12 (c) current gain is
possible. But these circuit options seem feasible for single interconnect lines. However, they have
the drawback of complexity when applied in SRAM data path. Since two bit lines are involved,
two current conveyers would be required, resulting in a relatively complex solution. A simpler
approach, providing two virtually short-circuited current inputs, two current outputs, and
requiring only four equal-sized transistors is indicated in figure 12(d). So this is a better solution
for problem defined in figure 1 for SRAM cells. Thus it is analyzed that current mode signaling is
superior to voltage mode signalling in various aspects.
V. CONCLUSIONS
In the upcoming technology nodes, looking into the need for performance effective integrated
circuits, CNT is a good option to replace Cu as an interconnect material.
In this paper a novel analytical delay model for current mode signaling is developed and
presented. By using this proposed model dominant pole is computed from the first order system
function. It is analyzed for different current mode circuit parameters to determine the nature of
current mode circuits. It is also observed that the proposed model for CNT type of material,
global and intermediate length of interconnects provides average reduction 23% whereas at Al
and Cu results are in close agreement with existing model. Further with the length of interconnect
the simulation results deviates the analytical model at global length of interconnect by 0.68%. So
it is better to use CNT material at global length of interconnects. When the proposed model
results evaluated at 45nm node, it is found that CNT provides 81.78% reduction in delay and
w.r.t. to Al it is further reduced upto 86.80%. In DSM mode the superiority factor between
current versus voltage remains 66.66%, once load is shorted at termination end. Throughput, Bit
line delay and energy consumed during bit transmission is also discussed and presented. By
simulative investigation, it is found that bit line delay is insensitive to extremely small value of
load capacitance. Various topologies for sensing the signal at receiver termination is also
discussed. And finally, it is concluded that the use of current mode techniques can lead to
significant speed enhancement in long VLSI interconnects. This proposed current mode technique
can significantly impact chip access times and architecture trade-offs for future fast CMOS
SRAM design. Current mode signal receivers can be used to significantly reduce the line delays
in CMOS VLSI chips. Secondly, figure of merit have been developed that determine the relative
accuracy of a rc model on-chip interconnects. The derived expression along with accuracy
analysis can serve as a convenient tool for delay estimation with minimal computation during
design.
Acknowledgement
The authors acknowledge with gratitude the technical and financial support from YMCA
University of Science & technology, Faridabad, Haryana, India, for providing EDA tool facilities
in Electronics Circuit Design and simulation Lab and National Council Of YMCAs of India, Govt
of Haryana, India and the Central Agencies for Development Aid, Bonn, Germany for technical
support.
13. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
43
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[17] MATLAB version R2009a Online, http://mathwork.com, 2013.
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14. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
44
Table 2 Comparison between present and existing work at 45nm. (without DSM condition)
Table 3 Material based comparison at 45nm.
15. Electrical and Electronics Engineering: An
Table 4 Comparison between voltage and current mode interconnect delay using CNT material at 45nm in
DSM when
Fig. 9 Comparison between voltage and current mode interconnect using CNT material
Authors
Sunil Jadav received the B.Tech. degree in Electronics & Communication
Engineering from the Guru Jambheshwar University of Science & Technology,
Hissar Haryana, India, in 2007 and the M.Tech degree in VLSI Design &
Automation from National Institute of Technology, Hamirpur, Himachal Pradesh,
India in 2010. In 2011, he joined YMCA University of Science & Technology,
Faridabad, Haryana, India (State University), as an Assistant Professor in Electronics
Engineering Department. Currently he is also pursuing Ph.D. degree in Electronics
Engineering Department of YMCA University of Science & Technology Faridabad.
Before joining YMCAUST, he also worked as Assistant Professor in Electronics & Communication
Engineering Department of National Institute of Technology, Hamirpur. During his work in N.I.T
Hamirpur, he has effectively utilized and worked on various VLSI CAD Tools/Semiconductor Process and
0
20
40
60
80
100
120
140
160
0 2000
Delay(ps)
Current Mode
Voltage Mode
Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
Table 4 Comparison between voltage and current mode interconnect delay using CNT material at 45nm in
DSM when ߬௧ ߬௧ then ܴ௧ ܴௌ or ܴଵ ܴௌ.
Fig. 9 Comparison between voltage and current mode interconnect using CNT material
Jadav received the B.Tech. degree in Electronics & Communication
Engineering from the Guru Jambheshwar University of Science & Technology,
Hissar Haryana, India, in 2007 and the M.Tech degree in VLSI Design &
Automation from National Institute of Technology, Hamirpur, Himachal Pradesh,
India in 2010. In 2011, he joined YMCA University of Science & Technology,
Faridabad, Haryana, India (State University), as an Assistant Professor in Electronics
partment. Currently he is also pursuing Ph.D. degree in Electronics
Engineering Department of YMCA University of Science & Technology Faridabad.
Before joining YMCAUST, he also worked as Assistant Professor in Electronics & Communication
ment of National Institute of Technology, Hamirpur. During his work in N.I.T
Hamirpur, he has effectively utilized and worked on various VLSI CAD Tools/Semiconductor Process and
4000 6000 8000
Interconnect Length (um)
Current Mode
Voltage Mode
International Journal (ELELIJ) Vol 3, No 4, November 2014
45
Table 4 Comparison between voltage and current mode interconnect delay using CNT material at 45nm in
Fig. 9 Comparison between voltage and current mode interconnect using CNT material
Before joining YMCAUST, he also worked as Assistant Professor in Electronics & Communication
ment of National Institute of Technology, Hamirpur. During his work in N.I.T
Hamirpur, he has effectively utilized and worked on various VLSI CAD Tools/Semiconductor Process and
10000
16. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 4, November 2014
46
on field programmable gate array architecture development and low-power circuit design. He has
published more than 20 papers in refereed journals and Conferences. His research interests include analog
IC design/CAD with particular emphasis in low-power electronics for portable computing and wireless
communications, and High Speed Low power VLSI Interconnect.
Dr. Munish Vashishath received his B.Tech in Electronics and Telecommunication
Engineering from North Maharashtra University, Jalgaon in the year 1997, M.E in
Electronics and Control Engineering with Hons. from Birla Institute of Technology and
Science, Pilani in 2000 and Ph.D (Semiconductor Devices) from Thapar University,
Patiala in the year 2010. From Dec 2007, he is serving as Associate Professor in
Electronics Engg. at YMCA University of Science & Technology, Faridabad. His
research interest includes Microelectronics, Semiconductor Devices Modeling &
Simulation and VLSI Technology. Before 2007, he served many reputed institutes like Thapar University,
NIT, Kurukshetra and NIT, Hamirpur. He has also published 40 papers in reputed Journals and
Conferences.
Dr.(Mrs.) Rajeevan Chandel has done pre engineering (Gold Medalist ) in 1986
from D.A.V College Kangra, H.P university and after that she has received her
B.Tech in Electronics and Communication Engineering from Thapar Institute of
Engineering & Technology, Patiala in the year 1990, M.Tech in Integrated
Electronics Engineering from Indian Institute of Technology, Delhi, India in 1997
and Ph.D (VLSI Design, Microelectronics) from Indian Institute of Technology,
Roorkee, Utrakhand, India in the year 2005. From Dec 1997, she is serving as
Professor & Head in Electronics & Communication Engg. at N.I.T Hamirpur Himachal Pradesh, India. Her
research interest includes Microelectronics, Semiconductor Devices Modeling & Simulation and Low-
Power VLSI Circuit and Interconnect Design. She has also published more than 140 papers in reputed
Journals and Conferences.