The document discusses the implementation and comparative analysis of 2x1 multiplexers using different dynamic logic techniques. It describes schematics and output waveforms for 2x1 multiplexers designed using conventional CMOS logic, pseudo NMOS logic, C2MOS logic, domino logic, and low power feed through (LPFT) logic. Power consumption and delay are analyzed for each design using Mentor Graphics simulation tools at 130nm technology.
IRJET - Low Power Design for Fast Full AdderIRJET Journal
This document describes the design of a low power, high speed full adder circuit using 45nm CMOS technology. It discusses how reducing the size of transistors from 65nm to 45nm allows for lower power consumption and higher processing speeds. A new hybrid full adder circuit is proposed that uses simultaneous XOR/XNOR gates and transmission gates to minimize delay and reduce dynamic and static power dissipation. Simulation results show the proposed 20T, 17T, 26T and 22T full adder circuits have higher speeds and lower power consumption than previous designs.
IRJET- An Analysis of CMOS based Low Power 2:4 Decoder at 32nm Node using LEC...IRJET Journal
This document summarizes a research paper that analyzes a CMOS-based 2:4 decoder circuit implemented at a 32nm technology node using the LECTOR (Leakage Control TransistOR) technique to reduce leakage power. The LECTOR technique introduces additional transistors between the pull-up and pull-down networks of CMOS gates to increase resistance and reduce leakage current when the circuit is idle. Simulation results show the LECTOR-based 2:4 decoder reduces leakage power by 65.23% and leakage current by 65.23% compared to a conventional CMOS implementation, with a 145.81% increase in propagation delay. The LECTOR technique effectively reduces static power consumption without impacting dynamic power.
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...IRJET Journal
The document discusses techniques for designing low-power multipliers and fast adders. It introduces the Gate Diffusion Input (GDI) and Modified Gate Diffusion Input (MGDI) techniques, which can reduce transistor count and power consumption compared to traditional CMOS designs. Basic logic gates like AND, OR, XOR can be implemented using GDI cells. Using GDI gates, low-power multipliers and fast adders can be designed, like a 6-transistor GDI full adder. MGDI further improves upon GDI by permanently tying the substrate terminals, reducing static power dissipation. Array and tree multipliers are discussed as approaches to multiply two binary numbers using additions of partial products.
This document discusses the design and implementation of a universal set of integrated circuit gates for multiple valued logic (MVL) circuits using CMOS 180nm technology. MVL circuits can reduce the number of interconnections needed compared to binary circuits. The document proposes a universal set of five CMOS gates - Maximum, Successor, and three extended AND operators - that can be used to synthesize any quaternary (base-4) MVL circuit. It describes implementing the gates in voltage mode by comparing input voltages to threshold voltages to discriminate the four logic levels, and using control switches to set the output levels. The goal is to prove the feasibility of these MVL gates for synthesizing combinational and sequential circuits using the proposed M
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The document describes the design and analysis of 64-bit adders using different logic families in Cadence. Specifically, it discusses:
1. Implementing 1-bit full adder circuits using CMOS, Pseudo-NMOS, and Transmission Gate logic and cascading them to create 64-bit adders of each family.
2. Simulating and analyzing the power consumption of the 64-bit adders, measuring their total power, peak power, and power-delay product.
3. Finding that CMOS and Pseudo-NMOS have identical power characteristics while Transmission Gate has the highest peak power but lowest transistor count and power-delay product.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
Design and implementation of 15 4 compressor using 1-bit semi domino full add...eSAT Journals
Abstract In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre. Keywords: Semi Domino Logic, Full adder, 5-3 compressor, power, delay, PDP, TSMC 28nm.
IRJET - Low Power Design for Fast Full AdderIRJET Journal
This document describes the design of a low power, high speed full adder circuit using 45nm CMOS technology. It discusses how reducing the size of transistors from 65nm to 45nm allows for lower power consumption and higher processing speeds. A new hybrid full adder circuit is proposed that uses simultaneous XOR/XNOR gates and transmission gates to minimize delay and reduce dynamic and static power dissipation. Simulation results show the proposed 20T, 17T, 26T and 22T full adder circuits have higher speeds and lower power consumption than previous designs.
IRJET- An Analysis of CMOS based Low Power 2:4 Decoder at 32nm Node using LEC...IRJET Journal
This document summarizes a research paper that analyzes a CMOS-based 2:4 decoder circuit implemented at a 32nm technology node using the LECTOR (Leakage Control TransistOR) technique to reduce leakage power. The LECTOR technique introduces additional transistors between the pull-up and pull-down networks of CMOS gates to increase resistance and reduce leakage current when the circuit is idle. Simulation results show the LECTOR-based 2:4 decoder reduces leakage power by 65.23% and leakage current by 65.23% compared to a conventional CMOS implementation, with a 145.81% increase in propagation delay. The LECTOR technique effectively reduces static power consumption without impacting dynamic power.
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...IRJET Journal
The document discusses techniques for designing low-power multipliers and fast adders. It introduces the Gate Diffusion Input (GDI) and Modified Gate Diffusion Input (MGDI) techniques, which can reduce transistor count and power consumption compared to traditional CMOS designs. Basic logic gates like AND, OR, XOR can be implemented using GDI cells. Using GDI gates, low-power multipliers and fast adders can be designed, like a 6-transistor GDI full adder. MGDI further improves upon GDI by permanently tying the substrate terminals, reducing static power dissipation. Array and tree multipliers are discussed as approaches to multiply two binary numbers using additions of partial products.
This document discusses the design and implementation of a universal set of integrated circuit gates for multiple valued logic (MVL) circuits using CMOS 180nm technology. MVL circuits can reduce the number of interconnections needed compared to binary circuits. The document proposes a universal set of five CMOS gates - Maximum, Successor, and three extended AND operators - that can be used to synthesize any quaternary (base-4) MVL circuit. It describes implementing the gates in voltage mode by comparing input voltages to threshold voltages to discriminate the four logic levels, and using control switches to set the output levels. The goal is to prove the feasibility of these MVL gates for synthesizing combinational and sequential circuits using the proposed M
Design And Analysis Of 64-Bit Adders In Cadence Using Different Logic FamiliesIRJET Journal
The document describes the design and analysis of 64-bit adders using different logic families in Cadence. Specifically, it discusses:
1. Implementing 1-bit full adder circuits using CMOS, Pseudo-NMOS, and Transmission Gate logic and cascading them to create 64-bit adders of each family.
2. Simulating and analyzing the power consumption of the 64-bit adders, measuring their total power, peak power, and power-delay product.
3. Finding that CMOS and Pseudo-NMOS have identical power characteristics while Transmission Gate has the highest peak power but lowest transistor count and power-delay product.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
Design and implementation of 15 4 compressor using 1-bit semi domino full add...eSAT Journals
Abstract In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre. Keywords: Semi Domino Logic, Full adder, 5-3 compressor, power, delay, PDP, TSMC 28nm.
IRJET- A Novel Design of Hybrid 2 Bit Magnitude ComparatorIRJET Journal
This document proposes and evaluates several novel hybrid circuit designs for a 2-bit magnitude comparator that aim to reduce power consumption. It first describes existing comparator circuit designs using different logic styles and their limitations. It then introduces four new hybrid designs that combine Pass Transistor Logic (PTL) and Gate Diffusion Input (GDI) styles, and incorporates a Self Controllable Voltage Level (SVL) technique to further reduce power. Simulation results show the PTL-GDI 4 design with SVL achieves the greatest power reduction compared to conventional designs, demonstrating over 50% lower power consumption.
Ultra Low Power Design and High Speed Design of Domino Logic CircuitIJERA Editor
The tremendous success of the low-power designs of VLSI circuits over the past 50 years has significant change
in our life style. Integrated circuits are everywhere from computers to automobiles, from cell phones to home
appliances. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or
NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and
extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less
resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which
increases performance compared to existing domino logic styles. According to the simulations in cadence
virtuoso 65nm CMOS process, the proposed circuit shows the improvement of up thirty percent compared
existing domino logics.
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...IRJET Journal
This document describes the design and implementation of a low power 32-bit carry look ahead adder using adiabatic efficient charge recovery logic (ECRL). ECRL is an adiabatic logic that allows for energy recovery, leading to lower power consumption than conventional CMOS logic. The authors designed inverters, AND, OR, and EX-OR gates as well as 4, 8, 16, and 32-bit carry look ahead adders using ECRL in a 45nm technology. Simulation results showed the ECRL implementations consumed less average power than equivalent static CMOS designs. For example, the 32-bit ECRL carry look ahead adder consumed 36.76μw on average
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
IRJET - Analysis of Power Consumption in Glitch Free Dual Edge Triggered ...IRJET Journal
This document analyzes power consumption in a glitch-free dual edge triggered flip-flop circuit design. It discusses existing DET flip-flop designs that use C-element circuits or a combination of C-element and 2P-1N structures. The proposed design aims to reduce area, power consumption, and increase speed. It combines a 1P-2N structure with a C-element circuit to provide a glitch-free output and filter out glitches from prior logic stages, improving system efficiency while consuming less power. The design works accurately at low supply voltages and its operation and ability to avoid glitches are explained.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED VLSICS Design
Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design SystemIOSRJVSP
There is need to develop various new design techniques in order to fulfil the demand of increased speed, reduced area for compactness and reduced power consumption. It is considered that improved other performance specifications such as less delay, high noise immunity and suitable ambient temperature conditions are the prime factors. In this paper two different techniques are used for designing a 4-bit Magnitude Comparator(MC) and then a comparison is made about area and average delay. First one is Transmission Gate (TG) technique and second one is GDI Technique. This paper describes the design of an Integrated Circuit (IC) layout for a 4-bit MC. The layout was designed by use of an open source software namely Electric VLSI Design System which is Electronic Design Automation (EDA) tool. LTspiceXVII is used as simulator to carry out the simulation work.
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...IRJET Journal
This document presents a novel architecture for a high-speed inexact speculative adder using carry lookahead adder and Brent Kung adder. The proposed adder splits the critical path into shorter paths using fine-grain pipelining to improve speed. It uses a carry lookahead adder and Brent Kung adder in 4-bit blocks to speculate the carry and calculate sums, with error compensation. The design is implemented using a 5-stage pipeline to further reduce delay. Implementation in MAGIC shows the proposed adder achieves higher speed through optimized pipelining of key components in the speculative and compensation blocks.
This document proposes a low-power full adder array-based multiplier circuit design using domino logic. It is based on the Wallace tree technique. The proposed circuit uses a clocked architecture that results in lower power dissipation and improved power-delay product compared to traditional designs. As a proof of concept, the authors implemented an 8x8 bit multiplier using multiple 4x4 bit multiplier blocks. Simulation results show the 8x8 multiplier design has an average power of 0.11108 microwatts when implemented using a 0.5um CMOS process at 5V supply voltage.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A high speed dynamic ripple carry addereSAT Journals
Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
TRANSFORMER FAULT DETECTION AND MONITORINGIRJET Journal
This document describes a project to detect and monitor faults in power transformers using sensors and GSM technology. The system measures four parameters - oil level, temperature, open circuit, and short circuit. Sensors detect faults and send SMS alerts to responsible personnel. The aim is to reduce response time for faults to protect transformers and maintain power stability. When faults are detected, the controlling unit can automatically shut down power.
IRJET- Implementation of Combined SVL Technique in Domino Inverter using Micr...IRJET Journal
This document discusses the implementation of a combined self-controllable voltage level (SVL) technique in a domino inverter to reduce power consumption. The combined SVL technique incorporates both upper and lower SVL circuits. The lower SVL circuit increases the back gate bias of transistors, raising their threshold voltage and reducing leakage current. The upper SVL circuit decreases the supply voltage, reducing drain induced barrier lowering and also raising threshold voltage. Simulations using Microwind at 90nm show the combined SVL domino inverter has 27.7% lower power consumption than a standard static CMOS inverter. The combined SVL technique is an effective way to reduce power dissipation in domino logic circuits.
Digital Voltage Control of DC-DC Boost ConverterIJERA Editor
The need for digital control for faster communication between power stage module & system controllers is increased with requirement of load complexity. The requirements also include stability of power module with the parametric variation. This paper presents a digital control of a dc-dc boost converter under nominal parameter conditions. The system controller has been verified in both frequency response as well as MATLAB-Simulink under nominal & parametric varying condition. The modeling of converter has been illustrated using state-space averaging technique. Direct digital design method is equipped to design the controller in frequency response to yield constant load voltage. The characteristic of load voltage before & after parametric variation is shown.
IRJET- Design and Implementation of CMOS and CNT based 2:1 Multiplexer at...IRJET Journal
This document compares the design and performance of a 2:1 multiplexer circuit built using carbon nanotube field-effect transistors (CNTFETs) versus complementary metal–oxide–semiconductor (CMOS) transistors at a 32nm technology node. Simulation results show that the CNTFET-based multiplexer has lower power consumption (6.40nW vs 6.83nW), lower leakage power (319.20pW vs 504.218pW), and similar delay (40.84ns vs 40.86ns) compared to the CMOS-based design. Overall, the CNTFET multiplexer exhibits around a 58% reduction in leakage power over the CMOS design while maintaining comparable operation, demonstrating
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
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Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design SystemIOSRJVSP
There is need to develop various new design techniques in order to fulfil the demand of increased speed, reduced area for compactness and reduced power consumption. It is considered that improved other performance specifications such as less delay, high noise immunity and suitable ambient temperature conditions are the prime factors. In this paper two different techniques are used for designing a 4-bit Magnitude Comparator(MC) and then a comparison is made about area and average delay. First one is Transmission Gate (TG) technique and second one is GDI Technique. This paper describes the design of an Integrated Circuit (IC) layout for a 4-bit MC. The layout was designed by use of an open source software namely Electric VLSI Design System which is Electronic Design Automation (EDA) tool. LTspiceXVII is used as simulator to carry out the simulation work.
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...IRJET Journal
This document presents a novel architecture for a high-speed inexact speculative adder using carry lookahead adder and Brent Kung adder. The proposed adder splits the critical path into shorter paths using fine-grain pipelining to improve speed. It uses a carry lookahead adder and Brent Kung adder in 4-bit blocks to speculate the carry and calculate sums, with error compensation. The design is implemented using a 5-stage pipeline to further reduce delay. Implementation in MAGIC shows the proposed adder achieves higher speed through optimized pipelining of key components in the speculative and compensation blocks.
This document proposes a low-power full adder array-based multiplier circuit design using domino logic. It is based on the Wallace tree technique. The proposed circuit uses a clocked architecture that results in lower power dissipation and improved power-delay product compared to traditional designs. As a proof of concept, the authors implemented an 8x8 bit multiplier using multiple 4x4 bit multiplier blocks. Simulation results show the 8x8 multiplier design has an average power of 0.11108 microwatts when implemented using a 0.5um CMOS process at 5V supply voltage.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A high speed dynamic ripple carry addereSAT Journals
Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
TRANSFORMER FAULT DETECTION AND MONITORINGIRJET Journal
This document describes a project to detect and monitor faults in power transformers using sensors and GSM technology. The system measures four parameters - oil level, temperature, open circuit, and short circuit. Sensors detect faults and send SMS alerts to responsible personnel. The aim is to reduce response time for faults to protect transformers and maintain power stability. When faults are detected, the controlling unit can automatically shut down power.
IRJET- Implementation of Combined SVL Technique in Domino Inverter using Micr...IRJET Journal
This document discusses the implementation of a combined self-controllable voltage level (SVL) technique in a domino inverter to reduce power consumption. The combined SVL technique incorporates both upper and lower SVL circuits. The lower SVL circuit increases the back gate bias of transistors, raising their threshold voltage and reducing leakage current. The upper SVL circuit decreases the supply voltage, reducing drain induced barrier lowering and also raising threshold voltage. Simulations using Microwind at 90nm show the combined SVL domino inverter has 27.7% lower power consumption than a standard static CMOS inverter. The combined SVL technique is an effective way to reduce power dissipation in domino logic circuits.
Digital Voltage Control of DC-DC Boost ConverterIJERA Editor
The need for digital control for faster communication between power stage module & system controllers is increased with requirement of load complexity. The requirements also include stability of power module with the parametric variation. This paper presents a digital control of a dc-dc boost converter under nominal parameter conditions. The system controller has been verified in both frequency response as well as MATLAB-Simulink under nominal & parametric varying condition. The modeling of converter has been illustrated using state-space averaging technique. Direct digital design method is equipped to design the controller in frequency response to yield constant load voltage. The characteristic of load voltage before & after parametric variation is shown.
IRJET- Design and Implementation of CMOS and CNT based 2:1 Multiplexer at...IRJET Journal
This document compares the design and performance of a 2:1 multiplexer circuit built using carbon nanotube field-effect transistors (CNTFETs) versus complementary metal–oxide–semiconductor (CMOS) transistors at a 32nm technology node. Simulation results show that the CNTFET-based multiplexer has lower power consumption (6.40nW vs 6.83nW), lower leakage power (319.20pW vs 504.218pW), and similar delay (40.84ns vs 40.86ns) compared to the CMOS-based design. Overall, the CNTFET multiplexer exhibits around a 58% reduction in leakage power over the CMOS design while maintaining comparable operation, demonstrating
Similar to Implementation and Comparative Analysis of 2x1 Multiplexers Using Different Dynamic Logic Techniques (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
The CBC machine is a common diagnostic tool used by doctors to measure a patient's red blood cell count, white blood cell count and platelet count. The machine uses a small sample of the patient's blood, which is then placed into special tubes and analyzed. The results of the analysis are then displayed on a screen for the doctor to review. The CBC machine is an important tool for diagnosing various conditions, such as anemia, infection and leukemia. It can also help to monitor a patient's response to treatment.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.