Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz. Simulate, synthesize and physical design your adder.
Follow the directions below to create the 32-bit CSA
• Create a 4-bit Carry Look Ahead (CLA) adder
• combine 8-stages of the CLA adder to create the 32-bit CSA
• use 4-bit 2-to-1 mux to choose the sum from each set of CLA
• use 1-bit 2-to-1 mux to select the carry for the next stage
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adder
Types of Adder
Half Adder
Exclusive OR gate and AND Gate
Block diagram
Logic circuit
Truth Table
Full Adder
OR Gate
Block diagram
Logic circuit
Truth Table
a technical review of efficient and high speed adders for vedic multipliersINFOGAIN PUBLICATION
n the VLSI system design, the main regions of research are the reduced size & increase speed path logic systems. A fundamental requirement of high speed, addition and multiplication is always needed for the high performance digital processors. In the digital system, the speed of addition depend on the propagation of carry, which is generated successively, after the previous bit has been summed & carry is propagated, into the next location. There are numerous types of adders available likes Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Avoid Adder, and Carry Select Adder, which have their own benefits and drawbacks. With the advances technology, proposal of Carry select adder (CSA) which deals either of the high speed, low power consumption, regularity of layout a smaller amount area and compact VLSI design implementation. Researchers justify that Ripple Carry Adder had a lesser area but having lesser in speed, in comparing with Carry Select Adders are fastest speed but possess a larger area. The Carry Look Ahead Adder is in between the spectrum having proper trade-offs between time and area complexities.
Area Efficient 4-Bit Full Adder Design using CMOS 90 nm Technology IJEEE
To any digital circuit reduction of surface area is one of the important parameter. Very large scale integration VLSI provides the way to reduce the silicon area. In this paper area efficient design of 4 bit full adder is developed. Adder is one important element in computer arithmetic. It uses for the addition of binary numbers. To design 4-bit full adder two different methods are used in this paper. First is fully auto CMOS design and second is semicustom design. In first fully automatic CMOS design schematic and layout of 4- bit full adder are developed. In second semicustom design method layout of 4-bit full adder is developed by using number of fringers. The layouts of both techniques are simulated using 90nm technology. It can be observed from the simulated results that semicustom layout results in 72% reduction of silicon area as compared to full automatic CMOS design.
Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz. Simulate, synthesize and physical design your adder.
Follow the directions below to create the 32-bit CSA
• Create a 4-bit Carry Look Ahead (CLA) adder
• combine 8-stages of the CLA adder to create the 32-bit CSA
• use 4-bit 2-to-1 mux to choose the sum from each set of CLA
• use 1-bit 2-to-1 mux to select the carry for the next stage
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adder
Types of Adder
Half Adder
Exclusive OR gate and AND Gate
Block diagram
Logic circuit
Truth Table
Full Adder
OR Gate
Block diagram
Logic circuit
Truth Table
a technical review of efficient and high speed adders for vedic multipliersINFOGAIN PUBLICATION
n the VLSI system design, the main regions of research are the reduced size & increase speed path logic systems. A fundamental requirement of high speed, addition and multiplication is always needed for the high performance digital processors. In the digital system, the speed of addition depend on the propagation of carry, which is generated successively, after the previous bit has been summed & carry is propagated, into the next location. There are numerous types of adders available likes Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Avoid Adder, and Carry Select Adder, which have their own benefits and drawbacks. With the advances technology, proposal of Carry select adder (CSA) which deals either of the high speed, low power consumption, regularity of layout a smaller amount area and compact VLSI design implementation. Researchers justify that Ripple Carry Adder had a lesser area but having lesser in speed, in comparing with Carry Select Adders are fastest speed but possess a larger area. The Carry Look Ahead Adder is in between the spectrum having proper trade-offs between time and area complexities.
Area Efficient 4-Bit Full Adder Design using CMOS 90 nm Technology IJEEE
To any digital circuit reduction of surface area is one of the important parameter. Very large scale integration VLSI provides the way to reduce the silicon area. In this paper area efficient design of 4 bit full adder is developed. Adder is one important element in computer arithmetic. It uses for the addition of binary numbers. To design 4-bit full adder two different methods are used in this paper. First is fully auto CMOS design and second is semicustom design. In first fully automatic CMOS design schematic and layout of 4- bit full adder are developed. In second semicustom design method layout of 4-bit full adder is developed by using number of fringers. The layouts of both techniques are simulated using 90nm technology. It can be observed from the simulated results that semicustom layout results in 72% reduction of silicon area as compared to full automatic CMOS design.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Design and Analysis of a Conventional Wallace Multiplier in 180nm CMOS Techno...iosrjce
Multiplier is an important building block in many electronic system design. There are many available
methods and techniques for designing multipliers. Wallace multiplier is important and popular multiplier
architecture. In this paper, design and analysis of a conventional Wallace multiplier is presented by using
Cadence virtuoso in 180nm CMOS technology. Performance analysis in terms of power, delay, and power delay
product are performed for a 4-bit Wallace multiplier in 180nm CMOS technology. The power and delay of the
designed multiplier are 689.3µW and 50µs respectively.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly
on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in
general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial
product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic
Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial
product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an
efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques,
Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for
N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder
and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit
multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated
using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier
using Urdhva–Tiryakbhyam Sutra in VHDL Environment.
MAC unit is used for high performance digital signal processing systems. The DSP applications include filtering, convolution, and inner products.
The design consists of 64 bit modified Wallace multiplier.
128 bit carry save adder and a register/ accumulator.
The output of carry save adder is 129 bit i.e. one bit is for the carry (128bits+ 1 bit). Then, the output is given to the accumulator register.
The accumulator register used in this design is Parallel In Parallel Out (PIPO).
The output of the accumulator register is taken out or fed back as one of the input to the carry save adder.
APPLICATIONS:
1) digital signal processing (DSP) applications
a. Signal filtering
b. convolution.
c. Decreasing number of inner products.
2) Optical communications.
Design and implementation of 15 4 compressor using 1-bit semi domino full add...eSAT Journals
Abstract In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre. Keywords: Semi Domino Logic, Full adder, 5-3 compressor, power, delay, PDP, TSMC 28nm.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A comparative study of full adder using static cmos logic styleeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits.
One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper
we will present a comparative analysis of existing clock gating techniques on some synchronous digital design
like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the
existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using
tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND
logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All
experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using
XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the
hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%.
Keywords — Tri state buffer; VLSI; Xilinx; glitches; hazards;Sparten.
A Low power and area efficient CLA adder design using Full swing GDI techniqueIJERA Editor
The low power VLSI design has an important role in designing of many electronic systems. While designing
any combinational or sequential circuits, the important parameters like power consumption, implementation
area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient
data path logic systems forms the largest areas of research in VLSI system design. This paper presents
a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed
CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard
CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical
limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections.
These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing
restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and
Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results
have shown a greater reduction in delay, power dissipation and area.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
Mechanical properties of hybrid fiber reinforced concrete for pavementseSAT Journals
Abstract
The effect of addition of mono fibers and hybrid fibers on the mechanical properties of concrete mixture is studied in the present
investigation. Steel fibers of 1% and polypropylene fibers 0.036% were added individually to the concrete mixture as mono fibers and
then they were added together to form a hybrid fiber reinforced concrete. Mechanical properties such as compressive, split tensile and
flexural strength were determined. The results show that hybrid fibers improve the compressive strength marginally as compared to
mono fibers. Whereas, hybridization improves split tensile strength and flexural strength noticeably.
Keywords:-Hybridization, mono fibers, steel fiber, polypropylene fiber, Improvement in mechanical properties.
Material management in construction – a case studyeSAT Journals
Abstract
The objective of the present study is to understand about all the problems occurring in the company because of improper application
of material management. In construction project operation, often there is a project cost variance in terms of the material, equipments,
manpower, subcontractor, overhead cost, and general condition. Material is the main component in construction projects. Therefore,
if the material management is not properly managed it will create a project cost variance. Project cost can be controlled by taking
corrective actions towards the cost variance. Therefore a methodology is used to diagnose and evaluate the procurement process
involved in material management and launch a continuous improvement was developed and applied. A thorough study was carried
out along with study of cases, surveys and interviews to professionals involved in this area. As a result, a methodology for diagnosis
and improvement was proposed and tested in selected projects. The results obtained show that the main problem of procurement is
related to schedule delays and lack of specified quality for the project. To prevent this situation it is often necessary to dedicate
important resources like money, personnel, time, etc. To monitor and control the process. A great potential for improvement was
detected if state of the art technologies such as, electronic mail, electronic data interchange (EDI), and analysis were applied to the
procurement process. These helped to eliminate the root causes for many types of problems that were detected.
Managing drought short term strategies in semi arid regions a case studyeSAT Journals
Abstract
Drought management needs multidisciplinary action. Interdisciplinary efforts among the experts in various fields of the droughts
prone areas are helpful to achieve tangible and permanent solution for this recurring problem. The Gulbarga district having the total
area around 16, 240 sq.km, and accounts 8.45 per cent of the Karnataka state area. The district has been situated with latitude 17º 19'
60" North and longitude of 76 º 49' 60" east. The district is situated entirely on the Deccan plateau positioned at a height of 300 to
750 m above MSL. Sub-tropical, semi-arid type is one among the drought prone districts of Karnataka State. The drought
management is very important for a district like Gulbarga. In this paper various short term strategies are discussed to mitigate the
drought condition in the district.
Keywords: Drought, South-West monsoon, Semi-Arid, Rainfall, Strategies etc.
Life cycle cost analysis of overlay for an urban road in bangaloreeSAT Journals
Abstract
Pavements are subjected to severe condition of stresses and weathering effects from the day they are constructed and opened to traffic
mainly due to its fatigue behavior and environmental effects. Therefore, pavement rehabilitation is one of the most important
components of entire road systems. This paper highlights the design of concrete pavement with added mono fibers like polypropylene,
steel and hybrid fibres for a widened portion of existing concrete pavement and various overlay alternatives for an existing
bituminous pavement in an urban road in Bangalore. Along with this, Life cycle cost analyses at these sections are done by Net
Present Value (NPV) method to identify the most feasible option. The results show that though the initial cost of construction of
concrete overlay is high, over a period of time it prove to be better than the bituminous overlay considering the whole life cycle cost.
The economic analysis also indicates that, out of the three fibre options, hybrid reinforced concrete would be economical without
compromising the performance of the pavement.
Keywords: - Fatigue, Life cycle cost analysis, Net Present Value method, Overlay, Rehabilitation
Laboratory studies of dense bituminous mixes ii with reclaimed asphalt materialseSAT Journals
Abstract
The issue of growing demand on our nation’s roadways over that past couple of decades, decreasing budgetary funds, and the need to
provide a safe, efficient, and cost effective roadway system has led to a dramatic increase in the need to rehabilitate our existing
pavements and the issue of building sustainable road infrastructure in India. With these emergency of the mentioned needs and this
are today’s burning issue and has become the purpose of the study.
In the present study, the samples of existing bituminous layer materials were collected from NH-48(Devahalli to Hassan) site.The
mixtures were designed by Marshall Method as per Asphalt institute (MS-II) at 20% and 30% Reclaimed Asphalt Pavement (RAP).
RAP material was blended with virgin aggregate such that all specimens tested for the, Dense Bituminous Macadam-II (DBM-II)
gradation as per Ministry of Roads, Transport, and Highways (MoRT&H) and cost analysis were carried out to know the economics.
Laboratory results and analysis showed the use of recycled materials showed significant variability in Marshall Stability, and the
variability increased with the increase in RAP content. The saving can be realized from utilization of recycled materials as per the
methodology, the reduction in the total cost is 19%, 30%, comparing with the virgin mixes.
Keywords: Reclaimed Asphalt Pavement, Marshall Stability, MS-II, Dense Bituminous Macadam-II
Laboratory investigation of expansive soil stabilized with natural inorganic ...eSAT Journals
Abstract
Soil stabilization has proven to be one of the oldest techniques to improve the soil properties. Literature review conducted revealed
that uses of natural inorganic stabilizers are found to be one of the best options for soil stabilization. In this regard an attempt has
been made to evaluate the influence of RBI-81 stabilizer on properties of black cotton soil through laboratory investigations. Black
cotton soil with varying percentages of RBI-81 viz., 0, 0.5, 1, 1.5, 2, and 2.5 percent were studied for moisture density relationships
and strength behaviour of soils. Also the effect of curing period was evaluated as literature review clearly emphasized the strength
gain of soils stabilized with RBI-81 over a period of time. The results obtained shows that the unconfined compressive strength of
specimens treated with RBI-81 increased approximately by 250% for a curing period of 28 days as compared to virgin soil. Further
the CBR value improved approximately by 400%. The studies indicated an increasing trend for soil strength behaviour with
increasing percentage of RBI-81 suggesting its potential applications in soil stabilization.
Influence of reinforcement on the behavior of hollow concrete block masonry p...eSAT Journals
Abstract
Reinforced masonry was developed to exploit the strength potential of masonry and to solve its lack of tensile strength. Experimental
and analytical studies have been carried out to investigate the effect of reinforcement on the behavior of hollow concrete block
masonry prisms under compression and to predict ultimate failure compressive strength. In the numerical program, three dimensional
non-linear finite elements (FE) model based on the micro-modeling approach is developed for both unreinforced and reinforced
masonry prisms using ANSYS (14.5). The proposed FE model uses multi-linear stress-strain relationships to model the non-linear
behavior of hollow concrete block, mortar, and grout. Willam-Warnke’s five parameter failure theory has been adopted to model the
failure of masonry materials. The comparison of the numerical and experimental results indicates that the FE models can successfully
capture the highly nonlinear behavior of the physical specimens and accurately predict their strength and failure mechanisms.
Keywords: Structural masonry, Hollow concrete block prism, grout, Compression failure, Finite element method,
Numerical modeling.
Influence of compaction energy on soil stabilized with chemical stabilizereSAT Journals
Abstract
Increase in traffic along with heavier magnitude of wheel loads cause rapid deterioration in pavements. There is a need to improve
density, strength of soil subgrade and other pavement layers. In this study an attempt is made to improve the properties of locally
available loamy soil using twin approaches viz., i) increasing the compaction of soil and ii) treating the soil with chemical stabilizer.
Laboratory studies are carried out on both untreated and treated soil samples compacted by different compaction efforts. Studies
show that increase in compaction effort results in increase in density of soil. However in soil treated with chemical stabilizer, rate of
increase in density is not significant. The soil treated with chemical stabilizer exhibits improvement in both strength and performance
properties.
Keywords: compaction, density, subgradestabilization, resilient modulus
Geographical information system (gis) for water resources managementeSAT Journals
Abstract
Water resources projects are inherited with overlapping and at times conflicting objectives. These projects are often of varied sizes
ranging from major projects with command areas of millions of hectares to very small projects implemented at the local level. Thus,
in all these projects there is seldom proper coordination which is essential for ensuring collective sustainability.
Integrated watershed development and management is the accepted answer but in turn requires a comprehensive framework that can
enable planning process involving all the stakeholders at different levels and scales is compulsory. Such a unified hydrological
framework is essential to evaluate the cause and effect of all the proposed actions within the drainage basins.
The present paper describes a hydrological framework developed in the form of a Hydrologic Information System (HIS) which is
intended to meet the specific information needs of the various line departments of a typical State connected with water related aspects.
The HIS consist of a hydrologic information database coupled with tools for collating primary and secondary data and tools for
analyzing and visualizing the data and information. The HIS also incorporates hydrological model base for indirect assessment of
various entities of water balance in space and time. The framework would be maintained and updated to reflect fully the most
accurate ground truth data and the infrastructure requirements for planning and management.
Keywords: Hydrological Information System (HIS); WebGIS; Data Model; Web Mapping Services
Forest type mapping of bidar forest division, karnataka using geoinformatics ...eSAT Journals
Abstract
The study demonstrate the potentiality of satellite remote sensing technique for the generation of baseline information on forest types
including tree plantation details in Bidar forest division, Karnataka covering an area of 5814.60Sq.Kms. The Total Area of Bidar
forest division is 5814Sq.Kms analysis of the satellite data in the study area reveals that about 84% of the total area is Covered by
crop land, 1.778% of the area is covered by dry deciduous forest, 1.38 % of mixed plantation, which is very threatening to the
environmental stability of the forest, future plantation site has been mapped. With the use of latest Geo-informatics technology proper
and exact condition of the trees can be observed and necessary precautions can be taken for future plantation works in an appropriate
manner
Keywords:-RS, GIS, GPS, Forest Type, Tree Plantation
Factors influencing compressive strength of geopolymer concreteeSAT Journals
Abstract
To study effects of several factors on the properties of fly ash based geopolymer concrete on the compressive strength and also the
cost comparison with the normal concrete. The test variables were molarities of sodium hydroxide(NaOH) 8M,14M and 16M, ratio of
NaOH to sodium silicate (Na2SiO3) 1, 1.5, 2 and 2.5, alkaline liquid to fly ash ratio 0.35 and 0.40 and replacement of water in
Na2SiO3 solution by 10%, 20% and 30% were used in the present study. The test results indicated that the highest compressive
strength 54 MPa was observed for 16M of NaOH, ratio of NaOH to Na2SiO3 2.5 and alkaline liquid to fly ash ratio of 0.35. Lowest
compressive strength of 27 MPa was observed for 8M of NaOH, ratio of NaOH to Na2SiO3 is 1 and alkaline liquid to fly ash ratio of
0.40. Alkaline liquid to fly ash ratio of 0.35, water replacement of 10% and 30% for 8 and 16 molarity of NaOH and has resulted in
compressive strength of 36 MPa and 20 MPa respectively. Superplasticiser dosage of 2 % by weight of fly ash has given higher
strength in all cases.
Keywords: compressive strength, alkaline liquid, fly ash
Experimental investigation on circular hollow steel columns in filled with li...eSAT Journals
Abstract
Composite Circular hollow Steel tubes with and without GFRP infill for three different grades of Light weight concrete are tested for
ultimate load capacity and axial shortening , under Cyclic loading. Steel tubes are compared for different lengths, cross sections and
thickness. Specimens were tested separately after adopting Taguchi’s L9 (Latin Squares) Orthogonal array in order to save the initial
experimental cost on number of specimens and experimental duration. Analysis was carried out using ANN (Artificial Neural
Network) technique with the assistance of Mini Tab- a statistical soft tool. Comparison for predicted, experimental & ANN output is
obtained from linear regression plots. From this research study, it can be concluded that *Cross sectional area of steel tube has most
significant effect on ultimate load carrying capacity, *as length of steel tube increased- load carrying capacity decreased & *ANN
modeling predicted acceptable results. Thus ANN tool can be utilized for predicting ultimate load carrying capacity for composite
columns.
Keywords: Light weight concrete, GFRP, Artificial Neural Network, Linear Regression, Back propagation, orthogonal
Array, Latin Squares
Experimental behavior of circular hsscfrc filled steel tubular columns under ...eSAT Journals
Abstract
This paper presents an outlook on experimental behavior and a comparison with predicted formula on the behaviour of circular
concentrically loaded self-consolidating fibre reinforced concrete filled steel tube columns (HSSCFRC). Forty-five specimens were
tested. The main parameters varied in the tests are: (1) percentage of fiber (2) tube diameter or width to wall thickness ratio (D/t
from 15 to 25) (3) L/d ratio from 2.97 to 7.04 the results from these predictions were compared with the experimental data. The
experimental results) were also validated in this study.
Keywords: Self-compacting concrete; Concrete-filled steel tube; axial load behavior; Ultimate capacity.
Evaluation of punching shear in flat slabseSAT Journals
Abstract
Flat-slab construction has been widely used in construction today because of many advantages that it offers. The basic philosophy in
the design of flat slab is to consider only gravity forces; this method ignores the effect of punching shear due to unbalanced moments
at the slab column junction which is critical. An attempt has been made to generate generalized design sheets which accounts both
punching shear due to gravity loads and unbalanced moments for cases (a) interior column; (b) edge column (bending perpendicular
to shorter edge); (c) edge column (bending parallel to shorter edge); (d) corner column. These design sheets are prepared as per
codal provisions of IS 456-2000. These design sheets will be helpful in calculating the shear reinforcement to be provided at the
critical section which is ignored in many design offices. Apart from its usefulness in evaluating punching shear and the necessary
shear reinforcement, the design sheets developed will enable the designer to fix the depth of flat slab during the initial phase of the
design.
Keywords: Flat slabs, punching shear, unbalanced moment.
Evaluation of performance of intake tower dam for recent earthquake in indiaeSAT Journals
Abstract
Intake towers are typically tall, hollow, reinforced concrete structures and form entrance to reservoir outlet works. A parametric
study on dynamic behavior of circular cylindrical towers can be carried out to study the effect of depth of submergence, wall thickness
and slenderness ratio, and also effect on tower considering dynamic analysis for time history function of different soil condition and
by Goyal and Chopra accounting interaction effects of added hydrodynamic mass of surrounding and inside water in intake tower of
dam
Key words: Hydrodynamic mass, Depth of submergence, Reservoir, Time history analysis,
Evaluation of operational efficiency of urban road network using travel time ...eSAT Journals
Abstract
Efficiency of the road network system is analyzed by travel time reliability measures. The study overlooks on an important measure of
travel time reliability and prioritizing Tiruchirappalli road network. Traffic volume and travel time were collected using license plate
matching method. Travel time measures were estimated from average travel time and 95th travel time. Effect of non-motorized vehicle
on efficiency of road system was evaluated. Relation between buffer time index and traffic volume was created. Travel time model has
been developed and travel time measure was validated. Then service quality of road sections in network were graded based on
travel time reliability measures.
Keywords: Buffer Time Index (BTI); Average Travel Time (ATT); Travel Time Reliability (TTR); Buffer Time (BT).
Estimation of surface runoff in nallur amanikere watershed using scs cn methodeSAT Journals
Abstract
The development of watershed aims at productive utilization of all the available natural resources in the entire area extending from
ridge line to stream outlet. The per capita availability of land for cultivation has been decreasing over the years. Therefore, water and
the related land resources must be developed, utilized and managed in an integrated and comprehensive manner. Remote sensing and
GIS techniques are being increasingly used for planning, management and development of natural resources. The study area, Nallur
Amanikere watershed geographically lies between 110 38’ and 110 52’ N latitude and 760 30’ and 760 50’ E longitude with an area of
415.68 Sq. km. The thematic layers such as land use/land cover and soil maps were derived from remotely sensed data and overlayed
through ArcGIS software to assign the curve number on polygon wise. The daily rainfall data of six rain gauge stations in and around
the watershed (2001-2011) was used to estimate the daily runoff from the watershed using Soil Conservation Service - Curve Number
(SCS-CN) method. The runoff estimated from the SCS-CN model was then used to know the variation of runoff potential with different
land use/land cover and with different soil conditions.
Keywords: Watershed, Nallur watershed, Surface runoff, Rainfall-Runoff, SCS-CN, Remote Sensing, GIS.
Estimation of morphometric parameters and runoff using rs & gis techniqueseSAT Journals
Abstract
Land and water are the two vital natural resources, the optimal management of these resources with minimum adverse environmental
impact are essential not only for sustainable development but also for human survival. Satellite remote sensing with geographic
information system has a pragmatic approach to map and generate spatial input layers of predicting response behavior and yield of
watershed. Hence, in the present study an attempt has been made to understand the hydrological process of the catchment at the
watershed level by drawing the inferences from moprhometric analysis and runoff. The study area chosen for the present study is
Yagachi catchment situated in Chickamaglur and Hassan district lies geographically at a longitude 75⁰52’08.77”E and
13⁰10’50.77”N latitude. It covers an area of 559.493 Sq.km. Morphometric analysis is carried out to estimate morphometric
parameters at Micro-watershed to understand the hydrological response of the catchment at the Micro-watershed level. Daily runoff
is estimated using USDA SCS curve number model for a period of 10 years from 2001 to 2010. The rainfall runoff relationship of the
study shows there is a positive correlation.
Keywords: morphometric analysis, runoff, remote sensing and GIS, SCS - method
-
Effect of variation of plastic hinge length on the results of non linear anal...eSAT Journals
Abstract The nonlinear Static procedure also well known as pushover analysis is method where in monotonically increasing loads are applied to the structure till the structure is unable to resist any further load. It is a popular tool for seismic performance evaluation of existing and new structures. In literature lot of research has been carried out on conventional pushover analysis and after knowing deficiency efforts have been made to improve it. But actual test results to verify the analytically obtained pushover results are rarely available. It has been found that some amount of variation is always expected to exist in seismic demand prediction of pushover analysis. Initial study is carried out by considering user defined hinge properties and default hinge length. Attempt is being made to assess the variation of pushover analysis results by considering user defined hinge properties and various hinge length formulations available in literature and results compared with experimentally obtained results based on test carried out on a G+2 storied RCC framed structure. For the present study two geometric models viz bare frame and rigid frame model is considered and it is found that the results of pushover analysis are very sensitive to geometric model and hinge length adopted. Keywords: Pushover analysis, Base shear, Displacement, hinge length, moment curvature analysis
Effect of use of recycled materials on indirect tensile strength of asphalt c...eSAT Journals
Abstract
Depletion of natural resources and aggregate quarries for the road construction is a serious problem to procure materials. Hence
recycling or reuse of material is beneficial. On emphasizing development in sustainable construction in the present era, recycling of
asphalt pavements is one of the effective and proven rehabilitation processes. For the laboratory investigations reclaimed asphalt
pavement (RAP) from NH-4 and crumb rubber modified binder (CRMB-55) was used. Foundry waste was used as a replacement to
conventional filler. Laboratory tests were conducted on asphalt concrete mixes with 30, 40, 50, and 60 percent replacement with RAP.
These test results were compared with conventional mixes and asphalt concrete mixes with complete binder extracted RAP
aggregates. Mix design was carried out by Marshall Method. The Marshall Tests indicated highest stability values for asphalt
concrete (AC) mixes with 60% RAP. The optimum binder content (OBC) decreased with increased in RAP in AC mixes. The Indirect
Tensile Strength (ITS) for AC mixes with RAP also was found to be higher when compared to conventional AC mixes at 300C.
Keywords: Reclaimed asphalt pavement, Foundry waste, Recycling, Marshall Stability, Indirect tensile strength.
TOP 10 B TECH COLLEGES IN JAIPUR 2024.pptxnikitacareer3
Looking for the best engineering colleges in Jaipur for 2024?
Check out our list of the top 10 B.Tech colleges to help you make the right choice for your future career!
1) MNIT
2) MANIPAL UNIV
3) LNMIIT
4) NIMS UNIV
5) JECRC
6) VIVEKANANDA GLOBAL UNIV
7) BIT JAIPUR
8) APEX UNIV
9) AMITY UNIV.
10) JNU
TO KNOW MORE ABOUT COLLEGES, FEES AND PLACEMENT, WATCH THE FULL VIDEO GIVEN BELOW ON "TOP 10 B TECH COLLEGES IN JAIPUR"
https://www.youtube.com/watch?v=vSNje0MBh7g
VISIT CAREER MANTRA PORTAL TO KNOW MORE ABOUT COLLEGES/UNIVERSITITES in Jaipur:
https://careermantra.net/colleges/3378/Jaipur/b-tech
Get all the information you need to plan your next steps in your medical career with Career Mantra!
https://careermantra.net/
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Recycled Concrete Aggregate in Construction Part III
A high speed dynamic ripple carry adder
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A HIGH SPEED DYNAMIC RIPPLE CARRY ADDER
Y. Anil Kumar1
, M. Satyanarayana2
1
Student, Department of ECE, MVGR College of Engineering, India.
2
Associate Professor, Department of ECE, MVGR College of Engineering, India.
Abstract
Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder
architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among
the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path;
apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related
problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the
critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten
transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The
CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area
compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction
compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor
version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing
blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power
dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools.
Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
--------------------------------------------------------------------***----------------------------------------------------------------------
1. INTRODUCTION
Addition is very crucial to perform fundamental arithmetic
operations. It is used extensively in many VLSI designs and
is by so far the most frequently used operation in general-
purpose system and in application-specific processors. Also,
because the operations of subtraction, multiplication,
division and address calculation usually rely on the
operation of addition, addition is often seen as an
indispensable part of the arithmetic unit. It is dubbed the
heart of any microprocessor, DSP architecture, and data
processing system.
The carry propagation from each bit to its higher position
results in a substantial delay. So the adder which lies in the
critical delay path effectively determines the system’s
overall speed. An efficient adder builds an efficient system.
This leads to increasing popularity of smaller and more
durable mobile computing and communication systems.
There are many adder architectures namely the Ripple Carry
Adder (RCA), the Carry Look-Ahead Adder (CLA), the
Carry Skip Adder (CSK), the Carry Select Adder (CSL), the
Carry Save Adder (CSA) and the Conditional Sum Adder
(COS). Each architecture has its own advantages.
Among all the adder architectures, the RCA occupies the
smallest area and offers good performance for random data
input. But the delay depends on length of carry propagation
path. As the number of inputs increases delay increases
linearly. For an n-bit RCA the delay is nT, where T is the
delay of a full adder block. The overall performance of an
RCA depends on design on Full adder block.
2. FULL ADDER BLOCK
There are many full adder (FA) architectures, where the
conventional CMOS adder uses 32 transistors, the highest
among the adders and least number of transistors required to
design a full adder are six. But the CMOS logic and
dynamic logic provides less power dissipation. But the
dynamic logic suffers from cascading problem. Domino
logic overcomes the cascading problem with an extra
inverter [3]. The cascading problem in dynamic logic and an
extra inverter overhead is compensated by NORA and
ZIPPER logic, but NORA logic suffers from charge leakage
and ZIPPER logic needs non overlapping clocks that creates
area overhead[1-2].
Some other versions of full adders include Complementary
pass transistor logic full adder, Transmission gate full adder,
17-transistor full adder, 14- transistor full adder, 10-
transistor full adder [5] etc.,
In this paper a high speed dynamic logic is proposed which
is derived from (Constant Delay) CD logic [8]. Before
discussing about CD logic, Feed Through Logic (FTL) [4]
should be understood. FTL is shown in fig. 1 overcomes the
area over head in domino logic and cascading problem in
dynamic logic. By removing the footer transistor and
placing a pre-discharge transistor parallel to output node, the
cascading problem is solved without an extra inverter. But
drawback of FTL is higher power dissipation than dynamic
and domino logic. This is due to the short circuit path from
VDD to Ground when M1 and NMOS pull down network
conducts simultaneously. CD logic overcomes the short
circuit problem in FTL with the help of an additional timing
block. This timing block prevents the pull up transistors and
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NMOS pull down logic to conduct simultaneously. The
inverter at the output is to eliminate the noise. CD LOGIC
can implement both inverting logic and non inverting logic.
Fig. 2 shows buffer implemented using constant delay logic.
In this paper six types of full adder configurations are
compared with each other, where A, B and CIN are the
inputs and COUT and SUM are the outputs. Fig. 3(a) and
3(b) shows the sum generation units, where 3(b) consumes
less power but provides more delay compared to CMOS
sum generation. Figure 4(a) – (d) shows the carry generation
units of Conventional CMOS logic, Domino logic, 10-
Transistor Full adder and CD logic respectively. Out of the 4
types of carry generation units the 10-Transistor FA requires
least number of transistors to generate carry. It generates the
inverted version of carry, so to use it in RCA the COUT
signal should be given to an inverter input. The noise in
COUT signal is removed by the inverter, to remove the noise
in SUM signal two inverters or a buffer should be added to
the SUM signal output. But this addition of inverters makes
it increase its size and power dissipation. When 10-T FA is
used in RCA, by connecting the sum output of the last stage
to a buffer, the noise at the output is reduced. CMOS logic
and Domino logic carry generation unit consumes the lesser
power. CD logic provides lesser delay above all the carry
generation units because of its pre-evaluation concept.
In this paper CD logic technique with optimized timing
block is utilized to design an 8-bit RCA. Importance of CD
logic and methods to overcome the drawbacks of CD logic
are briefly explained in the next section.
Fig -1 feed through logic (FTL)
Fig -2 Constant delay logic buffer
Fig -3 Sum generation units
Fig -4 Carry generation units
3. PROPOSED TIMING BLOCKS OF CD
LOGIC.
CD logic in D-Q mode shows high speed performance due
to its pre-evaluation nature. But when compared to domino
logic(without keeper), CD logic requires extra 11 transistors
and extra 13 compared to dynamic logic. In CD logic the
extra number of transistors is mainly due to timing block
(TB), so optimizing the timing block reduces the area
overhead and power consumption. The timing block should
be optimized in such a way that the delay should not be
increased.
Two optimized designs of timing blocks are proposed in this
paper which performs the same logical function of the
original timing block.
8-T Timing Block
In first design the number of transistors in the timing block
is reduced by two. Fig. 5 shows the original timing block
from where the transistors M1 and M3 are removed to get
the same operation performed. Fig. 6 shows the first
modification in timing block i.e., 8-T timing block. The
delay gets increased if this timing block is used because
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transistor M3 has clock as an input i.e., if CLK=’1’ then
TOUT should be pulled to zero.
Fig -5 Timing Block of CD logic
As M3 is absent in this circuit TOUT is made zero through
M2 and M1 using delay inverted clock signal. So TOUT is
inverted version of clock, i.e., when CLK=’1’ TOUT=’0’,
but with some delay. This delay makes the pre-charging
slower, which increases the delay. To reduce the delay, the
W/L ratio of pre-charge transistors should be increased. To
avoid this 9-T timing block is developed.
Fig -6 8-T timing block
9-T Timing block
In the second design one transistor is reduced as shown in
fig. 7, but the 8-T timing block has some limitations for low
leakage paths, and 9-T timing works well with the low
leakage paths but dissipates more power at high leakage
paths. The drawback in 8-T timing block is overcome by
adding transistor M3. So now, charging the TOUT node is
faster compared to that in 8-T timing block. But here the
disadvantage is more power dissipation due to extra
transistor.
Fig -7 9-T timing block
4. IMPLEMENTATION OF 8-BIT RIPPLE
CARRY ADDER
In RCA the carry chain constitute the critical path, so
speeding up the carry helps in improving the speed of the
RCA. Ripple Carry adder is subjected to a glitching
problem. Due to delay in previous stage carry signals the
glitches occur. In CD logic delay from the previous stage is
to be considered seriously as the evaluation time for this
logic type is very less. Evaluation time is said to be the
window width. The window width is equal to the three
inverter delay. Generally in dynamic logic the evaluation
time is the whole evaluation period, but in CD logic it is just
a part of the evaluation period, so the delay should be less
than the window width to prevent false logic evaluation. If
the glitches from the previous state last for the window
width period then false evaluation takes place. To eliminate
this problem the clock signal should be delayed such that the
window width period can be delayed and the glitches can be
avoided. Figure 8 shows the arrangements of inverters to
generate appropriate clock signals for each stage. CLK1,
CLK2 and CLK3are delayed clock signals for different
stages of RCA. This arrangement is only for dynamic logic,
as the static logic doesn’t operate on clock signals.
In this paper an 8-bit RCA is simulated using six different
full adder blocks. The sum generation unit same for all
adder blocks. The simulated results in Table I are of the
RCA circuit that used CMOS sum generation unit. Even
though 12-T adder provides lesser transistors and noise less
output, it creates more delay which is due to the inverters
INV1 and INV2 in fig 3(b). Due to the extra delay the clock
arrangement also should be changed. It requires three extra
delay clock signals as shown in fig 9, CLK for stage1,
CLK1 for stage2, CLK2 for stage3, CLK3 for stage4, CLK4
for stage5, CLK5 for stage6, CLK6 for stage6 and stage7.
Other full adder (FA) with 28 transistors with sizing
strongly in favour of Cout computation [6] can also be used.
A more energy-efficient pass-transistor FA design [7] can
also be used in the full adder design
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Among the compared RCA architectures even though the
10-Transistor FA RCA requires the least number of
transistors the delay is almost equal to the CMOS 32-
Transistor FA RCA and power dissipation is very high.
Considering low leakage conditions Domino logic carry
generation circuit is simulated without a keeper transistor
and that reduced 8 transistors. If the keeper transistor is
included the power dissipation would be equal to that of
CMOS 32-T FA RCA. CD logic occupies more area than
CMOS logic but it has the better power delay product. 8-T
TB CD logic even though provides more delay than CD
logic it has second least power delay product. 9-TB CD
logic is the fastest among the compared logics and having
the third least power delay product. Another logic, the
Current Comparison Domino (CCD) Logic [9] consumes
very less power which is not discussed in this paper but not
faster than CD logic.
Ripple carry adder occupies the least area among all the
other adder architectures, but has more delay when number
of inputs increases. But with modified CD logic in critical
path of RCA makes it suitable for 8-bit applications. Instead
of going to CLA it is better to opt RCA which occupies less
area with increasing speed.
Fig -8 8-bit Ripple carry adder
Figure 9 Clock signals arrangement for CD logic RCA with 12-T sum unit
Table -1 Comparison Of Rca Architectures With Different Logics
Logic type S7 Delay COUT DELAY Number of
transistors
Power Dissipation Power Delay
product (10-18
)
Conventional 32-T FA 2.113 ns 2.07 ns 276 20.5962 n Watts 43.519
Domino Logic 1.04 ns 587.718 ps 160 14.238 n Watts 14.807
CD Logic 677.780 ps 550.134 ps 300 51.191 n Watts 34.656
10-T FA 2.512 n s 2.527 ns 96 59.889 u Watts 150441
8-T TB CD logic 734.65 ps 612.456 ns 284 32.8427 n Watts 24.131
9-T TB CD logic 643.247 ps 575.767 ps 292 42.3167 n Watts 27.220
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Fig -10 Power and Delay characteristics of different types of
8-bit RCA architectures
5. CONCLUSION
In this paper different RCA architectures are analyzed. Even
though the 10-transistor FA occupies less area it failed to
reduce the power and delay. CMOS logic despite of its
bulky nature provides lesser power dissipation, but the delay
increased by 200% when compared to CD logic. Two new
techniques are employed in CD logic to reduce the power
dissipation and delay. The two techniques 8T- Timing block
and 9-T timing block used CD logic succeeded in reducing
the power dissipation compared to its predecessor but the 8-
T timing CD logic failed to reduce the delay. But the 8-T
TB CD logic has lesser delay compared to CMOS logic,
Domino Logic and 10-T FA RCA. Fig. 10 shows the Power-
Delay product and Delay characteristics graph. 8-T TB CD
logic has the better Power-Delay product among the other
CD logic versions. The 8-transistor version also achieves
reduction of delay by 65% and 29% compared to Static and
dynamic logic. But the 8-T TB version has 14% more delay
compared to 9-T TB version. Even though 8-T TB version
dissipates less power than 9-T TB version, as the main aim
is to reduce the critical path 9-T TB version is considered.
Domino logic has the lesser power delay product but the
delay is 53.4% more compared to CD logic and 61.7% more
than 9-TB CD logic. So the domino logic dissipated less
power and CD logic provides more speed. As the VLSI
domain mainly opts for high speed and low power designs,
9-TB CD logic is suitable in replacing critical path circuits
and the remaining circuit can be designed with domino logic
or some other low power logic.
REFERNCES
[1]. N. Goncalves and H. De Man, “NORA: A racefree
dynamic CMOS technique for pipelined logic
structures”, IEEE J. Solid-State Circuits, vol. 18, no. 3,
pp. 261–266, Jun. 1983.
[2]. C. Lee and E. Szeto, “Zipper CMOS”, IEEE Circuits
Syst. Mag., vol. 2,no. 3, pp. 10–16, May 1986.
[3]. Sung-mo (Steve) Kang and Yusuf Leblebici. “CMOS
Digital Integrated Circuits Analysis And Design”, 3rd
edition, WCB McGraw Hill, 2003.
[4]. V. Navarro-Botello, J. A. Montiel-Nelson, and S.
Nooshabadi, “Analysis of high-performance fast feed
through logic families in CMOS”, IEEE Trans. Circuits
Syst. II, xp. Briefs, vol. 54, no. 6, pp. 489–493, Jun.
2007.
[5]. Kiat-Seng Yeo and Kaushik Roy “Low-Voltage, Low-
Power VLSI Subsystems”, Tata McGraw-Hill Edition
2009.
[6]. N. Weste and D. Harris, “CMOS VLSI Design: A
Circuits and Systems Perspective”, 4th ed. Reading,
MA: Addison Wesley, Mar. 2010.
[7]. M. Aguirre-Hernandez and M. Linares-Aranda,
“CMOS full-adders for energy-efficient arithmetic
applications”, IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 19, no. 99, pp. 1–5, Apr. 2010.
[8]. Pierce Chuang, David Li and Manoj Sachdev
“Constant Delay Logic Style” IEEE Transactions On
VLSI Systems, Vol. 21, No. 3, pp. 554-565, March
2013.
[9]. Ali Peiravi, Mohammad Asyaei, “Current-
Comparison-Based Domino: New Low-Leakage High-
Speed Domino Circuit for Wide Fan-In Gates”, IEEE
Transactions VLSI Systems, Vol. 21, No. 5,pp. 934-
943, May 2013.
BIOGRAPHIES
Yerninti Anil Kumar received B.tech
degree in Electronics and Communication
Engineering from LENDI College of Engg.
and Tech. Pursuing M.tech (VLSI) in
MVGR college of Engineering.
Dr. Moturi Satyanarayana received
B.tech in Electronics and Communication
Engineering from Nagarjuna University.
M.tech in Radar and Microwave
Engineering from Andhra University, and
PhD in Antenna Arrays from Andhra
University. Member of IETE, SEMCE, ISTE and ISOI.
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CMOS
logic
Domino
logic
CD logic 8-T TB
CD logic
9-T TB
CD logic
Normalizedvalues
Logic types
Power and Delay characteristics
Power
Delay
product
Delay