1. International Journal of Electrical and Computing Engineering (IJECE)
Vol. 1, Issue. 4, June 2015 ISSN (Online): 2349-8218
29
Digital Circuit Synthesis Using Universal Set of
CMOS MVL Gates1
Swati Sharma, 2
Sakthivel P
1,2
Department of Electronics and Communication Engineering
College of Engineering, Guindy, Anna University, Chennai, INDIA
Abstract— The synthesis of digital circuits is generally performed
in two level logic switching algebra. But if we increase the
representation domain from two level logic(N=2) to N>2 then the
design of Multiple Valued Logic (MVL) digital circuits is
possible. Interconnections play an important role in deep sub-
micron designs as they affects power and area. Due to the
requirement of interconnections the design of binary logic is
limited. In modern SoC designs,the interconnection is becoming a
major problem which can be solved using MVL interconnection.
Thus reduction in the area along with advantage of being able to
easily interface with traditional binary logic circuits are the
benefits of MVL digital circuits. A universal set of MVL CMOS
gates can be used to synthesize and implement any MVL digital
circuit. The lack of existing integrated circuits to implement the
universal set of MVL gates is one of the major drawbacks. To
overcome this issue, the design andimplementationof a universal
set of Integrated Circuits gates using CMOS 180nm technology is
proposed which includes: Maximum (MAX), extended AND
operators- eAND1, eAND2, eAND3, Successor (SUC) to
synthesize any MVL circuit. The proposed gates allows designing
of any MVL digital circuit by utilizing the knowledge coming
from the binary circuits and extending it for the synthesis of
MVL digital circuit.
Keywords—Multiple valued logic, SoC
I. INTRODUCTION
Presently all the digital circuit synthesis is done in two
level logic (L=2), where D = {0, 1} is the domain of numerical
representation. Whereas if we increase the domain D = {0, 1,
2, …. K = L-1}, the synthesis of multi valued logic circuit is
possible.MVL is also known as many valued or multiple
valued or multi valued which traces its origin from the Post
algebra and Lukasiewicz logic [1], [2].
Now a day,designers are facing new challenges due to the
presence of large number of components in modern Systemon
Chip (SoC). High integration of different systems on a single
chip leads to an increment in the number and length of
interconnections [3], the quantity and the delay time [4], and
thus the overall complexity of the systemis increased.
Therefore to overcome interconnection issue, multiple
valued logics are proposed as they decrease the number of
interconnections and processing components. By using MVL,
the number of interconnections N can be reduced as inverse of
log2N. Thus reduction in area of integrated circuit occurs
which promotes multi valued logic.
Also, MVL circuits can be used to represent numbers with
fewer bits as compared to binary, e.g. the decimal number 255
is denoted as 11111111 in binary logic whereas 3333 in
quaternary logic . Therefore since less no. of bits are required
in quaternary logic, processing of the data become faster and
also more reliable [5] [6] [7]. The possibility of representing
the information using MVL is not recent. Flash memory has
been successfully accomplished using MVL [8], for example,
different logic values can be held by a single memory cell.
Some combinational circuits like multipliers [9], adders [10],
as well as FPGAs [11] were also proposed. These devices are
based on current mode thus reducing area but due to the
excessive power consumption & implementation complexities
they are not suitable alternative for standard CMOS designs.
To overcome the issue of static power dissipation , a
voltage mode MVL technique is presented in [12] by using a
standard CMOS process and still maintaining low compaction
by reducing the number of interconnections. Discrimination
among the logic levels has to be done in voltage mode. To
design the DLC (Down Literal Circuit) voltage discriminatory
circuit Neuron MOS is used [13]. To define L logic levels
with different threshold voltage, implementation of CMOS
gates and PMOS and NMOS transistors is proposed in [14]
and [15] respectively.MVL digital circuit synthesis comprised
of operators and their properties. But the lack of existing IC
that can implement universal set of gates and minimization
tools for practical MVL circuit design serve as their main
drawback
To overcome the first drawback ie lack of existing
integrated circuit that can implement universal set of gates,
design and implementation of universal set of IC gates based
on 180nm technology is proposed in this paper. Universal set
of IC gates for quaternary MVL algebra (where domain D =
{0, 1, 2, 3}) comprised of five CMOS gates Maximum
(MAX), Successor (SUC) and extended AND operators:
eAND1, eAND2, eAND3.
Thus this paper presents design and implementation of
universal set of MVL integrated circuit gates, initially

2. International Journal of Electrical and Computing Engineering (IJECE)
Vol. 1, Issue. 4, June 2015 ISSN (Online): 2349-8218
30
proposed in [16], in voltage mode utilizing CMOS technology
and analysis of their transient response.
II. BASIC PRINCIPLES OF MVL
Depending on the assigned values to the inputs variables,
MVL function will represent the value in domain D = {0, 1,
…., K = L-1} and then a unique truth table can be obtained.
Analogous to Products of Sums (POS) or Sum of Products
(SOP) which is a unique representation of the function for
binary algebra , canonical Sum of Extended Products (SOEP)
form is defined for universal set of operators for quaternary
MVL algebra. The already mentioned operators SUC, MAX,
eAND1, eAND2, eAND3 in the introduction, define a
universal set for quaternary logic under the proposed algebra.
Once the universal set is defined, to minimize the number
of terms and literals of the MVL function postulates and
theorems are needed, thus a minimal covering is determined.
Also suitable algebra laws are defined to develop algorithms
in a proper way and to implement software tools for
performing the minimization. In binary algebra, there are
many techniques for function minimization such as K maps,
Espresso, Quine McCluskey etc [17]. Depending on the MVL
algebra under consideration all these binary techniques can be
extended to the MVL domain.
The next step for the synthesis is to design gates in either
CMOS current mode or CMOS voltage mode. In voltage
mode there is problem of how to define voltage levels to
discriminate different logic reference levels for defining the
threshold value of CMOS inverters. As this paper addresses
voltage mode to design gate some characteristics must be
defined to overcome this issue, for example - power
consumption, frequency response, fan-in, fan-out, noise
margins etc that has an effect on the W/L relation between the
PMOS and NMOS gates and also on how to choose the
reference voltage to discriminate among logic levels for the
MVL. In recent years quaternary circuits has been studied
increasingly as they have the practical advantage of
transforming a four-valued signal into a two-valued signal.
The next step is to define an algebra which is easy to learn
and convenient to use, must have a well-known methodology
which is feasible to implement from both algorithmic and
gates point of views. A possible way is to extend the well
known concepts of the binary switching algebra to MVL
algebra. This approach is adopted in this work.
III. MVL ALGEBRA: SUM OF EXTENDED
PRODUCTS FORM:
MVL variables are denoted as Aj for notation purpose.
MVL constants are represented by lower case letters such as j,
k, l and the base of the digital representation is denoted by L
with domain D = {0, 1, 2, …., K = L-1}. The Maximum
operator is denoted by “+” symbol. The proposed closed MVL
algebra is the ordered set with domain D in which acting one
unary Successor(SUC) operator and two binary extended
AND(eAND) and Maximum(MAX) operators (+, *j
) and two
elements 0 and (L-1) with the following definitions.
Definition 1: Successor (SUC) operator is denoted by P1
where P1
= Q with Q being the next element after P1
in cyclic
ordered set D [18]. The notation P1
, P2
, P3
….. PN
indicates that
the Successor operator is applied to P once, twice, thrice and
so on upto N times. Note that A1
P
= (A1 + P) MOD L, where
MOD stands for the modulo operator and symbol „+‟ stands
for arithmetic addition here.
Table 1, Truth table for SUC operator
Definition 2: Extended AND (eAND) operator is denoted by
A1 *j
A2 and by definition A1 *j
A2 = j if A1 = A2 = j else A1 *j
A2 = 0 as shown in Table 2 for quaternary logic D = {0, 1, 2,
3}.
Table 2, Truth table for eAND1, eAND2, eAND3 operator
P P1
P2
P3
0 1 2 3
1 2 3 0
2 3 0 1
3 0 1 2
A1/A2 0 1 2 3
0 0 0 0 0
1 0 0 0 0
2 0 0 1 0
3 0 0 0 0
A1/A2 0 1 2 3
0 0 0 0 0
1 0 1 0 0
2 0 0 0 0
3 0 0 0 0
A1/A2 0 1 2 3
0 0 0 0 0
1 0 0 0 0
2 0 0 0 0
3 0 0 0 1

3. International Journal of Electrical and Computing Engineering (IJECE)
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Definition 3: Maximum operator is denoted by the symbol A1
+ A2 and is defined as A1 + A2 = A1 if A1 > A2 otherwise A1 +
A2 = A2.
Table 3, Truth table for MAX operator
Thus, these SUC, eAND and MAX operators form a
universal set of gates [19], [20].
IV. IMPLEMENTATION OF MVL GATES:
1) SUGGESTED METHOD:
The IC implementation of universal set of gates is done to
prove the concepts and feasibility of these gates to synthesis
any discrete combinational and sequential circuit by utilizing
the proposed algebra. Therefore instead optimization of IC, the
main concern is MVL circuit design process and functionality.
The methodology followed in this work is to first compare
inputs with different threshold voltage threshold in order to
identify four quaternary logic levels. Then the output of the
comparator is fed to a set of control switches that set the
output to four quaternary levels.
The design and implementation of universal set of MVL
IC gates is divided into 3 circuit stages:
a) First stage has a „discriminatory circuit‟ which
identifies the input into four logic levels of
quaternary domain (0, 1, 2, 3).
b) Second stage has a „binary logic circuit‟ for
performing binary logical operations to control set of
switches.
c) Third stage has a „set of switches‟ for setting the
output voltage according to the output of second
stage and to set the logic voltages in the output
CMOS divider is designed.
Fig. 1, Voltage values for Quaternary digit
For our experiments, 180nm CMOS technology is used.
Generally binary logic values are represented by 0 V and 1 V
that means the logic value „0‟ and „1‟ respectively. But in
quaternary representation, four discrete voltage intervals are
needed in order to represent four logic levels. Thus, the
discrete voltage intervals 0 V- 0.7 V, 0.7 V-1.4 V, 1.4 V-2.2 V
and 2.2V- 3.3 V are used to represent four quaternary logic
levels „0‟, „1‟, „2‟ and „3‟ and these logic levels are denoted
as 0q, 1q, 2q, 3q as shown in Fig. 1 and eq. (1). The threshold
voltages 0.7 V, 1.4 V and 2.2 V in the vertical axis correspond
with the VTH shown in Fig. 2 shows standard inverter
behaviour used as comparator in discriminatory circuit.
The implementation of circuit is done in partially binary
circuit levels 0b and 1b with voltage levels of 0 V and 3.3 V,
respectively.
Fig. 2, Behaviour of Comparator
The output of the comparator is at 1b level if the input
voltage is less than VTH represented as 3.3Vin Fig. 2. Here the
voltage level Vdd = 3.3 V represents both 1b and 3q. Thus, by
comparing the input voltage against corresponding threshold,
a unique quaternary digit (QIN) is set in the {0q, 1q, 2q, 3q}
domain as follows:
{ – (1)
A1/A2 0 1 2 3
0 0 1 2 3
1 1 1 2 3
2 2 2 2 3
3 3 3 3 3

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The transition voltages are determined by (W/L)P and
(W/L)N of the PMOS and NMOS transistors in comparator.
Table-1 shows (W, L) for PMOS and NMOS transistors for
each inerter logic gate. Here for notation purpose INV07,
INV14 and INV22 are used to represent inverter logic gates
with thresholds 0.7V, 1.4V, and 2.2V.
Inverter Transistor W L
INV07
NMOS
PMOS
10µm
0.4µm
0.18µm
0.18µm
INV14
NMOS
PMOS
2.8µm
4.4µm
0.18µm
0.18µm
INV22
NMOS
PMOS
0.4µm
10 µm
0.18µm
0.18µm
Table 4, Width (W) and length (L) for Inverter Logic Gates
The value of the threshold voltage depends on W/L ratio.
In Fig.1 the threshold voltage levels 0q, 1q, 2q are evenly
distributed except 3q. Because in order put a value greater than
threshold value VTH= 2.2V, according to the simulation results
the width of PMOS must be changed from Wp = 10µm to Wp
= 60µm, which leads to unpractical design (Wp α V4
TH).
On comparing the input voltage VIN with different
threshold voltages, the output of the inverters INV07, INV14,
INV22 will be as follows:
If VIN > VTH = 0.7 V, the output for inverter INV07 is 0b,
otherwise 1b.
If VIN > VTH = 1.4V, the output for inverter INV14 is 0b,
otherwise1b.
Similarly, if VIN > VTH = 2.2, the output for inverter
INV22 is 0b, otherwise1b.
Now the value of unique quaternary digit (QIN) is set
according to the output of inverters as follows:
If the output of INV07 is 1b, then QIN will be 0b.
If the output of INV07 and INV14 are 0b and 1b
respectively, then QIN will be 1q.
If the output of INV14 and INV22 are 0b and 1b
respectively, then QIN will be 2q.
If the output of INV22 is 0b, then QIN will be 3q.
2) MVL GATES:
a) SUCCESSOR (SUC) GATE:
Fig.3 shows the schematic of MVL SUC gate. It has one
input and one output as shown in Fig. and output can have
four possible values either 0q or 1q or 2q or 3q. To identify all
the quaternary digits at input and then to set the output voltage
as VR0 or VR1 or VR2 or VR3 , four switches MP0, MN0, MN1,
MN2 and three inverters INV07, INV14, INV22 are used.
As shown in Fig.3, in order to define four reference
voltages , gnd and Vdd = 3.3 V are used as two reference
voltages VR0 and VR3 and a voltage divider circuit is used to
establish the other two reference voltages ie VR1 and VR2.
Fig. 3, Schematic of SUC gate
All the transistors MN0, MN1, MN2 and MP0 have one
gate.
MN0, MN1, MN2 transistors has a length and width of
1µm whereas MP0has length of 1µm and width of 2.9µm.
b) EXTENDED AND1 (eAND1) GATE:
Fig.4 shows the schematic of eAND1 gate. It has two
inputs (VIN1 and VIN2) and one output (VOUT). When both VIN1
= VIN2 = 1q then only VOUT = 1q otherwise it will take value 0q.
Thus VOUT can take two possible values either 0q or 1q.
The circuit will generate E or Eb signal when the first set
of inverter INV07 and INV14 both will receive input1 ie VIN1
and the second set of inverter INV07 and INV14 both will
receive input2 ie VIN2. The two signals E and Eb will control a
set of two switches MN0 and MN1 to set the output voltage as
either VR0 = 0V ie 0q or VR1 = 1V ie 1q.
Where, E=NOT(VOUTINV07 OR NOT(VOUTINV14) OR
VOUTINV07 OR NOT(VOUTINV14)).
Eb = NOT(E).
Here, NOT denotes binary operator for Complement and
OR denotes the usual binary operator OR.
As shown in Fig.4, in order to define four reference
voltages , gnd and Vdd = 3.3 V are used as two reference
voltages VR0 and VR3 and a voltage divider circuit is used to
establish the other two reference voltages ie VR1 and VR2.

5. International Journal of Electrical and Computing Engineering (IJECE)
Vol. 1, Issue. 4, June 2015 ISSN (Online): 2349-8218
33
Fig.4, Schematic of eAND1 gate
Both the transistor MN0 and MN1 have one gate and has
width equals to 2µm and length equals to 2µm.
c) EXTENDED AND2 (eAND2) GATE:
Fig.5 shows the schematic of eAND2 gate. Similar to
eAND1, it also has two inputs (VIN1 and VIN2) and one output
(VOUT). Here the set of inverter used in eAND2 consist of
INV14 and INV22.
Fig.5, Schematic of eAND2 gate
d) EXTENDED AND3 (eAND3) GATE:
Fig.6 shows the schematic of eAND3 gate. The input
voltages VIN1 and VIN2 are fed to two inverters INV22 and
INV22, respectively. The inverters will then identify the unique
quaternary digit 3q and the binary logic NOR gate will do the
binary operations and internally it interconnects the output of
the gate with the ref voltages either VR0 or VR3. Since the
value of the voltage for 0q and 3q are equivalent to 0b and 1b,
respectively, this implementation is possible.
Fig.6, Schematic of eAND3 gate
e) MAXIMUM (MAX) GATE:
Fig.7 shows the schematic of MAX gate. It has two inputs
(VIN1 and VIN2) and one output (VOUT) which can take any
quaternary digit values (0q, 1q, 2q or 3q) according to the input.
As shown in Fig.7, a voltage to current converter is used to
convert input voltage signals into current signals and its output
is fed to a current comparator in order to perform the
comparison in current mode to determine the input having
highest value. Then two switches MN1 and MP3 are used to
connect the output to the highest input value which is
controlled by the signals E and Eb.
Fig.7, Schematic of MAX gate

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Vol. 1, Issue. 4, June 2015 ISSN (Online): 2349-8218
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V. SIMULATION RESULTS OF MVL GATES:
The simulation of proposed universal set of MVL gates is
done using Cadance software. Fig. 8-12 shows the simulation
results of universal set of gates (SUC, eAND1, eAND2,
eAND3, MAX).
Fig.8, Transient response of SUC gate
Fig.9 Transient response of eAND1 gate
Fig.10, Transient response of eAND2 gate
Fig.11, Transient response of eAND3 gate
Fig.12, Transient response of MAX gate
For all the possible combination of input values it shows
the corresponding output values or in other words shows the
timing results for the proposed gates. Thus the correct
functionality of the implemented universal set of MVL gates
can be analysed by comparing the simulation results with the
truth table shown in Table 1-3.
VI. CONCLUSION AND FUTURE WORK
In this paper an alternative method and algebra is
proposed to design and synthesize multiple valued operators
for designing digital circuit based on multi valued logic
instead of binary logic. Five new gates SUC, eAND1, eAND2,
eAND3 and MAX have been defined which can be used to
design and implement any Multi Valued Logic digital circuit.
The paper presented utilizes the knowledge coming from the
binary logic digital circuit and extends it for the synthesis of
digital circuit based on MV Logic. The results obtained by
analysing the transient response of these MVL gates clearly
shows the correct functionality of these multi valued logic
gates and thus also shows the possibility of designing any
sequential and combinational digital circuit based on multiple
value concept. Future work will be done to show the
implementation of these MVL based sequential and
combinational circuit and also to improve the characteristics of
these gates like fan in, fan out, delay etc.
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