Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
A Low power and area efficient CLA adder design using Full swing GDI techniqueIJERA Editor
The low power VLSI design has an important role in designing of many electronic systems. While designing
any combinational or sequential circuits, the important parameters like power consumption, implementation
area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient
data path logic systems forms the largest areas of research in VLSI system design. This paper presents
a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed
CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard
CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical
limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections.
These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing
restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and
Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results
have shown a greater reduction in delay, power dissipation and area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
A Low power and area efficient CLA adder design using Full swing GDI techniqueIJERA Editor
The low power VLSI design has an important role in designing of many electronic systems. While designing
any combinational or sequential circuits, the important parameters like power consumption, implementation
area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient
data path logic systems forms the largest areas of research in VLSI system design. This paper presents
a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed
CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard
CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical
limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections.
These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing
restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and
Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results
have shown a greater reduction in delay, power dissipation and area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
In modern digital VLSI design, digital signal processors (DSP) and data processing application-specific integrated circuits(ASIC), comparators are important design element and arithmetic components . In this paper, a 2-bit magnitude comparator has been developed in three different style based on full adder module which is designed to provide good performance. The performance of these three different styles of comparator has been compared in terms of area and power consumption which are the important parameters that are considered while designing any digital circuit. The schematic are designed and simulated for its behavior using DSCH-3.1.The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3.1 to analyze the performance of three different styles at 45nm and 90 nm CMOS technology.
Delay Optimization of Low Power Reversible Gate using MOS Transistor Level de...IJERA Editor
In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base
application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the
power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI
circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using
the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce
energy loss due to the information bits lost during the operation information loss occurs because the total number
of output signals generated is less than total number of input signals applied. In reversible if the input vector can
be uniquely recovered from the output vector and if there is a one to one correspondence between its input and
output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS
transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future
in design of low power consumption circuits and high speed application.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Area-Delay Efficient Binary Adders in QCAIJERA Editor
In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that decrease the number
of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new
algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder
designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders,
with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the
RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the
number of clock cycles required for completing the explanation was limited. As transistors reduce in size more
and more of them can be accommodated in a single die, thus increasing chip computational capabilities.
However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata
approach represents one of the possible solutions in overcome this physical limit, even though the design of
logic modules in QCA is not forever straightforward.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and power delay product. We designed each of these techniques by using Spice simulation soft wares.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
In modern digital VLSI design, digital signal processors (DSP) and data processing application-specific integrated circuits(ASIC), comparators are important design element and arithmetic components . In this paper, a 2-bit magnitude comparator has been developed in three different style based on full adder module which is designed to provide good performance. The performance of these three different styles of comparator has been compared in terms of area and power consumption which are the important parameters that are considered while designing any digital circuit. The schematic are designed and simulated for its behavior using DSCH-3.1.The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3.1 to analyze the performance of three different styles at 45nm and 90 nm CMOS technology.
Delay Optimization of Low Power Reversible Gate using MOS Transistor Level de...IJERA Editor
In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base
application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the
power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI
circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using
the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce
energy loss due to the information bits lost during the operation information loss occurs because the total number
of output signals generated is less than total number of input signals applied. In reversible if the input vector can
be uniquely recovered from the output vector and if there is a one to one correspondence between its input and
output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS
transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future
in design of low power consumption circuits and high speed application.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Area-Delay Efficient Binary Adders in QCAIJERA Editor
In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that decrease the number
of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new
algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder
designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders,
with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the
RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the
number of clock cycles required for completing the explanation was limited. As transistors reduce in size more
and more of them can be accommodated in a single die, thus increasing chip computational capabilities.
However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata
approach represents one of the possible solutions in overcome this physical limit, even though the design of
logic modules in QCA is not forever straightforward.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and power delay product. We designed each of these techniques by using Spice simulation soft wares.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Area and Power Efficient Up-Down counter Design by Using Full Adder ModuleIJEEE
In this paper an area and power efficient 98T Up- Down counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.
Study on self resetting logic with gate diffusion input (SRL-GDI)shubham jha
With continual technology scaling and improvements in lithography, the integrated system has become faster and thus it is employed in diverse real-time applications. To support high performance applications, proper choice of technology selection and topology for implementing various logic are the mandatory issues in designing low- power devices.
Self Resetting Logic with Gate Diffusion Input (SRLGDI) is the successor of SRCMOS where the CMOS block is replaced with the GDI block hence the name SRLGDI, which is an asynchronous dynamic circuit. This logic family resolves the issues in dynamic circuits like charge sharing , charge leakage , short circuit power dissipation, monotonicity requirement and low output voltage.
In this design the pull down tree is implemented with gate diffusion input (GDI) with level restoration which apparently eliminates the conductance overlap between nMOS and pMOS devices , thereby reducing the short circuit power dissipation and providing high output voltage.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Layout Design of Low Power Half Adder using 90nm Technology IJEEE
The basic building block of any digital operation is addition. This paper compares fully automatic and proposed semicustom layout design; the proposed design has been optimized for power consumption, low area and high speed. Power consumption and area are the major design issue for a designer. All the design result of fully custom and proposed semicustom design taken at 1.2V. In this the circuit simulation has been done on DSCH3 and layout simulation on Microwind3.1.
LOW POWER-AREA GDI & PTL TECHNIQUES BASED FULL ADDER DESIGNScscpconf
Full adder circuit is functional building block of micro processors, digital signal processors or any ALUs. In this paper leakage power is reduced by using less number of transistors with the techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors ( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs. The entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
Low power area gdi & ptl techniques based full adder designscsandit
Full adder circuit is functional building block of micro processors, digital signal processors or
any ALUs. In this paper leakage power is reduced by using less number of transistors with the
techniques like GDI (Gate Diffusion Input) and PTL (Pass Transistor Logic) techniques. In this
paper 3 designs have been proposed of low power 1 bit full adder circuit with 10Transistors
( using PTL multiplexer) , 8 Transistor
(by using NMOS and PMOS PTL devices), 12Transistors (6Transistors to generate carry using
GDI technique and 6Transistors to generate sum using tri state inverters).
These circuits consume less power with maximum of 73% power saving com-pare to
conventional 28T design. The proposed circuit exploits the advantage of GDI technique and
pass transistor logic, and sum is generated by tri state inverter logic in all designs.
The entire simulations have been done on 180nm single n-well CMOS bulk technology, in
virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz.
https://technoelectronics44.blogspot.com/
GDI TECHNOLOGY, here you get GDI implementation and design of GDI based gates AND, OR, XOR, and Adders like CLA, CIA, CSKA, performance analysis of CMOS And GDI
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
2. GDI technique based full adder have advantages over full
adder using pass transistor logic or CMOS logic and is
categorized by tremendous speed and low power. The
technique has been described below.
A. Gate Diffusion Input (GDI)Technique
The GDI technique offers realization of extensive variety of
logic functions using simple two transistor based circuit
arrangement. This scheme is appropriate for fast and low-
power circuit design, which reduces number of MOS
transistors as compared to CMOS and other existing low power
techniques, while the logic level swing and static power
dissipation improves. It also allows easy top- down approach
by means of small cell library [5]. The basic cell of GDI is
shown in Fig. 2.
1) The GDI cell consists of one nMOS and one pMOS. The
structure looks like a CMOS inverter. Though in case of GDI
both the sources and corresponding substrate terminals of
transistors are not connected with supply and it can be
randomly biased.
2) It has three input terminals: G (nMOS and pMOS shorted
gate input), P (pMOS source input), and N (nMOS source
input). The output is taken from D (nMOS and pMOS shorted
drain terminal) [11].
Fig 2 GDI basic cell consisting of pMOS and nMOS
GDI logic style approach consumes less silicon area compared
to other logic styles as it consists of less transistor count. In
view of the fact that, the area is less, the value of node
capacitances will be less and for this reason GDI gates have
faster operation which presents that GDI logic style is a power
efficient method of design.
We can realize different Boolean functions with GDI basic cell.
Table I shows how different Boolean functions can be realized
by using different input arrangements of the GDI cell.
TABLE I. GDI CELL BASED VARIOUS LOGIC FUNCTIONS USING DIFFERENT
INPUT CONFIGURATIONS AND CORRESPONDING TRANSISTOR COUNTS
III. ARCHITECTURE OF PROPOSED GDI FULL ADDER
The basic architecture of the 2:1 MUX using GDI method
is shown in fig. 3. In this configuration we have connected
PMOS and NMOS gate along with a SEL line ‘A’, as in
MUX. As we know that PMOS works on ACTIVE LOW and
NMOS works on ACTIVE HIGH. So, when the SELECT
input is low (0) then the PMOS get activated, and show the
input ‘B’ in the output and due to low input (0) the NMOS
stands idle, as it is activated in high input.
Fig.3 Basic view of 2T MUX using GDI technique
Same for the case, while the G input is high (1) then the
NMOS get activated, and show the input ‘C’ at the output.
Thus this circuitry behaves as a 2-input MUX using ‘A’ as
SEL line, and shows the favorable output as 2:1MUX.
Fig.4 Block Diagram of Low Power Proposed Full Adder using 2T MUX
Now we are implementing the low power full adder circuit
with the help of 2T MUX, made by GDI technique. It require
total 6 numbers of 2T MUX having same characteristics to
design a 12T full adder and connected as above in fig.4 [5].
The truth table for the above circuit taking each MUX as
consideration are shown table II, and from there it generates 6
various outputs of various MUX.
N P G OUTPUT FUNCTION
TRANSISTOR
COUNT
0 1 A A’ Inverter 2
0 B A A’B F1 2
B 1 A A’+B F2 2
1 B A A+B OR 2
B 0 A AB AND 2
C B A A’B+AC MUX 2
B’ B A A’B+B’A XOR 4
B B’ A AB+A’B’ XNOR 4
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3. TABLE II.TRUTH TABLE OF LOW POWER FULL ADDER USING 2T MUX
IV. LOGIC ANALYSIS
The digital circuit shown in the fig. 4 can be analyzed
logically with the help of simple Boolean algebra. The outputs
of each MUX can be analyzed to get the sum & carry.
Logic transition, short-circuit current and leakage current
are the three main sources of power dissipation in CMOS
VLSI circuits [6], [7]. During the transition of output from one
logic level to other both the NMOS and PMOS transistors
become active and provides a short circuit path directly
between supply to ground which increases the power
consumption of the circuit [2], [6]. As the proposed 12-T full
adder is made of GDI based MUX , it does not provide direct
connections between supply and ground, so the probability of
a getting short circuit current during switching can be
considerably reduced; i.e, the power consumption due to short
circuit current is considerably small. Again, in the proposed
12T full adder, all the select line of the MUX i.e. the G nodes
of the GDI cells are directly connected with the input signals,
results a much faster transition (less delay) in its output
signals. As a result, the power consumption of the final pad
out stage is low and it can provide faster Sum and Cout
outputs.
V. SIMULATION
The platform of simulator generally provides outputs on
behalf of certain input characteristics or behaviors of a
selected object or abstract system. Simulation can be used to
get or verify the behavioral and timing analysis of the circuit
models. Here conventional FA & proposed 12-T full adder
circuits are analyzed in standard simulator using 250 nm
technologies. We implement the conventional full adder using
28T (transistor) & simulate out its power consumption &
timing delays. Then we again design & simulate out the low
power full adder using the concept of GDI logic & thereby
implementing the design with 2-T MUX. First 2T GDI MUX
and then the conventional and proposed circuits are simulated
in schematic editor by providing various input logic
combinations shown in table III.
TABLE III. INPUT SPECIFICATIONS FOR 250NM TECHNOLOGY SIMULATION
Fig 5 Test circuit schematic of 2-T GDI based 2:1MUX
In fig. 5 the MUX is based on GDI technique as shown in fig.
2. The select line input is ‘A_SEL_line’ and the data inputs
are ‘IN0_B’ and ‘IN1_C’. Before simulating GDI full adder
the 2-T MUX is tested with standard bit combinations as
shown in fig. 5. The select line input bit pattern is ‘01010101’.
Similarly the data input bit patterns are ‘00110011’ and
‘00001111’ respectively. The test circuit is simulated for 80ns
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4. with an on/off bit time of 10ns. The input and output
responses are shown in fig. 6,
Fig. 6. 2T GDI based 2:1 MUX transient response.
The schematic diagrams of conventional 28-T FA and
proposed 12-T FA are shown in fig. 7 & 8 respectively.
Fig 7. Schematic diagram of conventional 28-T full adder
Fig. 8. Schematic diagram of proposed 8-T full adder
VI. SIMULATION RESULTS & ANALYSIS
The schematics shown in fig. 7 & fig.8 are simulated with
the help of standard simulator tool to get the timing, power
analysis. The transient responses of these schematics are
shown below in fig.9 & fig. 10.
Fig. 9 Transient response of conventional 28-T FA
Fig. 10 Transient response of proposed 12-T FA
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5. From the fig. 9 and fig.10 it can be easily understood that
the proposed 12-T full adder is having the same transient
response as like the conventional 28-T FA. The power &
timing analysis is tabulated in the table below,
TABLE IV. COMPARISN BETWEEN CONVENTIONAL & PROPOSED FA
28-T CMOS
CONVENTIONAL
FULL ADDER
12-T PROPOSED
FULL ADDER
Power
Analysis
Avg. Power 150.2901 mw 78.180 mw
Max Power 354.6744 mw 210.5247 mw
Min Power 0.0228 mw 0.0101 mw
Transient
Delay
Analysis
Rise time delay 0.85 ns 0.25 ps
Fall time delay: 1.34 ns 0.72 ps
Avg. time delay 1.09 ns 0.48 ps
Table IV shows that our proposed full adder gives 48%
improvement in avg. power consumption with respect to
conventional full adder as well as 95% improvement in
transient delay analysis.
Regarding area consideration it can be easily understood that
this proposed 12-T FA core will be of much lower size
compared to conventional 28-T FA. The estimate of area of
the core can be carried out by such a manner,
MOS Transistor area: L=0.25um, W=2.5um
Channel area: L x W
Area of Source: 5L x W
Area of Drain: 5L x W
MOS Transistor area: (L.W)+2(5L.W)=30.25 sq.um
-
Total area: No of MOS transistor x MOS transistor area+30%
extra area due to interconnection
Fig. 11. Core layout of 12-T proposed FA using lambda rule.
Fig. 11 shows the core area layout of proposed full adder
using 12 transistors using lambda rule. The layout summary is
as follows,
Core size in Lambda : 97.00 x 238.00
Core area (Lambda^2) : 23086.00
Frame size in Lambda : 3862.00 x 3862.00
Frame area (Lambda^2) : 14915044.00
The conventional 28T FA core area is equal to 28*
30.25sq.um+30% of area or 1101sq. um & 12 T FA core area
is equal to 12* 30.25sq.um+30% of area or 1101sq. um or 472
sq um. As the transistor size taken for both the conventional
and proposed FA is same therefore it can be easily understood
that proposed 12T transistor FA will have less area with
respect to 28T full adder.
Fig. 12 & 13 shows the power consumption of the 28 T & 12
T FA respectively,
Fig. 12 Power consumption of conventional 28-T FA
Fig. 13. Power consumption of proposed 12-T FA
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6. VII. CONCLUSION
From the above results it can be concluded that our proposed
full adder has got better performance in delay, power and area
consideration in comparison with conventional full adder. It
shows that in contrast to other conventional techniques, this
approach is better and it will be more appropriate for industrial
practice in complex process technologies.
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