This document discusses high speed multiplier architectures for digital signal processing applications. It begins by introducing the importance of fast multiplication in DSP algorithms. It then describes the Vedic multiplication algorithm and how it can be implemented for 4-bit and 8-bit numbers using the Urdhva Tiryakbhyam technique. Next, it introduces the Booth encoding technique for radix-8 multiplication and discusses how it reduces the number of partial products. Simulation results are shown comparing the Vedic and radix-8 multiplier architectures. The radix-8 multiplier is concluded to have better performance in terms of power, delay, and power-delay product, making it well-suited for DSP applications.