journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
I am Simon M. I am an Electrical Engineering exam Helper at liveexamhelper.com. I hold a Masters' Degree in Electrical Engineering from, University of Wisconsin, USA. I have been helping students with their exams for the past 10 years. You can hire me to take your exam in Electrical Engineering.
Visit liveexamhelper.com or email info@liveexamhelper.com.
You can also call on +1 678 648 4277 for any assistance with the Electrical Engineering exam.
I am Andrew O. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold a Ph.D. in Programming, Southampton, UK. I have been helping students with their homework for the past 10 years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
I am Simon M. I am an Electrical Engineering exam Helper at liveexamhelper.com. I hold a Masters' Degree in Electrical Engineering from, University of Wisconsin, USA. I have been helping students with their exams for the past 10 years. You can hire me to take your exam in Electrical Engineering.
Visit liveexamhelper.com or email info@liveexamhelper.com.
You can also call on +1 678 648 4277 for any assistance with the Electrical Engineering exam.
I am Andrew O. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold a Ph.D. in Programming, Southampton, UK. I have been helping students with their homework for the past 10 years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
I am Boris M. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold MSc. in Programming, McGill University, Canada. I have been helping students with their homework for the past 7 years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Us...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Low-Complexity Redundant Multiplier Architecture for Finite...ijcisjournal
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is
employed in applications like cryptography for data encryption and decryptionto deal with discrete
mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because
of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized
using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low
area and power when compared to the previous structures using the same representation.
I am Boris M. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold an MSc. in Programming, McGill University, Canada. I have been helping students with their homework for the past 8years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast ...Kumar Goud
Abstract— Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process; one of them is Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. In this paper Wallace tree construction is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. In this paper Wallace tree is constructed by traditional method and with the help of compressor techniques such as 4:2 compressor, 5:2 compressor, 6:2 compressor, 7:2 compressor. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity.
Index Terms—Component, formatting, style, styling, insert. (key words)
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
Modified approximate 8-point multiplier less DCT like transformIJERA Editor
Discrete Cosine Transform (DCT) is widely usedtransformation for compression in image and video standardslike H.264 or MPEGv4, JPEG etc. Currently the new standarddeveloped Codec is Highly Efficient Video Coding (HEVC) orH.265. With the help of the transformation matrix the computational cost can be dynamically reduce. This paper proposesa novel approach of multiplier-less modified approximate DCT like transformalgorithm and also comparison with exact DCT algorithm and theapproximate DCT like transform. This proposed algorithm willhave lower computational complexity. Furthermore, the proposedalgorithm will be modular in approach, and suitable for pipelinedVLSI implementation.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
I am Boris M. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold MSc. in Programming, McGill University, Canada. I have been helping students with their homework for the past 7 years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Us...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Low-Complexity Redundant Multiplier Architecture for Finite...ijcisjournal
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is
employed in applications like cryptography for data encryption and decryptionto deal with discrete
mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because
of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized
using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low
area and power when compared to the previous structures using the same representation.
I am Boris M. I am a Computer Science Assignment Help Expert at programminghomeworkhelp.com. I hold an MSc. in Programming, McGill University, Canada. I have been helping students with their homework for the past 8years. I solve assignments related to Computer Science.
Visit programminghomeworkhelp.com or email support@programminghomeworkhelp.com.You can also call on +1 678 648 4277 for any assistance with Computer Science assignments.
A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast ...Kumar Goud
Abstract— Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process; one of them is Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. In this paper Wallace tree construction is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. In this paper Wallace tree is constructed by traditional method and with the help of compressor techniques such as 4:2 compressor, 5:2 compressor, 6:2 compressor, 7:2 compressor. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity.
Index Terms—Component, formatting, style, styling, insert. (key words)
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
Modified approximate 8-point multiplier less DCT like transformIJERA Editor
Discrete Cosine Transform (DCT) is widely usedtransformation for compression in image and video standardslike H.264 or MPEGv4, JPEG etc. Currently the new standarddeveloped Codec is Highly Efficient Video Coding (HEVC) orH.265. With the help of the transformation matrix the computational cost can be dynamically reduce. This paper proposesa novel approach of multiplier-less modified approximate DCT like transformalgorithm and also comparison with exact DCT algorithm and theapproximate DCT like transform. This proposed algorithm willhave lower computational complexity. Furthermore, the proposedalgorithm will be modular in approach, and suitable for pipelinedVLSI implementation.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adders are one of the most widely digital
components in the digital integrated circuit design and are the
necessary part of Digital Signal Processing (DSP) applications.
With the advances in technology, researchers have tried and are
trying to design adders which offer either high speed, low power
consumption, less area or the combination of them. The addition
of the two bits is very Based on the various speed-up schemes for
binary addition, a comprehensive overview and a qualitative
evaluation of the different existing basic adder architectures are
given in this paper. In addition, their comparison is performed in
the thesis for the performance analysis. We will synthesize the
adders - Ripple Carry adder, Carry look- ahead Adder, Carry
Save Adder in ISE XIILINX 10.1 by using HDL - Verilog and
will simulate them in Modelsim 6.4a. We will Compare above
mentioned adders in terms of Delay, Slices Used and Look up
tables used by the adder architecture.
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
Abstract: Quaternary number system is a base-4 numeral system. Using Quaternary Signed Digit (QSD) number system may also execute carry free addition, borrow free subtraction and multiplication. The QSD number system wants a different group of prime modulo based logic elements for each arithmetic operation. In this work we extend this QSD addition to Delayed addition in place of carry free addition. Carry free addition generates intermediate carry and intermediate sum, in this carry propagation is required to generate intermediate sum. To reduce carry propagation we evaluated delayed addition. This delayed addition reduces carry propagation and improves arithmetic calculations. We present both QSD and Floating –point single precision addition using delayed addition. The design work is carried by using Verilog HDL in ISE.
Keywords: QSD, DA, CFA and Floating-Point.
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
Abstract: Quaternary number system is a base-4 numeral system. Using Quaternary Signed Digit (QSD) number system may also execute carry free addition, borrow free subtraction and multiplication. The QSD number system wants a different group of prime modulo based logic elements for each arithmetic operation. In this work we extend this QSD addition to Delayed addition in place of carry free addition. Carry free addition generates intermediate carry and intermediate sum, in this carry propagation is required to generate intermediate sum. To reduce carry propagation we evaluated delayed addition. This delayed addition reduces carry propagation and improves arithmetic calculations. We present both QSD and Floating –point single precision addition using delayed addition. The design work is carried by using Verilog HDL in ISE.
Keywords: QSD, DA, CFA and Floating-Point.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
A Novel Method for Prevention of Bandwidth Distributed Denial of Service AttacksIJERD Editor
Distributed Denial of Service (DDoS) Attacks became a massive threat to the Internet. Traditional
Architecture of internet is vulnerable to the attacks like DDoS. Attacker primarily acquire his army of Zombies,
then that army will be instructed by the Attacker that when to start an attack and on whom the attack should be
done. In this paper, different techniques which are used to perform DDoS Attacks, Tools that were used to
perform Attacks and Countermeasures in order to detect the attackers and eliminate the Bandwidth Distributed
Denial of Service attacks (B-DDoS) are reviewed. DDoS Attacks were done by using various Flooding
techniques which are used in DDoS attack.
The main purpose of this paper is to design an architecture which can reduce the Bandwidth
Distributed Denial of service Attack and make the victim site or server available for the normal users by
eliminating the zombie machines. Our Primary focus of this paper is to dispute how normal machines are
turning into zombies (Bots), how attack is been initiated, DDoS attack procedure and how an organization can
save their server from being a DDoS victim. In order to present this we implemented a simulated environment
with Cisco switches, Routers, Firewall, some virtual machines and some Attack tools to display a real DDoS
attack. By using Time scheduling, Resource Limiting, System log, Access Control List and some Modular
policy Framework we stopped the attack and identified the Attacker (Bot) machines
Hearing loss is one of the most common human impairments. It is estimated that by year 2015 more
than 700 million people will suffer mild deafness. Most can be helped by hearing aid devices depending on the
severity of their hearing loss. This paper describes the implementation and characterization details of a dual
channel transmitter front end (TFE) for digital hearing aid (DHA) applications that use novel micro
electromechanical- systems (MEMS) audio transducers and ultra-low power-scalable analog-to-digital
converters (ADCs), which enable a very-low form factor, energy-efficient implementation for next-generation
DHA. The contribution of the design is the implementation of the dual channel MEMS microphones and powerscalable
ADC system.
Influence of tensile behaviour of slab on the structural Behaviour of shear c...IJERD Editor
-A composite beam is composed of a steel beam and a slab connected by means of shear connectors
like studs installed on the top flange of the steel beam to form a structure behaving monolithically. This study
analyzes the effects of the tensile behavior of the slab on the structural behavior of the shear connection like slip
stiffness and maximum shear force in composite beams subjected to hogging moment. The results show that the
shear studs located in the crack-concentration zones due to large hogging moments sustain significantly smaller
shear force and slip stiffness than the other zones. Moreover, the reduction of the slip stiffness in the shear
connection appears also to be closely related to the change in the tensile strain of rebar according to the increase
of the load. Further experimental and analytical studies shall be conducted considering variables such as the
reinforcement ratio and the arrangement of shear connectors to achieve efficient design of the shear connection
in composite beams subjected to hogging moment.
Gold prospecting using Remote Sensing ‘A case study of Sudan’IJERD Editor
Gold has been extracted from northeast Africa for more than 5000 years, and this may be the first
place where the metal was extracted. The Arabian-Nubian Shield (ANS) is an exposure of Precambrian
crystalline rocks on the flanks of the Red Sea. The crystalline rocks are mostly Neoproterozoic in age. ANS
includes the nations of Israel, Jordan. Egypt, Saudi Arabia, Sudan, Eritrea, Ethiopia, Yemen, and Somalia.
Arabian Nubian Shield Consists of juvenile continental crest that formed between 900 550 Ma, when intra
oceanic arc welded together along ophiolite decorated arc. Primary Au mineralization probably developed in
association with the growth of intra oceanic arc and evolution of back arc. Multiple episodes of deformation
have obscured the primary metallogenic setting, but at least some of the deposits preserve evidence that they
originate as sea floor massive sulphide deposits.
The Red Sea Hills Region is a vast span of rugged, harsh and inhospitable sector of the Earth with
inimical moon-like terrain, nevertheless since ancient times it is famed to be an abode of gold and was a major
source of wealth for the Pharaohs of ancient Egypt. The Pharaohs old workings have been periodically
rediscovered through time. Recent endeavours by the Geological Research Authority of Sudan led to the
discovery of a score of occurrences with gold and massive sulphide mineralizations. In the nineties of the
previous century the Geological Research Authority of Sudan (GRAS) in cooperation with BRGM utilized
satellite data of Landsat TM using spectral ratio technique to map possible mineralized zones in the Red Sea
Hills of Sudan. The outcome of the study mapped a gossan type gold mineralization. Band ratio technique was
applied to Arbaat area and a signature of alteration zone was detected. The alteration zones are commonly
associated with mineralization. The alteration zones are commonly associated with mineralization. A filed check
confirmed the existence of stock work of gold bearing quartz in the alteration zone. Another type of gold
mineralization that was discovered using remote sensing is the gold associated with metachert in the Atmur
Desert.
Reducing Corrosion Rate by Welding DesignIJERD Editor
The paper addresses the importance of welding design to prevent corrosion at steel. Welding is
used to join pipe, profiles at bridges, spindle, and a lot more part of engineering construction. The
problems happened associated with welding are common issues in these fields, especially corrosion.
Corrosion can be reduced with many methods, they are painting, controlling humidity, and also good
welding design. In the research, it can be found that reducing residual stress on the welding can be
solved in corrosion rate reduction problem.
Preheating on 500oC and 600oC give better condition to reduce corosion rate than condition after
preheating 400oC. For all welding groove type, material with 500oC and 600oC preheating after 14 days
corrosion test is 0,5%-0,69% lost. Material with 400oC preheating after 14 days corrosion test is 0,57%-0,76%
lost.
Welding groove also influence corrosion rate. X and V type welding groove give better condition to reduce
corrosion rate than use 1/2V and 1/2 X welding groove. After 14 days corrosion test, the samples with
X welding groove type is 0,5%-0,57% lost. The samples with V welding groove after 14 days corrosion test is
0,51%-0,59% lost. The samples with 1/2V and 1/2X welding groove after 14 days corrosion test is 0,58%-
0,71% lost.
Router 1X3 – RTL Design and VerificationIJERD Editor
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks (as opposed to a network switch, which connects data lines from one single network). This paper,
mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of
router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top
module.
Active Power Exchange in Distributed Power-Flow Controller (DPFC) At Third Ha...IJERD Editor
This paper presents a component within the flexible ac-transmission system (FACTS) family, called
distributed power-flow controller (DPFC). The DPFC is derived from the unified power-flow controller (UPFC)
with an eliminated common dc link. The DPFC has the same control capabilities as the UPFC, which comprise
the adjustment of the line impedance, the transmission angle, and the bus voltage. The active power exchange
between the shunt and series converters, which is through the common dc link in the UPFC, is now through the
transmission lines at the third-harmonic frequency. DPFC multiple small-size single-phase converters which
reduces the cost of equipment, no voltage isolation between phases, increases redundancy and there by
reliability increases. The principle and analysis of the DPFC are presented in this paper and the corresponding
simulation results that are carried out on a scaled prototype are also shown.
Mitigation of Voltage Sag/Swell with Fuzzy Control Reduced Rating DVRIJERD Editor
Power quality has been an issue that is becoming increasingly pivotal in industrial electricity
consumers point of view in recent times. Modern industries employ Sensitive power electronic equipments,
control devices and non-linear loads as part of automated processes to increase energy efficiency and
productivity. Voltage disturbances are the most common power quality problem due to this the use of a large
numbers of sophisticated and sensitive electronic equipment in industrial systems is increased. This paper
discusses the design and simulation of dynamic voltage restorer for improvement of power quality and
reduce the harmonics distortion of sensitive loads. Power quality problem is occurring at non-standard
voltage, current and frequency. Electronic devices are very sensitive loads. In power system voltage sag,
swell, flicker and harmonics are some of the problem to the sensitive load. The compensation capability
of a DVR depends primarily on the maximum voltage injection ability and the amount of stored
energy available within the restorer. This device is connected in series with the distribution feeder at
medium voltage. A fuzzy logic control is used to produce the gate pulses for control circuit of DVR and the
circuit is simulated by using MATLAB/SIMULINK software.
Study on the Fused Deposition Modelling In Additive ManufacturingIJERD Editor
Additive manufacturing process, also popularly known as 3-D printing, is a process where a product
is created in a succession of layers. It is based on a novel materials incremental manufacturing philosophy.
Unlike conventional manufacturing processes where material is removed from a given work price to derive the
final shape of a product, 3-D printing develops the product from scratch thus obviating the necessity to cut away
materials. This prevents wastage of raw materials. Commonly used raw materials for the process are ABS
plastic, PLA and nylon. Recently the use of gold, bronze and wood has also been implemented. The complexity
factor of this process is 0% as in any object of any shape and size can be manufactured.
Spyware triggering system by particular string valueIJERD Editor
This computer programme can be used for good and bad purpose in hacking or in any general
purpose. We can say it is next step for hacking techniques such as keylogger and spyware. Once in this system if
user or hacker store particular string as a input after that software continually compare typing activity of user
with that stored string and if it is match then launch spyware programme.
A Blind Steganalysis on JPEG Gray Level Image Based on Statistical Features a...IJERD Editor
This paper presents a blind steganalysis technique to effectively attack the JPEG steganographic
schemes i.e. Jsteg, F5, Outguess and DWT Based. The proposed method exploits the correlations between
block-DCTcoefficients from intra-block and inter-block relation and the statistical moments of characteristic
functions of the test image is selected as features. The features are extracted from the BDCT JPEG 2-array.
Support Vector Machine with cross-validation is implemented for the classification.The proposed scheme gives
improved outcome in attacking.
Secure Image Transmission for Cloud Storage System Using Hybrid SchemeIJERD Editor
- Data over the cloud is transferred or transmitted between servers and users. Privacy of that
data is very important as it belongs to personal information. If data get hacked by the hacker, can be
used to defame a person’s social data. Sometimes delay are held during data transmission. i.e. Mobile
communication, bandwidth is low. Hence compression algorithms are proposed for fast and efficient
transmission, encryption is used for security purposes and blurring is used by providing additional
layers of security. These algorithms are hybridized for having a robust and efficient security and
transmission over cloud storage system.
Application of Buckley-Leverett Equation in Modeling the Radius of Invasion i...IJERD Editor
A thorough review of existing literature indicates that the Buckley-Leverett equation only analyzes
waterflood practices directly without any adjustments on real reservoir scenarios. By doing so, quite a number
of errors are introduced into these analyses. Also, for most waterflood scenarios, a radial investigation is more
appropriate than a simplified linear system. This study investigates the adoption of the Buckley-Leverett
equation to estimate the radius invasion of the displacing fluid during waterflooding. The model is also adopted
for a Microbial flood and a comparative analysis is conducted for both waterflooding and microbial flooding.
Results shown from the analysis doesn’t only records a success in determining the radial distance of the leading
edge of water during the flooding process, but also gives a clearer understanding of the applicability of
microbes to enhance oil production through in-situ production of bio-products like bio surfactans, biogenic
gases, bio acids etc.
Gesture Gaming on the World Wide Web Using an Ordinary Web CameraIJERD Editor
- Gesture gaming is a method by which users having a laptop/pc/x-box play games using natural or
bodily gestures. This paper presents a way of playing free flash games on the internet using an ordinary webcam
with the help of open source technologies. Emphasis in human activity recognition is given on the pose
estimation and the consistency in the pose of the player. These are estimated with the help of an ordinary web
camera having different resolutions from VGA to 20mps. Our work involved giving a 10 second documentary to
the user on how to play a particular game using gestures and what are the various kinds of gestures that can be
performed in front of the system. The initial inputs of the RGB values for the gesture component is obtained by
instructing the user to place his component in a red box in about 10 seconds after the short documentary before
the game is finished. Later the system opens the concerned game on the internet on popular flash game sites like
miniclip, games arcade, GameStop etc and loads the game clicking at various places and brings the state to a
place where the user is to perform only gestures to start playing the game. At any point of time the user can call
off the game by hitting the esc key and the program will release all of the controls and return to the desktop. It
was noted that the results obtained using an ordinary webcam matched that of the Kinect and the users could
relive the gaming experience of the free flash games on the net. Therefore effective in game advertising could
also be achieved thus resulting in a disruptive growth to the advertising firms.
Hardware Analysis of Resonant Frequency Converter Using Isolated Circuits And...IJERD Editor
-LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region[5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Amateurs Radio operator, also known as HAM communicates with other HAMs through Radio
waves. Wireless communication in which Moon is used as natural satellite is called Moon-bounce or EME
(Earth -Moon-Earth) technique. Long distance communication (DXing) using Very High Frequency (VHF)
operated amateur HAM radio was difficult. Even with the modest setup having good transceiver, power
amplifier and high gain antenna with high directivity, VHF DXing is possible. Generally 2X11 YAGI antenna
along with rotor to set horizontal and vertical angle is used. Moon tracking software gives exact location,
visibility of Moon at both the stations and other vital data to acquire real time position of moon.
“MS-Extractor: An Innovative Approach to Extract Microsatellites on „Y‟ Chrom...IJERD Editor
Simple Sequence Repeats (SSR), also known as Microsatellites, have been extensively used as
molecular markers due to their abundance and high degree of polymorphism. The nucleotide sequences of
polymorphic forms of the same gene should be 99.9% identical. So, Microsatellites extraction from the Gene is
crucial. However, Microsatellites repeat count is compared, if they differ largely, he has some disorder. The Y
chromosome likely contains 50 to 60 genes that provide instructions for making proteins. Because only males
have the Y chromosome, the genes on this chromosome tend to be involved in male sex determination and
development. Several Microsatellite Extractors exist and they fail to extract microsatellites on large data sets of
giga bytes and tera bytes in size. The proposed tool “MS-Extractor: An Innovative Approach to extract
Microsatellites on „Y‟ Chromosome” can extract both Perfect as well as Imperfect Microsatellites from large
data sets of human genome „Y‟. The proposed system uses string matching with sliding window approach to
locate Microsatellites and extracts them.
Importance of Measurements in Smart GridIJERD Editor
- The need to get reliable supply, independence from fossil fuels, and capability to provide clean
energy at a fixed and lower cost, the existing power grid structure is transforming into Smart Grid. The
development of a smart energy distribution grid is a current goal of many nations. A Smart Grid should have
new capabilities such as self-healing, high reliability, energy management, and real-time pricing. This new era
of smart future grid will lead to major changes in existing technologies at generation, transmission and
distribution levels. The incorporation of renewable energy resources and distribution generators in the existing
grid will increase the complexity, optimization problems and instability of the system. This will lead to a
paradigm shift in the instrumentation and control requirements for Smart Grids for high quality, stable and
reliable electricity supply of power. The monitoring of the grid system state and stability relies on the
availability of reliable measurement of data. In this paper the measurement areas that highlight new
measurement challenges, development of the Smart Meters and the critical parameters of electric energy to be
monitored for improving the reliability of power systems has been discussed.
Study of Macro level Properties of SCC using GGBS and Lime stone powderIJERD Editor
One of the major environmental concerns is the disposal of the waste materials and utilization of
industrial by products. Lime stone quarries will produce millions of tons waste dust powder every year. Having
considerable high degree of fineness in comparision to cement this material may be utilized as a partial
replacement to cement. For this purpose an experiment is conducted to investigate the possibility of using lime
stone powder in the production of SCC with combined use GGBS and how it affects the fresh and mechanical
properties of SCC. First SCC is made by replacing cement with GGBS in percentages like 10, 20, 30, 40, 50 and
by taking the optimum mix with GGBS lime stone powder is blended to mix in percentages like 5, 10, 15, 20 as
a partial replacement to cement. Test results shows that the SCC mix with combination of 30% GGBS and 15%
limestone powder gives maximum compressive strength and fresh properties are also in the limits prescribed by
the EFNARC.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
International Journal of Engineering Research and Development (IJERD)
1. International Journal of Engineering Research and Development
e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.com
Volume 8, Issue 6 (September 2013), PP.23-28
www.ijerd.com 23 | Page
Design and Implementation of Vedic Multiplier
C.Sheshavali M.Tech1
, K.Niranjan kumar Asst.professor2
1,2
Department of ECE, PBR VITs, SPSR Nellore (district),
JNTUA, Ananthapur, India.
Abstract:- In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is
proposed. This multiplier's architecture is similar to that of a Constant Coefficient Multiplier (KCM). However,
for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed
multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava Multiplier for
both 8 bit and 16 bit cases and the results are presented. The proposed multiplier is 1.5 times faster than the
other multipliers for 16x16 case and consumes only 76% area for 8x8 multiplier and 42% area for 16x16
multiplier.
Keywords:- KCM; Urdhava; Vedic Maths; Array Multiplier; FPGA.
I. INTRODUCTION
Multiplication is one of the more silicon-intensive functions, especially when implemented in
Programmable Logic. Multipliers are key components of many high performance systems such as FIR filters,
Microprocessors, Digital Signal Processors, etc. A system's performance is generally determined by the
performance of the multiplier, because the multiplier is generally the slowest element in the system.
Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a
major design issue.
Vedic mathematics [I] is the ancient Indian system of mathematics which mainly deals with Vedic
mathematical formulae and their application to various branches of mathematics. The word 'Vedic' is derived
from the word 'Veda' which means the store-house of all knowledge. Vedic mathematics was reconstructed from
the ancient Indian scriptures (Vedas) by Sri Bharati Krshna Tirthaji (1884-1960), after his eight years of
research on Vedas [1]. According to his research, Vedic mathematics is mainly based on sixteen principles or
word-formulae which are termed as Sutras. This is a very interesting field and presents some effective
algorithms which can be applied to various branches of Engineering such as Computing and Digital Signal
Processing.
II. ARRAY MULTIPLIER
In Array multiplier [2], AND gates are used for generation of the bit-products and adders for
accumulation of generated bit products. All bit-products are generated in parallel and collected through an array
of full adders or any other type of adders. Since the array multiplier is having a regular structure, wiring and the
layout are done in a much simplified manner. Therefore, among other multiplier structures, array multiplier
takes up the least amount of area. But it is also the slowest with the latency proportional to O (Wct), where Wd
is the word length of the operand. Example I describes the multiplication process using array multiplier and Fig.l
depicts the structure of the same. Instead of Ripple Carry Adder (RCA), here Carry Save Adder (CSA) is used
for adding each group of partial product terms, because RCA is the slowest adder among all other types of
adders available. In case of multiplier with CSA [5], partial product addition is carried out in Carry save form
and RCA is used only in final addition.
Example 1: (1101 x 1110) = 1 0 1 1 0 1 1 0
1 1 0 1
1 1 1 0 X
-----------------------------------
0 0 0 0
1 1 0 1 --- Left Shift by I bit
1 1 0 1 --- Left Shift by 2 bit
1 1 0 1 --- Left Shift by 3 bit
-----------------------------------------
1 0 1 1 0 1 1 0
2. Design and Implementation of Vedic Multiplier
www.ijerd.com 24 | Page
Here from the above example it is inferred that partial products are generated sequentially, which
reduces the speed of the multiplier. However the structure of the multiplier is regular.
Fig. 1: Array Multiplier using CSA Hardware Architecture
III. URDHAVA MULTIPLIER
Urdhava Tiryakbhyam [1] [3] (Vertically and Crosswise), is one of Sixteen Vedic Sutras and deals with
the multiplication of numbers. The sutra is illustrated in Example 2 and the hardware architecture is depicted in
Fig.3. In this example two decimal numbers (31 x 35) are multiplied. Line diagram for the multiplication of two,
three and four digit numbers is shown in Fig. 2 using Urdhava Method. The digits on the two ends of the line are
multiplied and the result is added with the previous carry. When three or more lines are present, all the results
are added to the previous carry. The least significant digit of the number thus obtained acts as one of the result
digit and the rest act as the carry for the next step. Initially the carry is taken to be zero.
Example 2: 40x45 =1800
4 0 0 4 0 4
4 5X 5 X 4 5 4X
-------- ---------------- -----------
0 20 + 0 = 20 16+2=18
-------- ---------------- -----------
Carry to next stage
Answer: 40x45 =1800
Fig. 2: Line Diagram for Urdhava Multiplication of 2, 3 and 4 digits
From the Example 2, it is observed that all the partial products are generated in parallel. So the speed of
the multiplier is higher compared to array multiplier.
The above discussions can now be extended to multiplication of binary number system with the
preliminary knowledge that the multiplication of two bits a0 and b0 is just an AND operation and can be
implemented using simple AND gate. To illustrate this multiplication scheme in binary number system, consider
the multiplication of two binary numbers a3a2ala0 and b3b2blb0. As the result of this multiplication would be more
than 4 bits, the product is expressed as r7r6r5r4r3r2rlr0. Least significant bit r0 is obtained by multiplying the
3. Design and Implementation of Vedic Multiplier
www.ijerd.com 25 | Page
least significant bits of the multiplicand and the multiplier as shown in the Fig.2. The digits on both sides of the
line are multiplied and added with the carry from the previous step. This generates one of the bits of the result
(r0) and a carry (Cn). This carry is added in the next step and thus the process goes on. If more than one line are
there in one step, all the results are added to the previous carry. In each step, least significant bit acts as the
result bit and the other entire bits act as carry.
For example, if in some intermediate step, we get 110, then 0 will act as result bit and 11 as the carry
(referred to as Cn in this text). It should be clearly noted that C n may be a multi-bit number. Thus the following
expressions (1) to (7) are derived:
r0 = a0b0 ... (1)
clrl = alb0 + aobl ... (2)
c2r2 = cl + a2b0 + alb1 + aob2 ... (3)
c3r3 = c2 + a3b0 + a2bl + alb2 + a0b3 ... (4)
c4r4 = c3 + a3bl + a2b2 + alb3 ... (5)
c5r5 = c4 + a3b2 + a2b3 ... (6)
c6r6 = c5 + a3b3 ... (7)
with c6r6r5r4r3r2r1rO being the final product. Partial products are calculated in parallel and hence the
delay involved is just the time it takes for the signal to propagate through the gates.
Fig.3 Urdhava Multiplier Hardware Architecture
The main advantage of the Vedic Multiplication algorithm (Urdhava Tiryakbhyam Sutra) stems from
the fact that it can be easily implemented in FPGA due to its simplicity and regularity [3]. The digital hardware
realization of a 4-bit multiplier using this Sutra is shown in Fig. 3. This hardware design is very similar to that of
the array multiplier where an array of adders is required to arrive at the final product. Here in Urdhava, all the
partial products are calculated in parallel and the delay associated is mainly the time taken by the carry to
propagate through the adders.
IV. PROPOSED METHOD
The proposed method is based on ROM approach however both the inputs for the multiplier can be
variables. In this proposed method a ROM is used for storing the squares of numbers as compared to KCM
where the multiples are stored. Method: To find (a x b), first we have to find whether the difference between 'a'
and 'b' is odd or even. Based on the difference, the product is calculated using (8) and (9).
I. In case of Even Difference
Result of Multiplication= [Average]2
- [Deviation]2
... (8)
II. In case of Odd Difference
Result of Multiplication = [Average x (Average + 1)]-[Deviation x (Deviation+ I)] ... (9)
Where, Average = [(a+b)/2] and Deviation = [Average - smallest (a, b)]
Example 3 (Even difference) and Example 4 (Odd difference) depict the multiplication process. Thus
the two variable multiplication is performed by averaging, squaring and subtraction. To find the average
4. Design and Implementation of Vedic Multiplier
www.ijerd.com 26 | Page
[(a+b)/2], which involves division by 2 is performed by right shifting the sum by one bit. If the squares of the
numbers are stored in a ROM, the result can be instantaneously calculated. However, in case of Odd difference,
the process is different as the average is a floating point number. In order to handle floating point arithmetic,
Ekadikena Purvena - the Vedic Sutra which is used to find the square of numbers end with 5 is applied. Example
5 illustrates this. In this case, instead of squaring the average and deviation, [Average x (Average + 1)] -
[Deviation x (Deviation+ I)] is used. However,
instead of performing the multiplications, the same ROM is used and using equation (10) the result of
multiplication is obtained. n(n+l) = (n 2
+n) ... (10)
Here n 2 is obtained from the ROM and is added with the address which is equal to n(n+l). The sample
ROM contents are given in Table 1. TABLE 1: ROM CONTENTS Address Memory Content (Square)
Thus, division and multiplication operations are effectively converted to subtraction and addition
operations using Vedic Maths. Square of both Average and Deviation is read out simultaneously by using a two
port memory to reduce memory access time.
Example 3: 18 x 14=252
I. Find the difference between (18-14) = 4 → Even Number
II. For Even Difference, Product = [Average]2
- [Deviation]2
i. Average = [(a+b)/2] = [(18+14)/2] = [32/2] = 16
ii. smallest(a, b) = smallest(l8,14) =14
iii. Deviation = Average - Smallest (a,b) = 16 -14 =2
III. Product = 162
-22
= 256 - 4 = 252
Example 4: 16 x 13 = 208
I. Find the difference between (16-13) =3 →Odd Number
II. For Odd Number Difference find the Average and Deviation.
i. Average = [(a+b)/2] = [(16+13)/2] = 14.5
ii. Deviation=[Average - smallest(a,b)]= [14.5 - smallest(l6,13)] = [14.5 - 13] = 1.5
III. Product = (l4xI5) - (lx2) = 210 - 2 =208
Example 5: 252
=625
I. To find the square of 25, first find the square of 5 which is 25 and put 2 in the tens place and 5 in the ones
place of the answer respectively.
II. To find the number in the hundreds place, multiply 2 by its immediate next number, 3, which is equal to
(2x3) = 6
III. Answer 252
=625
Fig.4 depicts the RTL view of the proposed multiplier for 4x4 as a sample case, implemented on a
Cyclone II device. 8x8 multiplier is implemented using ROM approach, by storing the squares of the numbers in
the memory starting from 0000 0000 to 1111 1111. The memory requirement for an 8x8 multiplication will be
8KB. But in the case of 16xl6 multiplier the memory requirement will be huge, 216
x32=2MB. So, in order to
reduce the memory requirements for higher order bit multiplication, (l6x16, 32x32, etc.) lower order (8x8)
multiplier can be instantiated[1 7]. By this process the constraint of larger memory requirements can be
overcome.
Fig. 4: RTL View of Proposed Multiplier (4x4)
5. Design and Implementation of Vedic Multiplier
www.ijerd.com 27 | Page
V. EXPERIMENTAL RESULTS
From the Table 2 and Table 3, it is inferred that the proposed multiplier is best suited for the
applications where the less area requires and speed is major considerations. This is achieved due to the feature
of multiplier that will consume only fewer logic elements for its implementation.
Array Multiplier Urdhava Multiplier Proposed Multiplier
16x16 Multiplier 510 810 145
8x8 Multiplier 126 180 311
Table: 2 Requirements of combinational logic functions
Array Multiplier Urdhava Multiplier Proposed Multiplier
61.277 50.952 23.87
Table: 3 Time delay in nanoseconds for 16x16 Multipliers
Fig:5 For 16x16 Multipliers it will shows the time delay comparison
Fig:6 For 16x16 Multipliers Area comparison
From the observation of simulation results for 8x8 and 16x16 multipliers in the case of proposed
multipliers it is clear that it is more efficient and comfortable for higher order multipliers i.e, greater than 8x8
multipliers
VI. CONCLUSION
Thus the proposed multiplier provides higher performance for higher order bit multiplication. In the
proposed multiplier for higher order bit multiplication i.e. for 16x16 and more, the multiplier is realized by
instantiating the lower order bit multipliers like 8x8. This is mainly due to memory constraints. Effective
memory implementation and deployment of memory compression algorithms can yield even better results.
REFERENCES
[1]. Swami Bharati Krishna Tirthaji, Vedic Mathematics. Delhi: Motilal Banarsidass Publishers, 1965.
[2]. K.K.Parhi "VLSI Digital Signal Processing Systems -Design and Implementation" John Wiley & Sons,
1999.
6. Design and Implementation of Vedic Multiplier
www.ijerd.com 28 | Page
[3]. Harpreet Singh Dhillon and Abhijit Mitra "A Digital Multiplier Architecture using Urdhava
Tiryakbhyam Sutra oj Vedic Mathematics" IEEE conference Proceedings, 2008.
[4]. Asmita Haveliya "A Novel Design for High Speed Multiplier .for Digital Signal Processing
Applications (Ancient Indian Vedic mathematics approach)" International Journal of Technology And
Engineering System(IJTES):Jan - March 2011- Vo12 .Nol
[5]. Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh "Perfimnance Analysis of'32-Bit Array
Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder" International Journal of
Recent Trends in Engineering, Vol 2, No. 6, November 2009
[6]. Parth Mehta, Dhanashri Gawali "Conventional versus Vedic mathematical method for Hardware
implementation of a multiplier"2009 International Conference on Advances in Computing, Control,
and Telecommunication Technologies
[7]. Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat ""High Speed ASIC Design of
Complex Multiplier Using Vedic Mathematics" Proceeding of the 2011 IEEE Students' Technology
Symposium 14-16 January, 20 II, lIT Kharagpur
[8]. H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. B. Cho, "Multiplier design based on ancient Indian
Vedic Mathematics," in Proceedings IEEE International SoC Design Conference, Busan, Nov. 24-25,
200S,pp.65-6S
[9]. H. Thapliyal, M. B. Srinivas and H. R. Arabnia , "Design And Analysis oj a VLSI Based High
PerJormance Low Power Parallel quare Architecture", in Proc. Int. Conf. Algo. Math. Compo Sc., Las
Vegas, June 2005, pp. 72-76.
[10]. P. D. Chidgupkar and M. T. Karad, "The Implementation oj Vedic Algorithms in Digital Signal
Processing", Global J. oj /c'ngg. /c’Du., vol. 8, no.2, pp. 153-158, 2004.
[11]. H. Thapliyal and M. B. Srinivas, "High Speed Efficient N x N Bit Parallel Hierarchical Overlay
Multiplier Architecture Based on Ancient Indian Vedic Mathematics", EnJormatika Trans., vol. 2, pp.
225-22S, Dec. 2004.
[12]. Wakerly, J.F. "Digital Design-Principles and Practices", 2006, 4th
Edition. Pearson Prentice Hall.
[13]. J.Bhasker, "Verilog HDL Primer" BS P Publishers, 2003.
[14]. Himanshu Thapliyal, S. Kotiyal and M.B. Srinivas, "Design and Analysis of a Novel Parallel Square
and Cube Architecture Based on Ancient Indian Vedic Mathematics", Proceedings on 48th II/c'/c'/c'
International Midwest Symposium on Circuits and Systems (MWSCAS 2005),