RGUKT- BASAR Chapter-1 Digital Systems Introduction
1. 1
RGUKT- BASARChapter-1
Chapter-1
INTRODUCTION
The concept of digital data manipulation has made a dramatic impact on our society.
One has long grown accustomed to the idea of digital computers. Evolving steadily from main-
frame and minicomputers, personal and laptop computers have proliferated into daily life.
More significant, however, is a continuous trend towards digital solutions in all other areas of
electronics. Instrumentation was one of the first non-computing domains where the potential
benefits of digital data manipulation over analog processing were recognized. Other areas
such as control and telecommunications were soon to follow.
Digital systems have such a prominent role in everyday life that we refer to the present
technological period as the digital age. Digital systems are used in communication, business
transactions, traffic control, spacecraft guidance, medical treatment, weather monitoring, the
Internet, and many other commercial, industrial, and scientific enterprises. We have digital
telephones, digital televisions, digital versatile discs, digital cameras, handheld devices, and,
of course, digital computers. We enjoy music downloaded to our portable media player (e.g.,
iPod Touch™) and other handheld devices having high resolution displays. These devices have
Graphical User Interfaces (GUIs), which enable them to execute commands that appear to the
user to be simple, but which, in fact, involve precise execution of a sequence of complex
internal instructions. Most, if not all, of these devices have a special‐purpose digital computer
embedded within them. The most striking property of the digital computer is its generality.
General‐purpose digital computers can perform a variety of information‐processing tasks that
range over a wide spectrum of applications.
Additions and multiplications are the only two basic operations involved in all digital
processors. The performance of the hardware which perform these operations is vital
importance in present technology. Multiplier is one of the key hardware block in designing
arithmetic, signal and image processors. Many transform algorithms like Fast Fourier
Transform (FFTs), Discrete Fourier Transform (DFT) etc. Make use of multipliers with
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RGUKT- BASAR
advances in technology, many researchers have tried to design multipliers which offer high
speed, low power consumption, regularity of layout and hence less area or even combination
of them in multiplier. In recent years, high-speed multipliers play an important role while
designing any architecture and researchers are still working on many factors to increase the
speed of operation of these basic elements. Algorithms for designing high-speed multipliers
have been modified and developed for better efficiency. The increased complexity of various
applications, demands not only faster multiplier chips but also smarter and efficient
multiplying algorithms that can be implemented in the chips. It is up to the need of the
application on to which the multiplier is implemented and what trade-offs need to be
considered. Generally, the efficiency of the multipliers are classified based on the variation in
speed, area and configuration.
The 1-bit full-adder cell is the building block of multiplier. Thus, enhancing its
performance is critical to enhance the overall module performance. Addition is a prefix
problem. Each result bit is dependent on all input bits. Propagation of a carry signal from each
bit to all higher bit position is necessary. This results in a considerable circuit delay. On the
other hand, there is a high demand for smaller and more durable portable systems. This leads
to considering two more design factors, the area and the power dissipation of the designed
cell. Less area will lead to smaller portable systems and low power dissipation will allow the
portable system to operate longer with the same battery.
Here we used area efficient, low power and high-speed I-bit full adder cell. It has only
10 transistors. And the performance: area, power, time delay and driving capabilities of the
proposed adder cell are analysed in comparison with the existent low-power high-speed
adder. Simulation of the proposed cell prototype is presented.
3. 3
RGUKT- BASARChapter-2
Chapter-2
MOTIVATION
Conventional mathematics is an integral part of engineering education as most
engineering system designs are based on various mathematical approaches. A multiplier is
one of the key hardware blocks in most digital signal processing systems. With advances in
technology, many researchers have tried to design multipliers which offer either of the
following- high speed, low power consumption, regularity of layout and hence less area or
even combination of them in multiplier. The Vedic mathematics approach is totally different
and considered very close to the way a human mind works.
The Vedic methods are direct, and truly extraordinary in their efficiency and
simplicity. Research is being carried out in many areas, including the effects on children
who learn Vedic maths and the development of new, powerful but easy applications of
the Vedic sutras in geometry, calculus, computing etc. But the real beauty and
effectiveness of Vedic mathematics cannot be fully appreciated without actually
practising the system. Then see that it is perhaps the most refined and efficient
mathematical system possible.
The Urdhva – Tiryagbhyam sutra under Vedic mathematics is the general formula
applicable to all cases of multiplication. The formula being very short and terse, consists of
only one compound word and means “vertically and crosswise”. The application of this sutra
will ensure simpler means to solve typical multiplication problems encountered in the
engineering environment.
4. 4
RGUKT- BASARChapter-3
Chapter-3
OBJECTVE AND METHODOLOGY
3.1 Objective:
Our main objective in this project is to implement 4x4 Vedic multiplier by using speed- and
power efficient 10 transistor Full adder cell.
3.2 Methodology
Design AND and
BUFFER.
Verify the circuits for
desired results
theoretically
Verify the schematics
circuit for desire result
using Mentor graphics.
Design a 10 Transistor adder cell for
less power less delay
Verify the circuit for desired results
theoretically
Verify the schematic circuit for desire
result using Mentor graphics.
Implement multibit adders using full
adder
Implement the 4X4 Vedic multiplier
architecture using previously designed
Full adder, XOR and MUX cells
Verify the schematic for the desired
results
Get the Overall power consumed and
delay of the circuit
Compare the result with previously
designed multiplier circuits.
Design 4X4 Vedic multiplier
architecture
Verify the architecture for
desired results theoretically
Verify the schematics circuit for
desire result using Verilog code
5. 5
RGUKT- BASARChapter-4
Chapter-4
LITERATURE SURVEY
4.1. Introduction
The 10 Transistor full adder cell paradigm can traced back to pioneering works done
by Vander Lu Junming, Lin Zhenghui and Wang Ling in [1]. Designing aspects of the 10
Transistor full adder cell is inspired by Shipra Mishra and Shylendra Sing Thomar [2] where
significant work has done to reduce the leak power and make the adder cell power efficient.
Dan wang and Maofeng Yang Implemented the full adder cell Using CMOS 180nm technology
in [3]. This paper proposes four low power adder cells using different XOR and XNOR gate
architectures. Two sets of circuit designs are presented. One implements full adders with 2
transistors (2-T) XOR and XNOR gates. This full adder cell demonstrate its advantages,
including lower power consumption, smaller area and higher speed.
Yogita Bhansal and Pradeep Kaur presented Vedic Multiplier based on Vedic formula
known as Urdva Tiryakbhyam (vertical and crosswise multiplication) which is proved as high
speed multiplier in [4]. Further high speed pipelined Vedic multiplier architecture is
proposed by Vaijyanath Kunchigi, Linganagouda Kulkarni and Subhash Kulkarni [5], which is
efficient in speed and area(less resources used, such as less number of multipliers and
adders) and is flexible in design. Design and Implementation of 8-Bit Vedic Multiplier Using
CMOS Logic presented by Yeshwant Deodhe, Sandeep Kakde and Rushikesh Deshmukh[6].
The design is then verified in T-SPICE using 180 nm CMOS technology model library file, this
proposed multiplier consumes 75% less power compared to the gate level analysis done
earlier. The paper pipelined architecture for Vedic multiplier by Harish Babu N and Satish
Reddy N [7] a 4bit pipelined Vedic multiplier architecture is designed and it has shown more
efficient in terms of less delay compared to normal Vedic Multiplier and improvement in
speed using U-T sutra with a span of 300ps, this design better suited for applications like
where delay is the criteria as a high speed multipliers.
4.2 Binary Adders
Digital computers perform a variety of information-processing tasks. Among the functions
encountered are the various arithmetic operations. The most basic arithmetic operation is
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RGUKT- BASARLITERATURE SURVEY
the addition of two binary digits. This simple addition consists of four possible elementary
operations: 0+0=0, 0+1=1, 1+0=1, and 1+1=10. The first three operations produce a sum of
one digit, but when both augend and addend bits are equal to 1, the binary sum consists of
two digits. The higher significant bit of this result is called a carry. When the augend and
addend numbers contain more significant digits, the carry obtained from the addition of two
bits is added to the next higher order pair of significant bits. A combinational circuit that
performs the addition of two bits is called a half adder. One that performs the addition of
three bits (two significant bits and a previous carry) is a full adder. The names of the circuits
stem from the fact that two half adders can be employed to implement a full adder.
A binary adder is a combinational circuit that performs the arithmetic operations of addition
with binary numbers. For this the half adder design is carried out first, from which the full
adder have developed. Connecting n full adders in cascade produces a binary adder for two
n-bit numbers.
Addition of n-bit binary numbers requires the use of a full adder, and the process of addition
proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After the
least significant bit, addition at each position adds not only the respective bits of the words,
but must also consider a possible carry bit from addition at the previous position. A full adder
is a combinational circuit that forms the arithmetic sum of three bits. It consists of three
inputs and two outputs. Two of the input variables, denoted by x and y, represent the two
significant bits to be added. The third input, z, represents the carry from the previous lower
significant position. Two outputs are necessary because the arithmetic sum of three binary
digits ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two
outputs are designated by the symbols S for sum and C for carry. The binary variable S gives
the value of the least significant bit of the sum. The binary variable C gives the output carry
formed by adding the input carry and the bits of the words. The truth table of the full adder
is listed in Table. The eight rows under the input variables designate all possible combinations
of the three variables. The output variables are determined from the arithmetic sum of the
input bits. When all input bits are 0, the output is 0. The S output is equal to 1 when only one
input is equal to 1 or when all three inputs are equal to 1. The C output has a carry of 1 if two
or three inputs are equal to 1. The input and output bits of the combinational circuit have
different interpretations at various stages of the problem. On the one hand, physically, the
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RGUKT- BASARLITERATURE SURVEY
binary signals of the inputs are considered binary digits to be added arithmetically to form a
two-digit sum at the output. On the other hand, the same binary values are considered as
variables of Boolean functions when expressed in the truth table or when the circuit is
implemented with logic gates. The maps for the outputs of the full adder are shown in Figure.
The simplified expressions are
𝑆 = 𝑋′
𝑌′
𝑍 + 𝑋′
𝑌𝑍′
+ 𝑋𝑦′
𝑍′
+ 𝑋𝑌𝑍
𝑆 = 𝑋⨁𝑌⨁𝑍
𝐶 = 𝑋𝑌 + 𝑌𝑍 + 𝑋𝑍
𝐶 = 𝑋𝑌 + 𝑍(𝑋⨁𝑌)
Table 4.1 Full Adder Truth table
Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder
and n-1 full adders. The four-bit adder is a typical example of a standard component. It can
be used in many applications involving arithmetic operations.
Figure 4.1.a Realization of full Adder with various gates
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RGUKT- BASARLITERATURE SURVEY
Figure 4.1.b Realization of full Adder with various gates
Figure 4.2. Four bit binary adder
4.3 Binary Multiplier
Multiplication of binary numbers is performed in the same way as multiplication of
decimal numbers. The multiplicand is multiplied by each bit of the multiplier, starting from
the least significant bit. Each such multiplication forms a partial product. Successive partial
products are shifted one position to the left. The final product is obtained from the sum of
the partial products. A simple 2-bit binary multiplier showed below
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RGUKT- BASARLITERATURE SURVEY
Figure 4.3. Two bit multiplier
4.3.1 Binary Multiplication Based on Vedic Mathematics
4.3.1.1 Vedic Mathematics
The Sanskrit word 'Veda' means 'knowledge'. The Vedas consist of a huge number
of documents there are said to be thousands of such documents in India, many of
which have not yet been translated, which are shown to be highly structured, both
within themselves and in relation to each other. Some documents, called 'Ganita sutras'
(the name 'ganita' means mathematics), were devoted to mathematical knowledge. Sri
Bharati Krishna Tirtha Maharaj, who is generally considered the doyen of this discipline,
in his seminal book Vedic Mathematics, wrote about this special use of sutras.Vedic
Mathematics" was the name given by him. He was the person who collected lost formulae
from the writings of "Atharwa Vedas" and wrote them in the form of Sixteen Sutras
and thirteen sub-sutras. Vedic Mathematics is based on 16 sutras dealing with
mathematics related to arithmetic, algebra, and geometry. These methods and ideas
can be directly applied on trigonometry, plain and spherical geometry, conics, calculus
and applied mathematics of various kinds. The Vedic methods are direct, and truly
extraordinary in their efficiency and simplicity. Research is being carried out in many
areas, including the effects on children who learn Vedic maths and the development of
new, powerful but easy applications of the Vedic sutras in geometry, calculus, computing
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RGUKT- BASARLITERATURE SURVEY
etc. But the real beauty and effectiveness of Vedic mathematics cannot be fully
appreciated without actually practising the system. Then see that it is perhaps the most
refined and efficient mathematical system possible.
This list of sutra is taken from the book Vedic Mathematics, which includes a full list of
the 16 main sutras The following are the 16 main sutras or formulae of Vedic math
and their meaning in English.
1. (Anurupye) Shunyamanyat - If one is in ratio, the other is zero
2. Chalana-Kalanabyham - Differences and Similarities.
3. Ekadhikina Purvena - By one more than the previous one.
4. Ekanyunena Purvena - By one less than the previous one
5. Gunakasamuchyah - The factors of the sum is equal to the sum of the factors
6. Gunitasamuchyah - The product of the sum is equal to the sum of the product
7. Nikhilam Navatashcaramam Dashatah - All from 9 and the last from 10
8. Paraavartya Yojayet - Transpose and adjust.
9. Puranapuranabyham By the completion or no completion
10. Sankalana-vyavakalanabhyam - By addition and by subtraction
11. Shesanyankena Charamena - The remainders by the last digit
12. Shunyam Saamyasamuccaye - When the sum is the same that sum is zero
13. Sopaantyadvayamantyam - The ultimate and twice thepenultimate
14. Urdhva-tiryakbyham - Vertically and crosswise
15. Vyashtisamanstih - Part and Whole
16. Yaavadunam - Whatever the extent of its deficiency
4.3.1.2 Urdhva-Tiryakbyham - Vertically and crosswise
This sutra is based on “Vertically and Crosswise” technique. It makes almost all the
numeric computations faster and easier. The advantage of multiplier based on this sutra over
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RGUKT- BASARLITERATURE SURVEY
the others is that with the increase in number of bits, area and delay increase at a smaller
rate in comparison to others. In Figure, this method is illustrated with the multiplication of
two decimal numbers 325 and 738. The numbers of steps in the process depend upon the
number of the digits being used. Digits on the two ends of the lines are multiplied and
resultant is added to the carry from previous step. When the number of crossing lines in a
single step is greater than one then they all are added along with the previous carry. After
this, only the least significant digit of the resulting number is taken as product digit and rest
are considered as carry digits. Initial carry is taken as zero.
Figure 4.4. Multiplication of two decimal Figure 4.5 2X2 Vedic multiplier
numbers using Urdhva Tiryakbhyam
Figure 4.6. Generalized block diagram for NXN multiplier
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RGUKT- BASARLITERATURE SURVEY
4.4. Switch level design of digital circuits
4.4.1 CMOS inverter
The inverter is truly the nucleus of all digital designs. Once its operation and properties
are understood, designing more intricate structures such as NAND gates, adders, multipliers,
and microprocessors is greatly simplified. The electrical behavior of these complex circuits
can be almost completely derived by extrapolating the results obtained for inverters. The
analysis of inverters can be extended to explain the behavior of more complex gates such as
NAND, NOR, or XOR, which in turn form the building blocks for modules such as multipliers
and processors.
Figure 4.7. CMOS inverter Figure 4.8. CMOS inverter DC characteristics
4.4.2 1-bit Full adder:The 1-bit full-adder functionality can be summarized by the following
equations, given the three 1-bit inputs A, B, and Cin, it is desired to generate the two 1-bit
outputs Sum and Cout , where
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RGUKT- BASARLITERATURE SURVEY
𝑆 = 𝐴⨁𝐵⨁𝐶in ----------------------------1
𝐶𝑜𝑢𝑡 = 𝐴𝐵 + (𝐴 ⊕ 𝐵)𝑛---------------2
These two equations can be arranged as follows:
𝑆 = (𝐴⨁𝐵)′𝐶𝑖𝑛 + (𝐴⨁𝐵)𝐶𝑖𝑛′
𝐶𝑜𝑢𝑡 = (𝐴⨁𝐵)𝐶𝑖𝑛 + (𝐴⨁𝐵)′𝐴
The novel adder cell has 10 transistors. In this adder cell, the implementation of the XOR and
XNOR of A and B (𝐻 = 𝐴⨁𝐵, 𝐻′ = 𝐴⨀𝐵) is based on using pass transistors and an inverter to
invert the input signal A. This implementation results in the Fast XOR and XNOR. The XOR and
XNOR circuits are shown in Fig. The novel adder cell is shown in Fig.
Figure 4.9. Pass transistor XOR and XNOR gates Figure 4.10. 10T full adder
Figure 4.11. Modified 10T Full adder cell
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RGUKT- BASARChapter-5
Chapter-5
DESIGN, IMPLEMENTATION AND SIMULATION
5.1 Inverter:
CMOS inverter was designed in 180nm technology.
Relation between aspect ratios of NMOS and PMOS for idea inverter given below
(
𝑊
𝐿
)
𝑛
= 2.5 (
𝑊
𝐿
)
𝑝
We found the value of aspect ratio for NMOS at which the DC characteristics of Inverter best
as
(
𝑊
𝐿
)
𝑛
= 10
As in 180nm technology channel length fixed to
𝐿 = 1.8𝜇𝑚
𝑊𝑛 = 1.8𝜇𝑚
Then aspect ratio of PMOS will be
(
𝑊
𝐿
)
𝑝
= 2.5
𝑊𝑝 = 4.5𝜇𝑚
Figure 5.1 CMOS Inverter
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
Figure 5.2 Obtained DC characteristics of CMOS inverter
Desired Logic levels set to be
• logic Zero between 0 V to 0.6 V
• logic one between 2.6 V to 3 V
Obtained noise margins are
𝑉𝐼𝐿 = 1.4𝑉 𝑎𝑛𝑑 𝑉𝐼𝐻 = 1.56
Which validates
𝑉𝑑𝑑 = 𝑉𝐼𝐿 + 𝑉𝐼𝐻
From now we have used this CMOS device to implement FULL Adder, AND gate and Buffer
which basic blocks to implement 4X4 Vedic Multiplier.
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
Figure 5.3 Transient results of CMOS Inverter
Simulation Setup for Transient analysis:
• Signal input = Pulse wave
• Time period = 50 ns
• Duty cycle = 25 ns
• Pulse voltage = 3V
Table 5.1 Performance parameters
Parameter Results
Power (static and Dynamic) 81 pW
Max delay 18.2 ps
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
5.2 Full Adder:
Existing 10T full adder:
Figure 5.4. Existence Full adder
Figure 5.5. Proposed Full adder
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
5.4. 4-bit adder:
Internal functional blocks:
10T full adder
Figure 5.10. Four bit ripple carry adder
Figure 5.11. Four bit full adder results
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
Figure 5.14. 4X4 Vedic multiplier output signals
Figure 5.15. Delay times in the output signals of 4X4 multiplier using proposed full adder
Figure 5.15. Maximum delay of 4X4 multiplier using proposed full adder
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RGUKT- BASARDESIGN, IMPLEMENTATION AND SIMULATION
Table 5.3 Performance parameters of Vedic multiplier using both the full adders
Parameters Existing full adder Proposed full adder
Max Delay 1.0827 ns 586.77 ps
Total power 16.839 mW 23mW
Power-Delay product 18.231 𝑋 10−12
𝑊𝑠 13.495 𝑋 10−12
𝑊𝑠
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RGUKT- BASARChapter-6
Chapter-6
CONCLUSION AND FUTURE SCOPE
7.1 Conclusion
The modified 10-transistors high-speed 1-bit full-adder cell has been proposed. It
uses the pass transistor implementations of the XOR and XNOR functions, inverter, and pass
transistors. Low delay is targeted at the circuit design level. The cell is characterized by a
balanced generation of the control signals of its transmission gates. This will even allow the
building of large architectures that can work at very high frequencies and still have low
delay, which are the requirements of today’s technology. Simulation results for the 1-bit
cells show the superiority of the proposed cell over existent implementations. Further Vedic
multiplier architecture was realized by using proposed full adder. As we have targeted the
full adder for low delay the multiplier also performed efficiently.
7.2 Future scope
Yet we haven’t compared the obtained results with existing work. We do it in future.In our
future work we will try reduce the power dissipation.As we gone through the 4x4 out we
found glitches due lack synchronism among input signals to modules.We will get rid of this by
using synchronism technique.Further we will implement 8X8 Vedic multiplier using this 4X4
Vedic multiplier.
