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Physical design

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Manjunath hosmani
Manjunath hosmani

Physical Design(Floor plan,Power Plan,Placements), With ICC codes

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Physical Design MANJUNATH HOSMANI
ASIC (Application Specific Integrated circuits) Design Flow:  Physical Design  Introduction to Physical Design  Physical Design Input  Physical Design Flow Import Design  Floor planning & Power planning
Physical Design Inputs: The following input files information are loaded to the PnR tool  Netlist (.v/ .vhd/ .edif)  Physical Libraries (.lef)  Timing Libraries (.lib)  Technology Files  Constraints (.sdc)  DEF/ FP
Netlist Netlist contains :  Std. Cell instance – Name & Drive Strength  Macros & Memories instances  Netlist also consists of Ports of Standard Cells and Macros  Interconnection details For ICC IC compiler can read design in .v ,.ddc ,.db formats From GUI: File ->import_design  Loading netlist  import_designs :-format verilog -top dtmf_recvr_core -cel dtmf_recvr_core
Synopsys Design Constraints (SDC): Timing Constraints  Clock Definition (Time Period, Duty Cycle) ICC Codes: Timing Exceptions read_sdc inputs/dtmf_recvr_core.sdc  False Paths, Asynchronous Paths Non-Timing Constraints  Operating conditions (PVT Conditions)  Wire load models  System interface,  Design rule constraints (DRVs - Max. Cap./ Transition/Fanout)  Area constraints,  Multi-voltage and Power optimization constraints  Logic assignments
Timing Libraries (.lib or .db) Timing Libraries:  Cell Logical View/ The Timing Library  Std. Cell lib, Macro lib, IO lib  Cell Type and Functionality  Delay Models Pin/ Cell Timings and design rules  PVT Conditions  Power Details (Leakage and Dynamic)
Library Exchange Format (LEF) Library Exchange Format (LEF):  Cell Abstract View/ the Physical Library  Std. Cell LEF, Macro LEF and IO LEF  LEF contains (Cell Name, Shape, Size, Orientation & Class)  Port/Pin Name, Direction and Layout Geometries  Obstruction/ Blockages  Antenna Diff. Area
Technology File and TLU+ Files Technology File:  Defines Units and Design Rules for Layers and Vias as per the Technology.  Name and Number conventions of Layers and Vias.  Physical and Electrical parameters of Layers and Vias. TLU+ Files:  TLU+ is a binary table format that stores the RC coefficients.  The TLU+ models enable accurate RC extraction results by including the effect of width, space, density, and temperature on the resistance coefficients.  The Map file matches the layer and via names in the Milky way technology file with the names in the ITF( Interconnect Technology Format) file.
Sanity Checks: Physical design sanity checks  check_library  check_timing  check_design  check_legality  report_timing ICC Codes:  check_library > reports/check_library.rpt  check_design > reports/check_design_import.rpt  check_timing > reports/check_timing_import.rpt  report_design > reports/report_design_physical.rpt
Design Exchange Format:  Design Exchange Formats List & locations of Components, Vias, Pins, Nets, Special nets.  Die dimensions, Row definitions, Placement and Bounding Box Data, Routing Grids, Power Grids, Pre- routes  .def, .fp are the common formats.
Creating Milkyway Library  It is necessary to create a Milky way library in which the work will be performed.  From GUI: File :>create library From Command Prompt: Create Milkyway Library Database using the below commands source this command and saved as .tcl format Icc_shell > source /scripts /import_design.tcl Creating milkyway database  create_mw_lib -technology /tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf - mw_reference_library {/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m. The Mw contains:  Technology parses the tech file.  Reference library parses the FRAM view
Floor Plan  A floor planning is the process of placing blocks/macros in the chip/core area, thereby determining the routing areas between them.  Floorplan determines the size of die and creates wire tracks for placement of standard cells.  It creates power ground(PG) connections.  It also determines the I/O pin/pad placement information. A good floor planning should meet the following constrains.  Minimize the total chip area,  Make routing phase easy (routable),  Improve the performance by reducing signal delays.
Contd.. Inputs for floorplan  Synthesized netlist(.v, .vhdl)  Design Constrains (SDC)  Physical partitioning information of the design  IO placement file(optional)  Macro placement file(optional)  Floor planning control parameters Output of floorplan  Die/Block area  I/O pad/placed  Macro placed  Power grid design  Power pre-routing  Standard cell placement areas.
Macro Placement Macro Placement is done based on connectivity information.  Macros to IO cells  Macro to Macro  Macro Placement is very typical for congestion and timing  Macro placement should result in uniform standard cells area. Macro Placement Requires  Fly lines analysis  Data flow analysis  Design module hierarchy Analysis  Channel length calculation
Macro Placement Guidelines Group the macros based on  Instance hierarchy  Connectivity(fly lines)  Data flow diagram  Never in middle or center except they are timing critical.  Place the macros where no or less no of I/O ports  Provide uniform Std.cell area
Create Floorplan  By Manually we can create a floorplan using the below procedure  Go to Floorplan menu >then click on the create floorplan then dialog box appear in the pop up window.  And also we can adjust the floorplan using below command create_floorplan -core_aspect_ratio 0.7 -flip_first_row -left_io2core 5 -bottom_io2core 5 -right_io2core 5 - top_io2core 5 -keep_macro_place  In the Dialog box Make core utilization is depends on your design and aspect ration also.  Click on the flip first row and keep macro place and hit OK.  Next we need to specify Constraints for routing the ports.  Using Get attribute comands Changing the attributes of all IO ports is fixed  set_attribute [get_ports *] is_fixed true  save_mw_cel -as io_placed Changing the attributes of Macros as fixed  set_attribute [all_macro_cells ] is_fixed true
Power Planning  Power planning is a step which typically is done with floor planning in which power grid network is created to distribute power to each part of the design equally. •Power planning can be done manually as well as automatically through the tool. •Deal with Power Distribution Network Three levels of Power Distribution  Rings Carries VDD and VSS around the chip  Stripes Carries VDD and VSS from Rings across the chip  Rails Connect VDD and VSS to the standard cell VDD and VSS.
Contd… ICC Commands:  To see the power report: Icc_shell >report_area  Check Logical Connectivity Icc_shell>check_mv_design –verbose  Making logical connection derive_pg_connection -power_net {VDD} -ground_net {VSS} -power_pin {VDD} -ground_pin {VSS} derive_pg_connection -power_net {VDD} -ground_net {VSS} -tie
Create Power Straps Create Power Straps We can Create power straps in a two ways one is Horizontal and another one is Vertical. For Horizontal /vertical Go to Pre rout tab in menu bar and select create power straps, then enter the value of the given field with their respect values: Ex:  Select Nets: VDD VSS  Layer:M7/M8  Width:0.5  Direction: Horizontal/Vertical  Y start:2  Straps:120  Y increment:10
Prerouting Standard cell  Standard Cells PG pins:preroutr > preroute_standard_cells  To physically rout standard cells PG pins go to the menu bar select preroute and then select preroute_standard_cells  Connect Pins only on Layer number M1  Connect: Horizontal and vertical  Verify weather all the power and ground pins of standard cell,macros,pad cells are connected to corresponding power and ground nets:  Icc-shell>verify_pg_nets
Pre Placed Cells Tap Cells  Well taps are inserted in design to prevent latch-up.  Well tap cells are used to limit resistance b/n power and ground connections to wells of substrate.  The rules for Well taps and End caps are technology dependent and need to have well tap for every X microns. And end caps at every edge of std cell row. End Cap Cells  These cells do not have cell connectivity as they are only connected to power and ground rails, thus to ensure that gaps do not occur between well and implant layer and to prevent the .DRC violations by satisfying well tie-off requirements for core rows.

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Physical design

  • 2. ASIC (Application Specific Integrated circuits) Design Flow:  Physical Design  Introduction to Physical Design  Physical Design Input  Physical Design Flow Import Design  Floor planning & Power planning
  • 3. Physical Design Inputs: The following input files information are loaded to the PnR tool  Netlist (.v/ .vhd/ .edif)  Physical Libraries (.lef)  Timing Libraries (.lib)  Technology Files  Constraints (.sdc)  DEF/ FP
  • 4. Netlist Netlist contains :  Std. Cell instance – Name & Drive Strength  Macros & Memories instances  Netlist also consists of Ports of Standard Cells and Macros  Interconnection details For ICC IC compiler can read design in .v ,.ddc ,.db formats From GUI: File ->import_design  Loading netlist  import_designs :-format verilog -top dtmf_recvr_core -cel dtmf_recvr_core
  • 5. Synopsys Design Constraints (SDC): Timing Constraints  Clock Definition (Time Period, Duty Cycle) ICC Codes: Timing Exceptions read_sdc inputs/dtmf_recvr_core.sdc  False Paths, Asynchronous Paths Non-Timing Constraints  Operating conditions (PVT Conditions)  Wire load models  System interface,  Design rule constraints (DRVs - Max. Cap./ Transition/Fanout)  Area constraints,  Multi-voltage and Power optimization constraints  Logic assignments
  • 6. Timing Libraries (.lib or .db) Timing Libraries:  Cell Logical View/ The Timing Library  Std. Cell lib, Macro lib, IO lib  Cell Type and Functionality  Delay Models Pin/ Cell Timings and design rules  PVT Conditions  Power Details (Leakage and Dynamic)
  • 7. Library Exchange Format (LEF) Library Exchange Format (LEF):  Cell Abstract View/ the Physical Library  Std. Cell LEF, Macro LEF and IO LEF  LEF contains (Cell Name, Shape, Size, Orientation & Class)  Port/Pin Name, Direction and Layout Geometries  Obstruction/ Blockages  Antenna Diff. Area
  • 8. Technology File and TLU+ Files Technology File:  Defines Units and Design Rules for Layers and Vias as per the Technology.  Name and Number conventions of Layers and Vias.  Physical and Electrical parameters of Layers and Vias. TLU+ Files:  TLU+ is a binary table format that stores the RC coefficients.  The TLU+ models enable accurate RC extraction results by including the effect of width, space, density, and temperature on the resistance coefficients.  The Map file matches the layer and via names in the Milky way technology file with the names in the ITF( Interconnect Technology Format) file.
  • 9. Sanity Checks: Physical design sanity checks  check_library  check_timing  check_design  check_legality  report_timing ICC Codes:  check_library > reports/check_library.rpt  check_design > reports/check_design_import.rpt  check_timing > reports/check_timing_import.rpt  report_design > reports/report_design_physical.rpt
  • 10. Design Exchange Format:  Design Exchange Formats List & locations of Components, Vias, Pins, Nets, Special nets.  Die dimensions, Row definitions, Placement and Bounding Box Data, Routing Grids, Power Grids, Pre- routes  .def, .fp are the common formats.
  • 11. Creating Milkyway Library  It is necessary to create a Milky way library in which the work will be performed.  From GUI: File :>create library From Command Prompt: Create Milkyway Library Database using the below commands source this command and saved as .tcl format Icc_shell > source /scripts /import_design.tcl Creating milkyway database  create_mw_lib -technology /tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf - mw_reference_library {/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m. The Mw contains:  Technology parses the tech file.  Reference library parses the FRAM view
  • 12. Floor Plan  A floor planning is the process of placing blocks/macros in the chip/core area, thereby determining the routing areas between them.  Floorplan determines the size of die and creates wire tracks for placement of standard cells.  It creates power ground(PG) connections.  It also determines the I/O pin/pad placement information. A good floor planning should meet the following constrains.  Minimize the total chip area,  Make routing phase easy (routable),  Improve the performance by reducing signal delays.
  • 13. Contd.. Inputs for floorplan  Synthesized netlist(.v, .vhdl)  Design Constrains (SDC)  Physical partitioning information of the design  IO placement file(optional)  Macro placement file(optional)  Floor planning control parameters Output of floorplan  Die/Block area  I/O pad/placed  Macro placed  Power grid design  Power pre-routing  Standard cell placement areas.
  • 14. Macro Placement Macro Placement is done based on connectivity information.  Macros to IO cells  Macro to Macro  Macro Placement is very typical for congestion and timing  Macro placement should result in uniform standard cells area. Macro Placement Requires  Fly lines analysis  Data flow analysis  Design module hierarchy Analysis  Channel length calculation
  • 15. Macro Placement Guidelines Group the macros based on  Instance hierarchy  Connectivity(fly lines)  Data flow diagram  Never in middle or center except they are timing critical.  Place the macros where no or less no of I/O ports  Provide uniform Std.cell area
  • 16. Create Floorplan  By Manually we can create a floorplan using the below procedure  Go to Floorplan menu >then click on the create floorplan then dialog box appear in the pop up window.  And also we can adjust the floorplan using below command create_floorplan -core_aspect_ratio 0.7 -flip_first_row -left_io2core 5 -bottom_io2core 5 -right_io2core 5 - top_io2core 5 -keep_macro_place  In the Dialog box Make core utilization is depends on your design and aspect ration also.  Click on the flip first row and keep macro place and hit OK.  Next we need to specify Constraints for routing the ports.  Using Get attribute comands Changing the attributes of all IO ports is fixed  set_attribute [get_ports *] is_fixed true  save_mw_cel -as io_placed Changing the attributes of Macros as fixed  set_attribute [all_macro_cells ] is_fixed true
  • 17. Power Planning  Power planning is a step which typically is done with floor planning in which power grid network is created to distribute power to each part of the design equally. •Power planning can be done manually as well as automatically through the tool. •Deal with Power Distribution Network Three levels of Power Distribution  Rings Carries VDD and VSS around the chip  Stripes Carries VDD and VSS from Rings across the chip  Rails Connect VDD and VSS to the standard cell VDD and VSS.
  • 18. Contd… ICC Commands:  To see the power report: Icc_shell >report_area  Check Logical Connectivity Icc_shell>check_mv_design –verbose  Making logical connection derive_pg_connection -power_net {VDD} -ground_net {VSS} -power_pin {VDD} -ground_pin {VSS} derive_pg_connection -power_net {VDD} -ground_net {VSS} -tie
  • 19. Create Power Straps Create Power Straps We can Create power straps in a two ways one is Horizontal and another one is Vertical. For Horizontal /vertical Go to Pre rout tab in menu bar and select create power straps, then enter the value of the given field with their respect values: Ex:  Select Nets: VDD VSS  Layer:M7/M8  Width:0.5  Direction: Horizontal/Vertical  Y start:2  Straps:120  Y increment:10
  • 20. Prerouting Standard cell  Standard Cells PG pins:preroutr > preroute_standard_cells  To physically rout standard cells PG pins go to the menu bar select preroute and then select preroute_standard_cells  Connect Pins only on Layer number M1  Connect: Horizontal and vertical  Verify weather all the power and ground pins of standard cell,macros,pad cells are connected to corresponding power and ground nets:  Icc-shell>verify_pg_nets
  • 21. Pre Placed Cells Tap Cells  Well taps are inserted in design to prevent latch-up.  Well tap cells are used to limit resistance b/n power and ground connections to wells of substrate.  The rules for Well taps and End caps are technology dependent and need to have well tap for every X microns. And end caps at every edge of std cell row. End Cap Cells  These cells do not have cell connectivity as they are only connected to power and ground rails, thus to ensure that gaps do not occur between well and implant layer and to prevent the .DRC violations by satisfying well tie-off requirements for core rows.