The paper describes the basic of Timing analysis like setup time, hold time, delays in logic circuits, timing violations and different types of timing paths like flip-flop to flip-flop path, clock gating path, asynchronous signal path, half cycle path, flip-flop to output path, input to flip-flop path and input to output path.
2. Introduction
In anyintegratedcircuit,more thanfifty million gates are embedded which are at picometers distance
fromeach other.The performance isaffectedbecausethe wiresorlogicgatesinterfere with the nearby
logicgatesaffectingthe circuitfunctionality. Therefore, the power dissipation, area, timing, reliability
become an important concern. Therefore, the chips have to go through verification and debugging
processto ensure the circuit worksproperly on silicon. Amongst all these analysis or processes, timing
analysis is very important because it ensures the proper circuit functionality. The paper deals with
different timing checks that the circuit has to go through in designing and testing stage.
Combinational and Sequential Circuits
Every design possesses the sequential parts and the combinational parts. The sequential circuit
possessesflip-flopsalsocalled memory elements whereas the combinational part includes logic gates
like NANDgate,NORgate,EXORgate,OR gate and soon. These logicgates are combined to implement
variouscircuitslike multipliers,adders,comparatorsandmanysuchlogic blocks.The sequentialelement
can store data whereasgatesproduce outputinstantlywhen inputs are applied. The gates are used for
computation purpose whereas the memory elements store the computed values. These are some
differencesbetweencombinational andsequentialelements. The following figures exhibit both circuit
elements.
Fig1 – Combinational Circuit
3. Fig2 – Sequential Circuit
The basic logic elements are described till now. The main concern is the time at which the output is
produced. The correct output is produced whenever every signal appears at the correct instant in the
circuit. For example,inFig2,if the input‘Bn’arrivesafterone clockcycle with respect to inputs ‘An’ and
‘Cn-1’then ‘sum’ and ‘carry’ generated is incorrect. Therefore, the paper deals with such issues which
are responsible forproducingincorrectoutput.The nextsectiondescribesaboutthe basictermsused in
this analysis.
Basic Terms
In orderto understandthe timing,itismandatorytounderstandfew basicterms related to it. The basic
terms are subdivided into different categories. First and foremost, it is important to understand the
different timing analysis types described in the following section.
Timing Analysis Types
1. Dynamic Timing Analysis (DTA)
The dynamictiminganalysisisusedtocheckwhetherthe outputobtainediscorrectafterinputs
are applied. This analysis concentrates on checking the circuit functionality. For example,
consider a full adder circuit, the DTA checks whether the adder produces correct output for
different stimulus applied. But it fails to check the gate delay involved to produce the output.
4. 2. Static Timing Analysis (STA)
The Dynamic Timing Analysis has some disadvantages. It only checks the circuit functionality.
But the static timing analysis helps to find the time required for each gate to generate output.
But it fails to check whether the circuit produces correct output for given inputs.
Therefore, both analyses go hand in hand. One type verifies the time required to produce an
output whereas one verifies the result obtained is correct or not. However, this paper
concentrates on static timing analysis because that determines the circuit performance.
Delays in Combinational Circuit
1. Propagation Delay (Tp)
A transistoristhe basic elementinlogicgate.Itconsumessome time toproduce the output. For
example,inCMOSinverter(Fig3) whenlogic ‘1’ is applied at the input, output obtained is logic
‘0’. Similarly,logic‘0’at inputresultsinlogic‘1’at the output.Here,transistorsconsume time to
change theirstateswhichcausesdelayingeneratingthe output.So,ingeneral,timerequired to
produce output after the input is applied is called propagation delay. It can also be defined as
the time interval between change in input and change in output for any given circuit. Fig4
demonstrates the propagation delay for inverter.
Fig3. CMOS Inverter
5. Fig4. Propagation Delay of Inverter
2. Tplh
The change inthe inputcausesthe outputto change from low to high.Thisdelayiscalled
propagationdelayfromlow-to-high(Tplh). Itismeasuredfrominputtransitiontime (fifty
percent) till outputrise time (fiftypercent).
3. Tphl
The change inthe inputcausesthe outputto change from highto low.Thisdelay iscalled
propagationdelayfromhigh-to-low (Tphl). Itismeasuredfrominputtransitiontime (fifty
percent) till outputfall time (fiftypercent).
4. Rise Delay (Tr) and Fall Delay (Tf)
The time takento change inputor outputfromlogic‘0’ to logic‘1’ is calledrise delay.The time
takenfor the circuitto change from logic‘1’ to logic‘0’is calledfall delay. The rise andfall
togetheriscalledtransitiondelay.
Fig5. Rise and Fall Delay
6. 5. Interconnect (wire) Delay
Interconnectisthe connectionbetweentwologiccellsinthe design.The signal consumes some
time to propagate through interconnect or wire. This delay is called interconnect delay.
6. Combinational Delay (Ld)
The combinational circuit consumes some time to produce the output. This delay is called the
combinational delay. The interconnect delay is included in the combinational delay.
Delays in Sequential Circuit
The flip-flopsconsume some timetoproduce the output. This is because the transistors consume time
to switchtheirstates.The inverters and the transmission gates consume time to turn on and off which
introduces delay in producing the output.
Fig6. Transistor Level Circuit of Flip-Flop
The circuit showninFig6 isthe flip-flop internal circuit diagram at transistor level. T1, T2, T3, T4 are the
transmission gates also called Pass gate or Pass switch. Pass gate is nothing but one PMOS and one
NMOS connected in parallel. Here, PMOS and NMOS turn on when logic ‘0’ and logic ‘1’ is applied to
PMOS and NMOS gates respectively.
Working of Flip-Flop
For example,T1turnson when‘clk’= 1 and‘clk_bar’= 0. WhenT1 turnson,D inputis reflected at point
‘M’ in the flip-flop.Atthattime,T2and T3 pass gatesare switchedoff because the controllingsignal ‘clk’
is low for NMOS and ‘clk_bar ’ is high for PMOS. But T4 is switched on along with T1. Therefore, T4 just
latches the output ‘Q’ till it remains on.
7. When clk level is changed, i.e. ‘clk’ = 0 and ‘clk_bar’ = 1, T2 and T3 turns on and T1 and T4 are cutoff.
Therefore, T2 just latches the data present at ‘M’ whereas T3 launches the current data at ‘M’ to ‘Q’.
These eventstake place attwodifferentclklevelsformingthe negative edgetriggeredflip-flop.Here,T1
and T2 together form master latch whereas T3 and T4 together form slave latch. The flip-flop internal
circuitdiagramproves that the flip-flopconsume timetolaunchthe data. Therefore,the flip-flop timing
consideration is briefly discussed in the following section.
Flip-flop Timing Consideration
1. Setup Time (Ts)
The minimumtime requiredforthe datato become stable priorto the active clock edge iscalled
setuptime. The passgate ‘T1’ andinvertersinmasterlatchtake some time to reflectinput‘D’at
point ‘M’. This delay is referred flip-flop setup time.
2. Hold Time (Th)
The phenomenon in which the data should remain stable after the active clock edge is called
holdtime. Afterthe active edge hasarrived,still T1 is on because transistors take some time to
turn off.Also,T2 start switchingitsstate i.e. itturnsonwhich holds the value at ‘M’. The T2 and
inverters introduce delay referred hold time.
Fig7. Setup Time and Hold Time
3. Setup Violation
According to setup time, it is mandatory that the data becomes stable prior the clock edge.
Suppose,if datachangeswithinthe setup time (shown in Fig8), then the circuit may enter into
metastable state. This phenomenon is called setup violation.
4. Hold Violation
Accordingto holdtime,the datashouldremainstable forsome time afterthe active clock edge.
Suppose the datatransitionoccurswithinthe hold time (shown in Fig8), then the circuit enters
in metastable state. This is called hold violation.
8. Fig8. Setup and Hold Violation
5. Metastable State
In metastable state,the outputkeepsdanglingbetween logic 1 and logic 0 for unbounded time
period. For example, consider the data transition taking place within the restricted region or
nearthe active clockedge.Atthat time,T1 and T2 start changingtheirstatesandeventhe point
‘M’ alsostarts transition.Butbefore T1 can capture the data, the inputiscutoff (T1 isturnedoff)
which results in voltage at ‘M’ lying between logic ‘1’ and logic ‘0’. After the clock level makes
transition, T3 turns on, this transmit the voltage at ‘M’ to flip-flop output ‘Q’. Therefore, the
output obtained is between ‘0’ and ‘1’. This phenomenon is called metastability.
6. Clock to Output time (Tc-q)
The minimumtime requiredtolaunchdataafter the clock arrives is called clock to output time.
Here,T3 and invertersconsumetime tolaunchthe dataat the output‘Q’.Thisis nothingbutthe
flip-flop slave delay.
7. Skew (Tskew)
The Phase Locked Loop (PLL) causes the clock edge to arrive early or late than expected. For
example,assumethe clockedge shouldarrive at 5ns. Due to some internal problems in PLL the
clock edge arrivesat4.95 ns or 5.05 ns(as showninFig9).The difference between actual arrival
time andthe expectedarrival timeiscalledskew.The followingdiagramdemonstratesthe skew
in the circuit.
9. Fig9. Skew
Positive skew and Negative skew
The clock edge arrives at the time instant after the expected arrival time. The time interval
betweenthe arrival timesispositiveskew. The clockedge arrivesat the time instant before the
expected arrival time. The time interval between the arrival times is negative skew.
The skew plays a negative role in causing hold violation or setup violation in the circuit. The above
discussedtimingparameters play a significant role in determining the circuit performance. Therefore,
this discussion paves a way to timing analysis part.
10. Timing Analysis
To performtiminganalysisingivencircuit,itisimportanttounderstand the timing paths present in the
circuit. The following circuit diagram shows the timing paths in the sequential circuit (Fig10). The
combinational pathbetweenanytwoflip-flops is reg-to-reg path. The path from chip input till the first
flip-flopinputis called input-to-reg path. The path from flip-flop till the circuit output is called reg-to-
outputpath.The combinational partexcludingthe registersinthe circuitis called input-to-output path.
Fig10. Different types of paths in the circuit
The static timing analysis is divided into two major types i.e. Setup Timing Analysis and Hold Timing
Analysis.The setuptime analysisdealswith the critical path(longpath) inthe circuitbecause the critical
path determines the clock frequency. Instead, the hold analysis deals with the minimum path in the
circuitas the minimumpathisresponsibleforthe race condition.Before discussing the timing analysis,
it is important to understand the delay calculation along different paths in the combinational block. It
helpsinidentifyingthe shortandlongpath inthe circuit.The followingsectionbrieflydescribesthe logic
delay calculation along the path.
11. Calculationof Delay in combinational paths
Fig11. Calculation of Long path and short path
In order to identify the critical path and the shortest path between two flip-flops, it is necessary to
compute the total logic delay for each path in the circuit. As a running example, consider the circuit
giveninFig11. InFig11, all interconnect(wire) andNANDgate delaysare specified.Forexample,atInput
‘B’,0.1 is the minimumdelayrequiredforthe inputtoarrive whereas0.5 isthe maximumdelayrequired
for inputB to arrive at the NANDgate ‘N1’ input.Similarly,forNANDgate ‘N1’,0.5 isthe minimumdelay
and 0.9 is the maximum delay. Similarly, the NAND gates and interconnect delays are specified in the
circuit. The next section demonstrates delay calculation for all paths in the circuit.
Calculatingdelay of longestpath
Path 1
Max delay(InputA + N2 + N4) = 0.8 + 0.9 + 0.4 + 0.8 = 2.9
Path 2
Max delay(InputB+ N1 + N2 + N4) = 0.5 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.0
Path 3
Max delay(InputB+ N1 + N3 + N4) = 0.5 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.6
Path 4
Max delay(InputC+ N1 + N2 + N4) = 0.6 + 0.9 + 0.5 + 0.9 + 0.4 + 0.8 = 4.1
Path 5
Max delay(InputC+ N1 + N3 + N4) = 0.6 + 0.9 + 0.3 + 0.8 + 0.3 + 0.8 = 3.7
Path 6
Max delay(InputD+ N3 + N4) = 0.4 + 0.8 + 0.3 + 0.8 = 2.3
12. Comparing all the maximum paths in the circuit, path 4 has the maximum delay and therefore it is
responsible fordeterminingthe clock frequency (explained later). Similarly, the minimum delay along
the path inthe combinationalcircuitcanbe calculated.The onlydifference incalculatingmaximumpath
and minimum path is, while calculating minimum delay, consider the minimum values for all
interconnectsandthe NANDgatesalong the path. The path with the least delay is responsible for race
condition (explained in hold analysis).
Minimumpath in the circuit
Path 1
Min delay(InputA + N2 + N4) = 0.2 + 0.4 + 0.2 + 0.5 = 1.3
Path 2
Min delay(InputD+ N3 + N4) = 0.2 + 0.6 + 0.1 + 0.5 = 1.4
Similarly,computeminimumdelaysalong the path, the shortest path obtained possess 1.3 as the least
delay. Other paths possess delay greater than 1.3 and so the path from Input ‘A’ till output ‘Y’ is the
shortest path and is considered for hold calculation. Now the combinational logic delay between two
flip-flops can be computed. So, the next section describes the reg-to-reg path timing analysis.
13. SetupTiming Analysis
Fig12. Setup and Hold Analysis Circuit
The setup timing analysis deals with the critical path (long path) in the circuit because the long path
determinesthe clockfrequency.If the clockfrequencyishigher,the output is produced at a faster rate.
Therefore,the logicdelayhastobe as small as possible. Therefore, the setup condition in equation (1)
determines the clock time period. According to the condition, the clock period should be greater than
the logic delay, setup time and skew.
Tclk > Tc-q + Ld + Ts + 2Tskew (1)
The above equationsaysthe critical pathincludes ‘Tc-q’aslaunch flip-flop (Flip-flop that launches data
inthe circuit) consumessome time toproduce the output. The ‘Ld’ represents the logic delay between
launch and capture flip-flops. ‘Ts’ is the setup time and ‘Tskew’ is the clock skew. ‘Tclk’ is the clock
period.
In Fig9,two combinational paths introduce delay.The firstpathisinverterdelayplusANDgate delay
whichisabout 3ns. The secondpathis onlyANDgate whichpossess2nsdelay. The maximumpathhas3
ns delayandhence itisconsideredinthe setupcondition. Substitute the valuesinequation(1) thatare
giveninFig12.
5 > 1+3+2+2
5 > 9
14. The above condition proves that the circuit in Fig12 cannot work at 5ns clock. This condition is called
setupviolation andconsequently may enter in metastable state. The clock period should be minimum
9ns to avoidsetupviolation.Therefore,todecrease the clockperiod(increaseclockfrequency) the logic
delay between two flip-flops has to be reduced.
Hold Timing Analysis
Hold analysis is exactly opposite of setup analysis. This type concentrates on short path in the circuit.
The short path is responsible for the race condition which results in undesirable output. Consider the
same circuit shown in Fig9 the short path has 2ns delay. The hold condition is given as follows
Th + 2Tskew < Tc-q + Ld (II)
2+2 < 1 + 2
4 < 3
Accordingto the condition, the short path should be greater than hold and skew. But above relation is
provedwrongwhichstatesthe circuitcan race. Thisphenomenoniscalledholdviolation.Therefore,the
output obtained is undesirable. In order to avoid hold violation, the minimum logic delay should be
greater than hold time and skew.
Race Condition
Fig13. Race Condition
Race conditionisthe phenomenonin which the output is obtained after the first clock edge instead of
second edge. For example, consider the circuit in Fig13, the logic delay is zero between launch and
capture flip-flops.Inthis situation, the capture flip-flop output is obtained directly after the first edge
instead of second edge.
15. The analysisisthe most importantone asmaximumchipspossesstypical reg-to-reg path and analysis is
done as discussedabove.Butchipsalso contain different paths that require analysis. For example, the
otherpaths inthe circuitlike input-to-reg,reg-to-outputandinput-to-output also need timing analysis.
The further section describes timing analysis for all these paths.
Input-To-RegPath
Fig14. Input-to-Reg Path
The circuit in Fig14 is an input-to-reg path. The input can reach capture flip-flop at random time. If the
timinganalysisfor this path is not performed then the circuit may enter into metastable state. So, it is
important to perform static timing analysis for this path. The important thing to note is there is no
launch flip-flop present in the circuit. Before commencing with timing analysis it is important to
understand few terms.
Virtual Flip-flop
In reg-to-regpath,actual flip-flop launches the data. In input-to-reg path, the input flip-flop is absent.
Therefore,connectavirtual flip-flop(shown with dotted lines in Fig12) at the circuit input. Virtual flip-
flop does not introduce delay in launching the data therefore it has zero ‘Tc-q’ delay.
Virtual Clock
The clock edges control flip-flops,therefore itiscrucial toconnect the clock to a virtual flip-flop (shown
in Fig15) called virtual clock. The virtual clock does not introduce delay because it does not exist
physically. As shown in the Fig15, L1 is the virtual clock triggering virtual launch flip-flop whereas L2 is
the actual clock triggering capture flip-flop.
16. Fig15. Input-to-Reg Path Analysis
SetupAnalysis for thispath
The virtual clockand virtual flip-flopconvertsthe input-to-regpathintobasicreg-to-regpath.Therefore
the input-to-outputpathtiminganalysis issimilartoreg-to-regpath. The differencebetween these two
path is the clock-to-output ‘Tc-q’ is absent because the launch flip-flop is virtual. Since virtual clock is
appliedatlaunchflip-flop,therefore the launchflip-flop skew is not considered in the setup condition.
To avoid setup violation at the chip input, the clock time period should be greater than logic delay,
capture flip-flopsetuptime andhalf skew. Therefore,the input-to-regpathsetupconditionforis shown
in equation (3).
Tclk > Ld + Ts (capture flop) + Tskew (3)
Hold Analysis
Typically,the holdanalysisisperformedforbothflip-flopsinreg-to-regpath.In aninput-to-regpath the
launch flip-flop is absent therefore the capture flip-flop is considered in hold analysis. The inputs can
arrive at anytime which may cause capture flip-flop to race. For example, the circuit shown in Fig16
below demonstrates the race condition.
Th + Tskew < Ld
2 + 1 < 2
3 < 2
The hold condition for input-to-reg path is that the logic delay is less than hold time and skew. In the
given hold condition, the Tc-q is absent as well as the Tskew is halved because the input flip-flop is
absentinthe circuit.As perthe givenvaluesinthe circuit,the holdconditionisviolated for input-to-reg
path. Therefore, it is extremely essential to perform hold analysis for this path in order to avoid race
condition at chip input.
17. Fig16. Input-to-reg path circuit example
Reg-to-OutputPath
Similarly, the output flip-flop (reg) may launch data which is the chip output called as reg-to-output
path.At the chip outputnocapture flip-flop is present which can capture the data (shown in Fig17). To
perform reg-to-output path timing analysis, connect the virtual flip-flop and virtual clock at the chip
output (shown in dotted lines in Fig 17).
Fig17. Reg-to-Output path Analysis
Tclk > Tc-q + Ld + Tskew (4)
The virtual flip-flopispresentatthe output. Therefore,the capture flip-flopsetuptime isnotconsidered
inthe setupcondition becausevirtual flip-flopdoesnotintroducedelay.Here,L1 is the real clock and L2
isthe virtual clock.Asa result,L2 doesnot introduce skew. Therefore,the skew ishalvedbecause virtual
18. clock isgivento the virtual flip-flop.Therefore,the reg-to-outputpathsetupanalysis isperformed using
equation (4).
Hold Analysisfor reg-to-outputpath
The inputflip-flopintroduces slave delay in the data path. Therefore, the data should remain stable at
leastforflip-flopholdtime.Also,clockatthe launchflip-flopmayintroduce skew andtherefore,skew is
consideredinthe holdcondition.Therefore,the reg-to-outputpathholdcondition saysthe flip-flophold
time andskewshouldbe lessthanclock-to-outputdelayandlogicdelayalongthe shortpath.Therefore,
the hold condition is given in equation (5).
Th + Tskew < Tc-q + Ld (5)
Comparing equation (2) and (5), the skew is halved because the virtual clock does not introduce any
variationinthe clockpath. Thisdiscussionprovesthe timing analysis of reg-to-output path needs to be
performed to avoid metastability and race condition. The next analysis is for input-to-output path
discussed briefly in the following section.
Input-to-OutputPath
The designcan have a path goingfrominputport to outputport.So, flip-flopisabsentatinputoroutput
endfor thispath. So, timinganalysisis performedinasimilarwayasexplainedforinput-to-reg path and
reg-to-output path. Since no flip-flops are present either at input or output port, connect virtual flip-
flops at both ends.
Fig18. Input-to-Reg Path analysis
The circuit with virtual flip-flops is shown in Fig18. Here, both launch flip-flop and capture flip-flop is
virtual andtherefore the setupcondition is given in equation (6). Comparing equation (1) and (6), only
logic delay is included because the virtual flip-flops do not introduce any delay in the data path.
Tclk > Ld (6)
19. Hold Time check for input-to-outputpath
Th < Ld (7)
Comparingequation(2) and(7),the Tc-q and Tskew delayare removedbecause the virtual flip-flops do
not introduce slave delayinthe data path. Therefore, the hold condition for input-to-output path only
dependsonlogicdelayandisgiven in equation (7). The above analysis explains the basic paths among
all different timing analysis. The following example demonstrates how to perform timing analysis for
different paths in the circuit.
Fig19. Timing Analysis Example
The differenttimingpathslike reg-to-reg,input-to-reg,reg-to-outputandinput-to-outputare present in
the circuit shown in Fig19. Therefore, the setup and hold analysis is performed for all these paths
presentinthe circuit. Therefore,the nextsectiondescribesthe setupand hold analysis for the circuit in
Fig19.
SetupAnalysis
The setup analysis deals with the maximum delay in the circuit. According to the setup condition, the
combinational pathwithmaximumdelay determines the clock frequency. Therefore, the timing paths
available in Fig15 are reg-to-reg path that includes U1 – U4 – U2 and U2 – U3 – U1. The input-to-reg
includes U7 – U4 – U2 and U7 – U3 – U1. Also, U1 – U5 – U6 and U2 – U5 – U6 are reg-to-output path in
the circuit. The path U7 – U5 – U6 is input-to-output path. Amongst all these data paths, the path with
maximum delay determines the clock frequency. The clock path includes U8 – U1 and U8 – U2.
For pathsotherthan reg-to-reg,use the setupconditions asdiscussedinrespective sections.Toperform
setupanalysis,considerthe maximumdelay along all paths. For example, the delay along reg-to-reg is
calculatedusingthe relationTc-q+ Ld + 2*Tskew + Ts. Therefore,the maximumdelay is 12ns along U1 –
U4 – U2 path and 13ns along U2 – U3 – U1 path.
20. Similarly, the input-to-reg path delay is computed using the relation Ld + Tskew + Ts. Here the Tc-q is
absent as well as Tskew is halved because the input launch flip-flop is absent. Still, this path is
consideredbecause thatcancause setupviolation.Therefore,the maximumpathdelay is 11ns along U7
– U4 – U2 path and 12ns along U7 – U3 – U1 path.
The reg-to-outputpath delay iscalculatedusingthe relationTc-q+Ld + Tskew.Here,the output capture
flip-flopisabsent.Therefore,the setuptime isnotconsideredandskew isalsohalved.So, the maximum
path delay is 17ns for U1 – U5 – U6 path and U2 – U5 – U6 path respectively. In input-to-output path,
the launch and capture flip-flops are absent and therefore logic delay (Ld) determines the maximum
delay along the path U7 – U5 – U6.
C.T > 17ns
The maximumdelayobtainedis17nsaftercomparingmaximumpathdelaysinthe circuit. Therefore, to
avoid setup violation, the clock time period should be greater than 17ns. The above analysis is
performed to avoid circuit failure due to long path in the circuit. Similarly, the circuit may fail due to
short path called hold violation. Therefore, it is extremely essential to perform hold analysis to avoid
race conditioninthe circuit.The nextsectiondescribes briefly about hold analysis for the given circuit.
Hold Analysis
The holdcheck dealswiththe minimum path in the circuit because the minimum path (short path) can
cause race condition. Therefore, the different paths hold condition is described in the respective
sections. To perform hold analysis, the minimum delay along various paths is considered.
Solvingthe exampleinFig15,considerall the pathsfor holdanalysis.Forexample, in reg-to-reg path U1
– U4 – U2, the holdconditionischeckedusingthe relation Th+ 2*Tskew < Tc-q + Ld. Similarly,all reg-to-
reg paths hold condition is checked using the relation given below.
Th + 2*Tskew < Tc-q + Ld (8)
2 + 2 < 1 + 7
4 < 8
Th + Tskew < Ld (9)
2 + 1 < 8
3<8
Similarly for input-to-reg path U7 – U4 – U2, the hold condition is given in equation (9). Therefore, the
input-to-regpathholdanalysisis performedusingthe equation(9). Along with other paths, hold is also
checked for reg-to-output path. The condition for this path is given in equation (10).
21. Th + Tskew < Tc-q + Ld (10)
2 + 1 < 1 + 15
3 < 16
Th < Ld (11)
2 < 1 + 9 + 6
2 < 16
Similarly,the input-to-outputpathischeckedusingthe conditiongivenin equation (11). Therefore, the
above analysisprovesthere is no hold violation for any path in the circuit. It is extremely important to
performholdanalysisbeforehandbecause itisdifficult to solve hold violation in physical design stage.
The above example demonstrates solving timing problem involves paths other than reg-to-reg path in
the circuit.Differenttimingchecksinvolvedinthe circuit along with the discussed above are explained
brieflyinthispaper.Alongwiththose paths, clockgatingcheck,recoveryandremoval timingcheck, half
cycle checkand many more are explained inthispaper.Considerthe circuitinFig20 whichshows signals
like reset,enable andasynchronousdatasignalsthatmaycause setupand holdviolation.Therefore,itis
essential tosolve timingviolationforthese pathsaswell.Therefore,the nextsectionsdeal withall these
different timing checks.
Fig20. Circuit for Different Types of Timing Checks
The circuit showninFig20 possesses manydifferentpathsalongwithreg-to-regpath,input-to-reg path,
reg-to-outputpathandinput-to-outputpath.Forexample,the pathfrom‘another_clk’to‘gating signal’
to ‘flip-flopclockpin’isaclockgatingpath. Also,the pathfrom‘clock buffer’to‘latch’toflip-flopoutput
signal ‘out1’ requires timing check. Therefore, many such paths available in the practical circuit are
showninFig20. These pathsmay cause setupviolationorholdviolation and so it is extremely essential
to performtiminganalysisforall these pathsaswell.Therefore, the following sections describe timing
checks for different paths in the circuit.
22. Clock gating check
A clock gating check is required when a gating signal controls the clock signal path in a logic circuit.
Considerthe simplified gated clock circuit diagram shown in Fig21. The AND gate has two inputs which
includes clock signal and ‘enable’ signal also called gated signal. The AND gate output is called ‘gated
clock’.
Fig21. Clock Gating Circuit
Priorto clock gatingcheck,fewconditionsmustbe considered. The gatedclockisusedtodrive flip-flops
and helpstogenerate newclock. The generated clock means the clock which has different parameters
like phase difference,frequencychange ascomparedtooriginal clock(systemclock).Another condition
isfor gatedsignal.The gatedsignal shouldnot be usedas a clockto drive any flip-flopsinthe circuit.The
gatedand clock signal can be connected to AND gate, OR gate or any logic that exhibits ‘AND’ function
or ‘OR’ function. It means clock gating signal is divided into two types.
Active-highclockgating signal and Active-lowclock gating signal
Active-high clock gating signal occurs when logic circuit has ‘AND’ or ‘NAND’ function. The clock is
allowed to propagate through gated logic when the gated signal is active high otherwise the clock is
ceasedto propagate whengatedsignal isactive low. Similarly, the active-low clock gating signal occurs
whenlogiccircuithas‘OR’ or ‘NOR’function.Here, when the gated signal is active low, then only clock
can propagate through the logic circuit.
Considerforexample,the active-highclockgatingsignal showninFig21.The outputclock ‘CLKB’timing
diagramand gatedsignal isshowninFig22. If the gatedsignal goeslow justafterthe positive clockedge
thena glitchis generatedwhichcantriggerthe flip-flopwhennotdesired.
23. Fig22. Gated Signal causing Glitch in CLKB
Therefore,the glitchproducedin‘CLKB’triggers the capture flip-flop which captures undesired output
causing whole system to produce incorrect results. Therefore, it is essential to perform clock gating
timing check to avoid circuit functionality failure in the system.
SetupCheck for clock gating signal
The setup check says the signal should arrive before the active clock edge. In gated check, the enable
shouldarrive atthe negative clocklevel otherwise itcausesthe systemtoproduce incorrectresults. The
Fig23 shows the enable signal is arriving before positive edge. Therefore, the output clock ‘CLKB’ is
produced without any glitches.
24. Fig23. Clock Output without any glitches.
Similarly,fornegative clockedge,the enable signal shouldarrive atnegative clocklevel.If the enable
signal goeslowat positive clocklevelthenoutputcontainsglitches.Here,the negativeedge arrivesearly
than desired.The Fig20showsthe glitchyoutputobtainedwhennegative edgetriggerisappliedtoflip-
flop.
25. Fig24. Glitchy Output for negative clock edge
Therefore,itprovesforbothpositiveclockedge andnegative clockedge, the gated signal should arrive
at the negative clock level. This is about clock gating setup analysis but it is essential to perform hold
analysis to ensure the gated signal arrives at the correct instant.
Hold Check
The hold check says the data should arrive after some time after the active clock edge. In gated clock,
the gated signal should arrive after active edge otherwise the AND gate produces glitches which
produces undesirable output. Therefore, gated check is required to avoid such timing violation.
In positive edge triggeredflip-flop, if the gated signal arrives prior the negative edge, than it results in
glitchyoutput(same asFig18) causingundesirable behavioral.Therefore, the gated signal should arrive
afternegative edge andbefore positive edge. This ensures that the AND gate output is glitch free. The
Fig19 exhibits that the enable signal should arrive after negative edge.
Similarly, atnegativeclockedge,the signal shouldarrive afternegative clockedge otherwise itresults in
glitches. The Fig20 depicts the glitch produced if the signal arrives after positive edge. Similarly, the
gated check can be performed for OR function present in the circuit. The next section deals with the
asynchronous signals like reset present in the circuit.
26. Recoveryand Removal Timing check
Fig25. Circuit with asynchronous reset
Considerthe circuitdiagramshowninFig25 that showsthe reset signal is asynchronous with respect to
clock.Asynchronousresetmeanswheneverthe resetsignal isapplied, the flip-flop resets even though
clock signal has not arrive. The asynchronous reset waveform is shown in Fig26.
Fig26. Asynchronous Reset
27. Now,if the resetsignal arriveswithinthe restrictedwindow (shown in Fig6) then the flip-flop enters in
metastable state for unbounded time interval. Fig27 depicts the circuit entering into metastable state
whenresetarriveswithin the restrictedregion. Therefore, the output produced is between logic 1 and
logic 0. Therefore, the asynchronous signals like reset, set, clear, preset and so on should not arrive
within the restricted region.
Fig27. Asynchronous Reset causing metastability
28. Removal TimingCheck
A removal timing check ensures that there is sufficient time between an active edge and an
asynchronoussignal. Considerthe circuitshown in Fig25. The reset signal is asynchronous with respect
to clock which may cause timing violation. Therefore, the removal timing check ensures that a signal
shouldremainstable till removal time after the active clock edge (shown in Fig28). This helps to avoid
metastability. This check is similar to hold time check.
Fig28. Removal Time Check
29. RecoveryTiming Check
The recoverytimingcheckand removal timingcheck contradicteachother.It ensuresthe asynchronous
signal arrivespriorthe active clockedge arrives.Inotherwords,thischeck ensures that there is enough
time to recoversothat the nextedge becomesactive. Here, recover means the circuit requires time to
respond to the active clock edge. Therefore, the reset signal should arrive sufficient time before the
edge arrives (shown in Fig29). This check is similar to setup analysis.
Fig29. Recovery Time Check
Thisis aboutrecoveryandremoval timingcheck.The nextsectiondescribesaboutanothertiming check
calledashalf cycle paths.The half cycle pathsare rarelyfoundinthe logicdesign.One such example for
half cycle path is SDRAMcontroller where both the clock edges are used. This check is useful to avoid
half cycle timing violation.
30. Half Cycle Check
The half cycle path is generallyfound when both the clock edges are used in the design. This path may
existfroma risingedge toa fallingedge orvice versa.Fig30showsthe half cycle path where fallingedge
islaunchingthe data andrisingedge istriggeringthe capture flip-flop.Since single cycle is used for both
launchingandcapturingthe data therefore the setuptimingcheckiswithrespecttorisingedge whereas
hold time check is with respect to falling edge (Fig31).
Fig30. Circuit working on both clock edges (Negative edge and Positive edge)
Fig31. Half Cycle Path Timing Check
As shown in Fig31 the data should remain stable at least for flip-flop hold time. Also, the data should
become stable before the capture edge arrives.Therefore,the design consumes half cycle that helps in
increasing the clock frequency.
The paper dealswithdifferent timingchecks andtherefore the next section describe about the latches
usedinthe design.Inthischeckthe latchtiminganalysisisperformedtoensure itdoesnot produce any
glitch. This check explains that latches can be used in the design to improve performance.
31. Latch in TimingAnalysis
Generally,itisadvisedthatlatchesshouldbe avoided inthe design because they are not synthesizable.
But sometimes latches are useful because they help in increasing the clock frequency. This section
explains how latches help in improving the circuit performance.
Fig32. No Time Borrowing
Consider a circuit shown in Fig32. It has huge logic delay in between two flip-flops. This logic delay is
responsible for degrading the circuit performance. In Fig32, the 12ns logic delay reduces the circuit
frequency. Therefore, in order to increase the frequency the latch is placed in between two flip-flops
(Fig33).The latch worksat positive clocklevel.The launchflip-floplaunchesinputatpositiveclock edge.
At thisedge,the latchisclosed(Fig34) and therefore, any change at latch input will not affect the latch
output. Therefore, the capture flip-flop can capture the data safely.
Fig33. Use of latch to reduce logic delay
32. Fig34. Working of Circuit in Fig33
At the negative clock edge, the launch flip-flop stops accepting the input. At this edge, the latch
launchesthe newoutputgenerated after 7ns delay and becomes stable before the next positive edge
arrives.Here,the dataconsumed7ns plusthe latchdelayto reachat point‘c’.It took about 5ns plus the
slave delaytoarrive at the capture flip-flopoutput.Therefore,the launch flip-flop borrowed time from
latch to reduce the logic delay.
33. Along with the different types discussed, many other types exist such as multicycle paths, multiple
clocks, false path timing check in the circuit and many more. In multicycle path, the reg-to-reg path
consumesmore thanone cycle to capture the data. In multiple clock timing check, two different clocks
are required to drive flip-flops in reg-to reg path. In this type, one clock drives launch flip-flop and
second clock drives capture flip-flop. In this paper, timing analysis with single clock is explained. The
next section is about different conditions that affects logic delay in the circuit.
Process-Voltage-Temperature (PVT) Variations
The timinganalysistypesassumedthe logicgates introduces logic delay in the circuit. Therefore, more
logicgatesin the pathincrease the delay whereasfewergates in the path reduce the delay. In real life,
the chips are affected with process, voltage and temperature variation that affect the delay in the
circuit. For example, the circuit with hundred gates may possess less delay than the circuit with fewer
gates. Therefore, this section deals with the PVT variations that affect the circuit performance.
Process
The process indicates the technology or the channel length like 90nm, 45nm, 22nm and so on. These
valuesrepresentthe lengthbetween MOSFETsource anddrain.These processesplayasignificantrole in
affecting the delay in the circuit. Consider the circuit shown in Fig35.
Fig35. Process vs. Delay
34. In Fig35, the supply voltage and the output capacitance are kept constant whereas the channel length
varies. The channel possesses some resistance which limits current flow through the transistor. As a
result,the outputcapacitorconsumestime to produce the output. As the channel length increases the
channel resistance alsoincreases(Fig36).Forexample, the 90nm process possesses more resistance as
comparedto 45nm. Therefore,the 90nm process consumes more time to produce output with respect
to 45nm keeping the output capacitor constant. Therefore, the large nodes increase the delay.
Therefore, it is vital to use the technology as small as possible.
Fig36. Resistance vs. Length
35. Voltage
Consider the circuit (Fig37) where channel length is constant but the supply voltage (Vdd) varies. The
highervoltage source cansupplylarge current whereas the low supply voltage can supply less current.
Therefore, the large supply voltage can charge capacitor at faster rate as compared to low supply
voltage.Consequently,the formersupplyconsumeslesstime toproduce the outputin comparison with
low supply voltage. Therefore, the delay reduces with increase in power supply.
Fig37. Voltage supply vs. Delay
36. Temperature
Alongwithvoltage andprocessvariations,temperature variationsgreatlyaffectcircuitdelay.Consider a
metal wire underhightemperature.Astemperatureincreases,the atomsvibrate vigorously. Therefore,
the electronscollisionrate withthe vibratingatomsincreaseswhichresultsinlesselectronspropagating
through the metal wire. Since electrons are responsible for current flowing in the device, current
decreases with increase in temperature.
A similarphenomenonisobservedintransistors.The channel issimilartometal wire whose currentflow
decreases with increase in temperature. Due to decrease in current flow, more time is required to
charge the capacitortherebyincreasingthe circuit delay. Therefore, at higher temperatures the circuit
delay is high and at lower temperatures the circuit delay is small.
This discussion proves the Process-Voltage-Temperature variations are responsible for increasing or
decreasingthe circuitdelay. The STA engineers have to perform timing analysis repeatedly in order to
ensure the circuit performance is maintained. It is essential to make the chip work in extreme
temperatureslike-40to +150 degreesaswell aswithdifferent voltage ranges from 0.9 V to 1.1 V. From
above discussion,itisprovedthatthe bestconditionforminimumdelayismaximumvoltage, minimum
temperature and best technology whereas the worst condition is minimum voltage, maximum
temperature and worst technology.
The above discussion provides information regarding delay due to process, voltage and temperature
variations.The timinganalysisisperformedtoensure the circuitworksproperlyevenif these variations
occur. This analysis is performed at various stages in VLSI design flow. For example, it is performed
duringsynthesistocheckwhetherthe circuitmeetsthe setup and hold condition. Similarly, in physical
designstage,interconnectorwire (usedtoconnectdifferentlogicgates) introducesdelay which affects
the circuit performance. Therefore, it is essential to check setup and hold violation.
Even if timing violation occurs, it is important to identify at early stage in the design cycle. It is not
impossible toavoidtimingviolationcompletelybutfew wayscanbe implemented to reduce them. The
following section provides ways to improve timing for any given circuit.
37. Solutions
Pipeline
The huge logic delay between two flip-flops reduces the clock frequency. Therefore, the delay is
distributedinmanystagestoimprove the circuitperformance.The phenomenoninwhich the flip-flops
inserted in between the logic to optimize the long path in the circuit is called pipelining.
Fig38. Circuit without pipelining
Fig39. Pipelined Circuit
38. Synchronization
In Fig38, betweenthe input‘c’ and the multiplier three flip-flops are inserted to match the timing. For
example,considerthe inputsgiveninFig33are a = 2, b=5 and c=5. The capture flip-flop produces ‘75’ as
output.Here,the inputsappliedtomultiplierandadderblocksshouldreachatcorrect instantotherwise
the circuit will produce incorrect results.
Therefore,afterpipeliningaswell,the inputsshould reach at correct instant to produce correct output.
In Fig39, aftereachlogicblocka flip-flopisinsertedtoreduce the critical pathbetweentwoflip-flops.As
a result, the inputs ‘a’, ‘b’ and ‘c’ are not synchronous with each other resulting in wrong output.
Therefore, the input ‘c’ is flopped thrice to make all inputs synchronous with each other. This aid in
improving the critical path as well as the synchronization problem is avoided.
ComplexCells
Fig40. Complex cells
Ratherthan usingcircuitwithmore logiclevels (Fig40), use a complex gates to reduce the interconnect
delaybetweenthe logicgates.Therefore,the loadcapacitance after every logic cell is reduced thereby
decreasingthe delaybetweeninputandoutput.Therefore,the synthesizerusescomplexcellsto reduce
delay in the design.
Many such waysare usedto fix timingviolationsuchasreduce clock frequency, insert high speed cells,
Interfaces and many more. The important observation is that the setup and hold condition are
contradictoryto eachother.Therefore,itisalwaystradeoff betweenthesetwochecksasthe conditions
contradict each other. Therefore, it is crucial to check for both checks after solving one issue.
39. Conclusion
Therefore, concluding this, the timing analysis is an important analysis in VLSI design flow. The circuit
has the tendencytoproduce wrong results withoutthisanalysis. Therefore,thisanalysisisperformedto
avoid undesirable output. This analysis is not limited to reg-to-reg path but it also includes input-to-
output,reg-to-output, half cycle path, clock gating path and so on. All these analysis are performed to
ensure the circuit works properly in all possible conditions.
References
1. http://www.vlsi-expert.com/p/static-timing-analysis.html
2. BhaskerJ. andChadha Rakesh, Static TimingAnalysis – A practicalbook for nanometer design,
SpringerPublications,2009
Blog
To perform timing analysisin given circuit,it is importantto understandthetiming paths present in thecircuit.
Timing Paths
The circuitdiagramgiven aboveshowsthetimingpathsin thesequential circuit.
40. 1. The combinationalpath betweenany two flip-flopsis reg-to-reg path.
2. The path fromchipinputtill thefirst flip-flopinputis calledinput-to-reg path.
3. The path fromflip-flop till thecircuit outputis calledreg-to-outputpath.
4. The combinationalpart excluding the registers in thecircuit is calledinput-to-outputpath.
Basic Terms -
1. Logic Delay- The combinationallogic (NAND, XOR, NOR, etc. gates and MUX, DECODERS and so
on) introduces produces outputafter someamount oftime.
2. Long Path - The maximumdelay introducedby a pathin the combinational logic is calledLong Path
(Critical Path).
3. Short Path - The minimumdelay introducedby a path in thecombinational logic is calledShort
Path.
