An overview of Floor Planning and power plan stages of Physical Design Flow

1. FLOOR
PLANNING

2. What is floor plan?
• First step in the Physical Design flow
• Floor planning is the process of determining the Macro
placement, power grid generation and I/O placement.
• Floor planning involves
• Defining the size of the chip or block,
• Pre-placing hard macros,
• IO pads and other desired objects and
• Defining a power grid for the design.
• Placing Blocks/Macros in the chip/core area, thereby
determining the routing areas between them.
• All stages like placement, routing and timing closure are
dependents on how good is your floorplan.
• A bad floor-plan will lead to waste-age of die area and
routing congestion.

3. Goal of Floor Plan
 Partition the design into functional blocks
 Arrange the blocks on a chip
 Place the Macros
 Decide the location of the I/O pads
 Decide the location and number of the power pads
 Decide the type of power distribution

4. Floor plan Inputs:
• Synthesis Netlist
• Physical Libraries
• Logic Libraries
• Timing constraints
• Power requirement
• Floor planning control parameters.

5. • Synthesis Netlist: A netlist is a description of the connectivity of
an electronic circuit. In its simplest form, a netlist consists of a list of
the electronic components in a circuit and a list of the nodes they are
connected to. It can be in the form of Verilog or VHDL. This netlist is
produced during logical, synthesis, which takes place prior to the physical
design stage.
• Physical Library: Physical/Reference libraries contains physical information
of standard, macro and pad cells, which is necessary for placement and
routing. These libraries define placement file like height of placement rows,
minimum width resolution, preferred routing direction, pitch of routing tracks
etc.
• Logical libraries: This library file which provides timing and functionality
information an each and every standard cells used in the design. It also
provides timing information of hard macros such as IP, ROM, RAM etc.
• Timing Constraints: SDC constraints. Clock constraints - max skew, max
and min insertion delay, no. of clock domains, clock start points (whether port
level or internally generated)
• Power Requirement: Power & Ground nets.
• Floor planning control parameters: Die size estimation, core size, aspect
ratio, core height, core width.

6. Inputs files
• Netlist: Logical file
• Libraries:
(i)Physical: Technology LEF & Physical LEF
(ii)Timing:-fast & slow libraries
• SDC: clock constraints
• IO file: IO pins info (Optional)
• Macro placement file(Optional)

7. • Netlist: You can get a gate level netlist from post
synthesis
• Physical Libraries:
Physical LEF: format is .lef (Layout Exchange Format):
It includes,
Physical information of std cells, macros, pads.
Pin information.
Define unit tile(sites) placement.
Minimum Width of Resolution.
Height of the placement Rows .
Preferred routing Directions.
Pitch of the routing tracks.
Antenna Rules.

8. PhysicalLEF continues……
Macro/Std Cells : Cell name
Size(Dimensions, Area)
Pin
Port
Layer
Direction
Pins information : Direction(Input, Output, INOUT)
Use(Signal, Power, Ground)
Antenna Gate Area
Layer
Library information can be included in a single LEF file. This creates a
large file that can be complex and hard to manage. So, it can be divided
into 2 files.
Technology LEF &
Cell Library LEF

9. Technology LEF:
Almost all physical synthesis and place-and-route tools operate
based on the technology file. Technology files contain information or
commands that are used to configure structures, parameters (such as
physical design rules and parasitic extractions), and limits of an ASIC
design targeted to specific process technology.
A technology file is provide by the technology vendor.
Technology file is unique for each technology. Technology file contains
the information related to metal/vias information such as,
Units & precision for electrical units(V, I and power),
Define colors and patterns of layers for displays,
Number & name designations for each metal/vias,
Physical & electrical characteristics of each metal/via,
Define design rules such as min. wire width & min. wire to wire
spacing,
Contains ERC rules, Extraction rules, LVS rules,
Provide parameterized cells for MOS capacitance,
Create menus and commands.

10. Tech LEF continues…
• Technology rule basics are as follows:
Manufacturing grid
Routing grid
Standard cell placement tile
Routing layer definition
Placement and routing blockage layer definition
Via definition
Conducting layer density rule
Metal layer slotting rule
Routing layer physical profile
Antenna definition

11. • Logical Library: These are lib files for the macros and the
standard cells . These contains,
Area
Internal power
Functionality
Capacitance and
Timing details at each pin of every cell.
These are required for the tool to do placement and
routing depending on all these factors
• SDC: This file contains the “synopsis design constraint” for
that particular design. It contains, input and output delay of
pins of each cell in the design and clock constraints. This helps
tool to place and route the cells depending on these constraints.
This is obtained from the front end designers.

12. CLOCK DEFINITIONS:
• Create Clock Period.
• Generated Clock Definitions
• Input Delay
• Output Delay
• I/O delay
• Max delay
• Min Delay
EXCEPTIONS
• Multi cycle path
• False path
• Half cycle path
• Disable timing arcs
• Case Analysis
• Multi cycle path, False path are Exceptions.

13. AND IT ALSO CONTAINS..,,
• Clock latency
• Clock Uncertainty
• Clock Transition
• Clock Gating setup
• Clock Gating Hold
• Clock Driving cell
• IO File:
It contains pad information like,
 Type of pads signal/power and its orientation (R0, R90, R180, R270),
 Side information like Top Left Bottom and Right and
 Physical pad information like corner pads, ESD pads etc
• Macro File:
This file contains cell information,
Cell Size, Cell site, Core type, Orientation,
Cell pin/port info like input/output/Feedthrough,
Type of port signal/power-ground and
OBS information like cell routing blockages and pin blockages.

14. Sanity Checks:
Data validation is done at this stage. It checks whether the input files received are
correct or not.
Validation includes
• Library mismatches
• Nets with assign statements (All Assign statements should be converted to
buffers)
• Black Boxes in netlist
• Checking timing constraint syntax
• Unsupported constraints
• Ignored timing constraints
• Resolving Footprint inconsistencies
• Creating and loading footprints correctly
• Making sure that library cells have same names as their footprint definitions.
• Making sure that all buffer cells for optimization are defined in footprint.
• Validating Floor plan
• Check for overlapping of blocks
• Place the design with out any issues
• By rough placement with low effort check for congestion presence.

15. • Before starting the Physical Design We first have to import the
design and associated libraries.
• LEF File :Contains layer, via and macro definition
• LIB File (.TLF): This file has timing information e.g. delay
and capacitance
• Verilog Netlist
• Netlist file generated by Synthesis Tool
• SDC File (Synopsys Design Constraints Format)
• Constraint file generated by synthesis tool
How to start?

16. Die Size Calculations
• Aspect Ratio
• Die area
• Core area
• Utilization
• Core to IO distance
Core area depends on aspect ratio and utilization.

17. Die Estimation

18. Aspect Ratio
• The Aspect Ratio of Core/Block/Design is given as:
• The Role of Aspect Ratio on the Design:
• The aspect ratio effects the routing resources available in the design
• The aspect ratio effects the congestion
• The floor planning need to be done depend on the aspect ratio
• The placement of the standard cells also effect due to aspect ratio
• The timing and there by the frequency of the chip also effects due to
aspect ratio
• The clock tree build on the chip also effect due to aspect ratio
• The placement of the IO pads on the IO area also effects due to aspect
ratio.

19. • The packaging also effects due to the aspect ratio
• The placement of the chip on the board also effects
• Ultimately every thing depends on the aspect ration of
core/block/design.
• The all the points are drawn attention in future articles

20. Utilization
The area occupied by standard cell, macros and
blockages. In general 70 to 80% of utilization is fixed because
more number of inverters and buffers will be added during the
process of CTS (Clock Tree Synthesis) in order to maintain
minimum skew.
Core utilization = (standard cell area+ macro cells area)/ total core
area.
A core utilization of 0.8 means that 80% of the area is
available for placement of cells, whereas 20% is left free for
routing.
Target utilization: Represents the size of module, fence, region.
Effective utilization: Represents placement utilization of
module, fence, region, partition. It says about the percentage of
area being occupied by standard cells, blocks.

21. Core rows:
• Core rows are rows formed on core with spacing of the standard
cell height.
• Standard cell height differs from technology to technology.
• That is taken from the standard cell LEF file (gives all the physical
information of the components like standard cells, hard macros,
metals, etc.,).
Concepts of core
rows:
Every alternative
row is flipped to
change the row
orientation.
Doing above allows
pairs of standard cell
rows to share power
and ground stripes.

22. • Row spacing:
• Determines the amount of routing resources between rows.
• Normally zero row spacing is used is the design is not too
congested.
• A non zero row spacing value can be used to reduce
congestion in a more congested design.

23. Design types
• Pad limited design:
• When pad width is greater than
the sum of core width and the
core margin, the die size is
decided by the pads.
• Core size is small, but the I/O
count is proportionally high; this
results in under-utilized die area,
which can drive up cost.
Die size is decided in two ways:
Core limited design
Pad limited design

24. • Core limited design:
• When pad width is less than the sum of core width and the core
margin, the die size is decided by the core.
Pad
Width
Pad Limited Die Vs Core
Limited Die:
On a pad-limited die we use tall, thin
pad-limited pads , which maximize the
number of pads we can fit around the
outside of the chip.
On a core-limited die we use short,
wide core-limited pads.
One set of VDD/VSS pads supplies
one power ring that runs around the pad
ring and supplies power to the I/O pads
only.
Another set of VDD/VSS pads
connects to a second power ring that
supplies the logic core

25. IO Placement
• IO pin placement
• IO pad placement
While fixing the location of the pin or pad always consider
the surrounding environment with which the block or chip
is interacting. This avoids routing congestion and also
benefits in effective circuit timing.
Provide sufficient number
of power/ground pads on
each side of the chip for
effective power distribution.
In deciding the number of
power/ground pads, Power
report and IR-drop in the
design should also be
considered

26. Macro Placement Guidelines
• Macro placement according to flight lines i.e,
• Macro to IO
• Macro to macro
• Macro to standard cells
• Ports communications.
• Macro's are placed at boundaries
• Macro grouping [logical hierarchy]
• Spacing between macro's
• Macro alignment
• Notches avoiding
• Orientation
• Blockages
• Avoid criss-cross placement of macros

27. Interconnections between the macros (An Example)
Inefficient floor plan Efficient floor plan

28. Types of Macros
 Soft Macros: Have fixed functionality (at the RTL level) but
the gate-level implementation and physical layout are still to
be determined.
 Firm Macros: Have a gate level implementation but no
physical layout.
 Hard Macros: Are fully implemented all the way through to
the physical layout.

29. Tips for macro Placement
/Floor planning :
1. Place macros around chip periphery.
2. Consider connections to fixed cells when placing
macros.
3. Orient macros to minimize distance between pins.
4. Reserve enough room around macros.
5. Reduce open fields as much as possible.
6. Reserve space for power grid.

30. Types of blockages
• Placement & Routing
• Hard
• No cells allowed.
• Soft
• No standard cell is allowed except buffers and
inverters.
• Partial
• Any cell can be placed but with some percentage
priority in that blockage area i.e, eg: 50% or 30% etc,.
• Create standard cell placement blockage at the corner of the
macro because this part is more prone to routing congestion.
• Also create standard cell placement blockage in long thin
channel between macros.
• When blockages overlap, hard blockages have higher priority

31. Macro 1 Macro 2
Hard blockage prevents
standard cells from being
placed in this region.
Soft blockage allows new
buffers/inverters to be inserted
during optimization.
Hard placement blockage
Soft placement blockage

32. HALO
• It’s the region around the boundary of fixed macros in
design in which no other macros or standard cells can be
placed. It allows placement of buffers and inverters in its
area.
• If the macros are moved from one place to another, halo
will also be moved.

33. Module Types
• Soft modules are placed according to the requirement.
• Design may require to place the cells in certain module in a
constrained place for better performance.
• Fragmentation of placement and routing blocks should be
considered.
• If not this may lead to placement of cells other than those in
soft modules in the fragmented area in turn leading to long
wire lengths.
• Size and shape the soft modules for better floor plan.
• Various types of modules:
• Guide
• Fence
• Region

34. • Guide:
• Guide is assigned with certain cells (standard
cells or macros) in the design.
• Allows the cells assigned to it to move outside if
required.
• Allows the other cells to sit inside it.
• Soft constraint.
• Region:
• Region is assigned with certain cells (standard
cells or macros) in the design.
• Does not all the cells assigned to it to be placed
outside.
• Allows the other cells to sit inside it.
• Soft constraint.
• Fence:
• Fence is assigned with certain cells in the design.
• Does not allow other cells inside.
• Does not allow the cells assigned to it outside.
• Hard constraint.

35. Physical cells
• Well taps
• End caps
• Filler cells
• De-cap cells
• Tie cells

36. Tap cells
• Well taps are inserted in design to prevent latch-up.
• Well tap cells are used to limit resistance b/n power and ground
connections to wells of substrate.
• Taps are used so that vdd and gnd are connected to substrate
and n wells respectively.
• The rules for Well taps and End caps are technology dependent
and need to have well tap for every X microns. And end caps at
every edge of std cell row.
• Placement of tap cells

37. End cap cells
• These cells do not have cell connectivity as they are only
connected to power and ground rails, thus to ensure that gaps
do not occur between well and implant layer and to prevent the
DRC violations by satisfying well tie-off requirements for core
rows.
• In the design power domains(voltage islands) and row
orientations will end here.

38. Filler cells
• Filler cells are used to establish the continuity of the N-
well and the implant layers on the standard cell rows.
• In those cases, the abutment of cells through inserting
filler cells can connect those substrates of small cells to
the power/ground nets. i.e. those thin cells can use the
bulk connection of the other cells.
• Used to fill empty space between cells and used to
complete the connection of power and ground rails
• Aligns the width of each row of standard cells.

39. Tie cells
• It is used for preventing Damage of cells; Tie
High cell(Gate One input is connected to Vdd,
another input is connected to signal net);Tie
low cells Gate one input is connected to Vss,
another input is connected to signal .
• Tie - high and Tie - low cells are used to
connect the gate of the transistor to either
Power and Ground.
• In lower technology nodes, if the gate is
connected to Power or Ground. The transistor
might be turned "ON/OFF" due to Power or
Ground Bounce.
• These cells are part of the std cell library.
• The cells which require Vdd(Typically
constant signals tied to 1) connect to tie high
cells.
• The cells which require Vss/Vdd (Typically
constant signals tied to 0) connect to tie low
cells.

40. De-cap cells
• Charge Sharing; To avoid the Dynamic IR drop ,charge
stores in the cells and release the charge to Nets.
• Decoupling capacitor cells or De-cap cells, are cells
that have a capacitor placed.
• Between the Power rail and Ground rail to Over come
Dynamic voltage drop.
• Dynamic IR Drop happens at the active edge of the
clock at which a High currents is drawn from the
Power Grid for a small Duration.
• If the Power is far from a flop the chances are there that
flop can go into Metastable State.
• To overcome de-caps are added , when current
requirements is High this De-caps discharges and
provide boost to the power grid.

41. Power Planning
• Power planning is a step which typically is done with floor
planning in which power grid network is created to distribute
power to each part of the design equally. Power planning can
be done manually as well as automatically through the tool.
Deal with Power Distribution Network
• Three levels of Power Distribution,
• Rings
• Carries VDD and VSS around the chip
• Stripes
• Carries VDD and VSS from Rings across the chip
• Rails
• Connect VDD and VSS to the standard cell VDD and VSS.
• Power planning is also called as the pre-routes because in the
chip power nets are routed first.

42. • Power Pads
• Power pads supply power to chip and is connected to power rings.
• Power Rings
• Carry power around periphery of the die, a std cell core area and
individual hard macros.
• Typically the power rings are put in higher layers to leave lower layers
for signal routing.
• In present designs these power rings are coming with IO pads, so these
rings are not seen in core
• From pads the power is connected to Horizontal and Vertical stripes.
• Vertical and Horizontal Straps
• Power rails, straps and trunks cross the entire die or sections of die.
• The Horizontal wires are often referred as strap and while the Vertical
referred as trunks.
• The straps and trunks typically uses widest and higher routing layers.
• Typically uniformly distributed across the die to have minimum IR
drop.
• User will specify the width and spacing of power grid.
• The power rail connects standard cell power pins together and then
extend to the power rings.

43. • Macro Power Ring
• Analog macros like usb, plls etc powering has to be taken care.
• These powering has to be routed with same pin width and should be
tapped to local PG Mesh
• Plls PG connectivity is differ from power domains. Each port has to
be connected to reference domain.
• If separate PG required we need to draw power rings around the
macro to have strong pg connection.
• Power domain Creation
• If design is operating with multiple power domains we need to create
power domains in design.
• Few cells cross signals from one domain to another domain for this
type of cells we need to create power domains and need to place these
cells in those domains.
• level shifter cells and always on cells need to be placed in particular
domains based on domain information.

44. • Std cell rails
• These rails are used to power standard cells in Design.
• VDD and GND rails can be shared by abutting std cell rows.
• Std cell are connected to these rails by using follow pins.
• Basically std cell follow pins are in M1 or M2
• These routing is done by tool based on technology information
provided.
• Power ring calculations
• Inputs
• Total power dissipation (Pchip in mw)
• Routing layers for power grid
• Max Current density of metals (Rj (ma/microns))
• This info we get from tech lef
• Input Voltage (volts)
• Width of perimeter ring
• Current per side

45. Power planning terminology

46. Power calculations
• Number of the core power pad required for each side of
chip=(total_core_power)/{(number_of_side)*(core_volta
ge)*maximum allowable current for a i/o pad)}
• Core ring width:
• Total ring width = [total current / Metal density]
• Ring width for side = [total ring width / 4]
• Stripe width:
• Total stripe width = [ total current / (2 * Metal density) ]
• Stripe width = [ total stripe width / side of square ]
• No of sets = [side of the square / set to set distance]

47. Power plan components
Global Net connections
Adding a core ring
Adding a block ring
Adding stripes to the core area
Adding stripes over blocks within the design
Connecting pad pins
Connecting block pins
Routing standard cell pins

48. Floor plan Terminology

49. Challenges in Floor Plan
Die Area
Congestion
Timing
Power network design
Electro-migration
IR Drop

50. Floor plan Outputs:
• Die/block Area
• I/O placed
• Macros Placed
• Power Grid designed
• Power Pre-routing
• Standard Cell Placement Areas