JSS ACADEMY OF TECHNICAL EDUCATION
FPGA IN OUTER SPACE
RAHUL KUMAR VERMA
ELECTRONICS AND COMMUNICATION ENGINEERING
A quiet revolution is taking place. Over the past few years, the density of the
average programmable logic device has begun to skyrocket. The maximum number
of gates in an FPGA is currently around 500,000 and doubling every 18 months.
Meanwhile, the price of these chips is dropping. What all of this means is that the
price of an individual NAND or NOR is rapidly approaching zero! And the
designers of embedded systems are taking note.
The line between hardware and software has blurred. Hardware engineers create
the bulk of their new digital circuitry in programming languages such as VHDL
and Verilog and often target it to CPLDs and FPGAs.
As this trend continues, it becomes more difficult to separate hardware from
software. After all, both hardware and software designers are now describing logic
in high-level terms, albeit in different languages, and downloading the compiled
result to a piece of silicon. Surely no one would claim that language choice alone
marks a real distinction between the two fields.
I owe my sincere gratitude to my supervisor, Mrs. Suvarna N.A. (Assistant
professor, < Department of ELECTRONICS AND COMMUNICATION>,
JSSATE-NOIDA) who has constantly given me the encouragement, technical
guidance and moral support throughout my thesis work.
I would like to extend my heartfelt thanks and lifelong indebtedness to
Prof.Dinesh Chandra (HOD, Department of EC, JSSATE-NOIDA) for his
technical and moral support.
4.2. High level language………………………………………..17
5.Modern Development Of FPGA…………………………...…17
5.1.The Xilinx Virtex-6 FPGA family……………………...……18
6.FPGA in Comparison To Other logic Devices…………….....19
7.1.Outer Space Application……………………………..20-21
7.2.FGPA-Based Development ……………………………...22
for Defenseand AerospaceApplications
7.2.1FPGA-Based COTS Boards……………...………………22
7.2.2 The FPGA Developers Kit………………...……………...23
8.Future Scope Of FPGA Technology……………………….…24
1. INTRODUCTION TO FPGA
FPGA stands for Field Programmable Gate Array. An FPGA is an integrated
circuit (IC) that can be programmed and configured by the embedded system
developer in the field after it has been manufactured. FPGA is a semi-conductor
device which is not limited to any pre-defined hardware function; it is rather highly
flexible in its functionality and may be configured by the embedded system
developer according to his design requirements.
FPGAs use pre-built logic blocks and programmable routing channels for
implementing custom hardware functionality depending upon how embedded
system developer configure these devices. The FPGAs are programmed and
configured using hardware description languages (HDL) like Verilog and VHDL,
similar to that used for an application-specific integrated circuit (ASIC).
FPGAs give a lot of flexibility to the embedded systems developer to program
features and functions of their FPGA based product even after the FPGA based
product has been installed in the field. This is the reason why FPGA is termed field
programmable, as FPGA may easily be reconfigured and reprogrammed in the
field according to new features and end-user’s requirements. FPGAs are being
widely used in digital electronic circuits and embedded systems design and FPGAs
have a well-defined place in every embedded system developer’s toolbox.
FPGAs may be used to implement any logical functions and features that an
Application-Specific Integrated Circuit (ASIC) could possibly be utilized to
implement. But in terms of flexibility of upgrading and modifying the functionality
and features of FPGAs, even after the FPGA based product has been shipped to the
end-user, FPGAs really have an edge over ASIC.
1.1. Field Programmable Gate Array
Field Programmable Gate Array
Field : ―in the field‖
Programmable : ―Re-Configurable‖ Change Logic Functions
Gate Array : reference to ASIC internal architecture
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing—hence "field-
The FPGA configuration is generally specified using a hardware description
language (HDL), similar to that used for an application-specific integrated circuit
(ASIC). Contemporary FPGAs have large resources of logic gates and RAM
blocks to implement complex digital computations.
As FPGA designs employ very fast IOs and bidirectional data buses it becomes a
challenge to verify correct timing of valid data within setup time and hold time.
Floor planning enables resources allocation within FPGA to meet these time
FPGAs can be used to implement any logical function that an ASIC could perform.
The ability to update the functionality after shipping, partial re-configuration of a
portion of the design and the low non-recurring engineering costs relative to an
ASIC, offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"—somewhat like many (changeable) logic gates that can be inter-wired in
(many) different configurations. Logic blocks can be configured to perform
complex combinational functions, or merely simple logic gates like AND and
XOR. In most FPGAs, the logic blocks also include memory elements, which may
be simple flip-flops or more complete blocks of memory.
1.2. History OfFPGA
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of
being programmed in batches in a factory or in the field (field programmable),
however programmable logic was hard-wired between logic gates.
In the late 1980s the Naval Surface Warfare Department funded an experiment
proposed by Steve Casselmanto develop a computer that would implement 600,000
reprogrammable gates. Casselman was successful and a
patent related to the system was issued in 1992.
Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first
commercially viable fielprogrammable gate array in 1985 – the XC2064. The
XC2064 had programmable gates and programmable interconnects between gates,
the beginnings of a new technology and market.
The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-
input lookup tables (LUTs).
More than 20 years later, Freeman was entered into the National Inventors Hall of
Fame for his invention Xilinx continued unchallenged and quickly growing from
1985 to the mid-1990s.
The 1990s were an explosive period of time for FPGAs, both in sophistication and
the volume of production. In the early 1990s, FPGAs were primarily used in
telecommunications and networking.
Ross Freeman and Bernard Vonderschmitt
They invented the first commercially viable field programmable gate
array in 1985
2. Architecture and working
The most common FPGA architecture consists of an array of logic blocks (called
Configurable Logic Block) CLB, or Logic Array Block, LAB, depending on
vendor), I/O pads, and routing channels.
Generally, all therouting channels have the same width (number of wires). Multiple
I/O pads may fit into the height of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs/LABs and I/Os required is easily determined from the
design, the number of routing tracks needed may vary considerably even among
designs with the same amount of logic.
For example, a crossbar switch requires much more routing than a systolic array
with the same gate count. Since unused routing tracks increase the costof the part
without providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs
can be routed.This is determined by estimates such as those derived from Rent's
rule or by experiments with existing designs.
CLB: The Configurable logic blocks are were the user specific functions are
IOB: The Input/Output block make it possible to connect the FPGA to the other
elements of the
Interconnect: Interconnect is essential for writing between CLB and from IOBs
It is composed of a lookup table (LUT) controlled by 4 inputs to implement
combinational logic and a D-Flip-Flop for sequential logic.
A MUX is used to select between using the output of the combinational logic
directly and using the output of the Flip-Flop.
One CLB is programmed by downloading the truth table of the logical function to
the LUT (16bit) and the control bit of the MUX (1 bit). By using multiple copies of
the this structure any combinational and sequential logic circuit can be
Additionally the LUT can also be used as memory.Once the CLB slices have been
configured to implement logical functions they have to be connected
to implement bigger logical function.
In general, a logic block (CLB or LAB) consists of a few logical cells (called
ALM, LE, Slice etc.). A typical cell consists of a 4-input LUT, a Full adder (FA)
and a D-type flip-flop, as shown below.
The LUTs are in this figure split into two 3-input LUTs. In normal modethose are
combined into a 4-input LUT through the lefmux. In arithmeticmode, their outputs
are fed to the FA. The selection of mode is programmed into the middle
The output can be either synchronous or asynchronous, depending on the
programming of the muxto the right, in the figure example. In practice, entire or
parts of the FA are put as functions into the LUTs In order to save space.
ALMs and Slices usually contains 2 or 4 structures similar to the example figure,
with some shared signals. CLBs/LABs typically contains a few ALMs/LEs/Slices.
In recent years, manufacturers have started moving to 6-input LUTs in their high
performance parts, claiming increased performance.
Since clock signals (and often other high-fan-out signals) are normally routed via
special-purpose dedicate routing networks in commercial FPGAs, they and other
signals are separately managed.
For this example architecture, the locations of the FPGA logic block pins are
shown below. Logic Block
2.2Previous generation logic device
Simple Logic (used to ―glue‖ other ICs together)
Reprogrammable (UV light, electrically eraseable)
Easy to Program
Many different variations
Eg. Implement Logic as ‘Sum of Products’ Terms
Large Complex Functions
Customised for Extremes of Speed, Low Power
PLAsPROMs PALs GALs etc.
a b c
a !a b !b c !c
a cb& &
Predefined AND array
w x y
w = (a & c) | (!b & !c)
x = (a & b & c) | (!b & !c)
y = (a & b & c)
Very Hard to Design.
Long Design cycles.
Not Reprogrammable. High Risk
Fig. Block Diagram Of ASIC’S
3. Feature And Characterstics
(a) Single-column arrays (b) Dual-column arrays
Hierarchy Programmable Channels between Logic Elements
Interfaces to the real world. Logic Levels. Fast Serial I/O
4.Massively Parallel Architecture (HEP)
5.Clocked Logic Design
6.CMOS based using SRAM cells for configuration
7.Fast Turnaround Designs
4. FPGA design and programming
FPGAs are not programmed directly. Synthesis tools translate the code into bit
stream, which is downloaded to the configuration memory of the FPGA.
Commonly, hardware description languages (HDL) are use to configure the device.
But resent trends also offer the possibility to high level languages.Furthermore,
there are library based solution which are optimized for a specific device.
4.1. Hardware description language
Using a HDL is the most common approach to configure a FPGA. There
are two dominating languages, VHDL and Verilog. Both languages have the powe
of international standards and working groups behind and are similar powerful.
VHDL was developed in the 1980s.
Verilog was originally a C-like programming language to model hardware and late
became IEEE standard like VHDL. The languages support different levels of
abstraction, but mostconfigurations are done at the register transfer level (RTL).
The design resembles soft development more than hardware development, but
there are big differences. Software programs have a sequential execution model
and the correctness of the program depends on the sequential executed commands.
Decision points are very common. Furthermore, programmer does not have to care
about data flow between registers and memory.
Hardware designs consists of several block of hardware running in parallel. The
designer tries to avoid decision points, because of performance reasons. The wires
for data movement have to be explicitly written on the FPGA.
4.2. High level language
There are also approaches using high level languages that make designing FPGA
application more alike software development.
SystemC is a C++ library that allows to specify and simulate hardware processes
using a C++ syntax.Handel-C is an extended subset of ANSI C that allows
developer to specify their designs with C. It can be synthesized directly for
implementation on FPGAs.WithAccelchip it is possible to generate VHDL or
Verilog code block for common MATLAB DSP functions.
5. Modern Development Of FPGA
Modern FPGAs have additional units that make the design of applications easier
and more efficient. Small memories and arithmetic units are difficult to implement
on CLBs. Therefore modern FPGAs provide embedded memories and embedded
logic blocks for arithmetic calculations. The most common arithmetic calculation
is the multiplication, but many other operations can be provided.
The advantage of embedded logic blocks are better speed and space. Additionally
embedded memories are easier to interface than extern memories. DSP
applications are often good targets for implementation on FPGA. Thus
manufacturer add embedded block to be useful for implementing DSP functions,
The Xilinx 4 family has support for additional operations configured by
the designer and implemented by CLBs with th auxiliary processing unit (APU)
In contrast to embedded processors, soft cores are build directly on the FPGA
fabric. The advantages are that they are configurable and the clock can be the same
as that of the FPGA. Furthermore, soft processor cores are easier to interface. The
big disadvantage is the slower clock rate.
5.1 The Xilinx Virtex-6 FPGA family
Virtex-6 the newest FPGA family from Xilinx. It is divided into the LXT, SXT and
HXT sub-family.Each sub-family contains a different ratio of features to address
the needs of many logic designs:
• Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity
• Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial
• Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity
CLBs possess a LUT which can be configured as one 6-input LUT or two 5-input
LUTs. The LUT also can be used as 64 bit RAM or 2 32 bit RAMs.
Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each
storing 36 Kbits. Each block RAM has two completely independent ports that
share nothing but the stored data.
All Virtex-6 FPGAs have many dedicated, full-custom, low-power DSP slices
combining high speed with small size, while retaining system design flexibility.
Each DSP48E1 slice fundamentally consists of a dedicated 25 18 bit two’s
complement multiplier and a 48-bit accumulator, both capable of operating at 600
Every FPGA of the family contains a System Monitor circuit providing thermal
and power supply status information. Sensor outputs are digitized by a 10-bit
analog-to-digital converter (ADC). This fully tested ADC can also be used to
digitize up to 17 external analog input channels.
All but one Virtex-6 device has between 8 to 72 gigabit transceiver circuits. Each
GTX transceiver is a combined transmitter and receiver capable of operating
at a data rate between 155 Mb/s and 6.5 Gb/s. An integrated Ethernet MAC blockis
easily connected to the FPGA logic, the GTX transceivers,and the
SelectIOresources.All but one FPGAs of the Virtex-6
6. FPGA in Comparison To Other logic Devices
Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays,
even for wide input functions. Use CPLDs for small designs, where "instant-on",
fast and wide decoding, ultra-low idle power consumption, and design security
are important (e.g., in battery-operated equipment).
Security: In CPLD once programmed, the design can be locked and thus
made secure. Since the configuration bitstream must be reloaded every time
power is re-applied, design security in FPGA is an issue.
Power: The high static (idle) power consumption prohibits use of CPLD in
battery-operated equipment. FPGA idle power consumption is reasonably low,
although it is sharply increasing in the newest families.
Design flexibility: FPGAs offer more logic flexibility and more
sophisticated system features than CPLDs: clock management, on-chip RAM,
DSP functions, (multipliers), and even on-chip microprocessors and Multi-
Gigabit Transceivers.These benefits and opportunities of dynamic
reconfiguration, even in the end-user system, are an important advantage.
Applications of FPGAs include digital signal processing, software-defined radio,
ASIC prototyping, medical imaging,computer vision, speech recognition,
cryptography, bioinformatics, computer hardware emulation,radio astronomy,
metal detection and a growing range of other areas.
7.1. FPGAs for Space Applications
Dedicated to providing FPGAstha meet the stringent radiation and quality
requirements of space applications,Actel is the world’s leading supplier of
radiationhardened and radiationtolerant FPGAs. Over the last six years, Actel
devices have been on board more than 100 launches and have been accepted for
flight-critical applications on over 250 satellites.
Actel continues its commitment to the space community with the RTSX-SU and
RTAX-S/SL FPGA families. Designed specifically for space, the RTSX-SU and
RTAX-S/SL products are built on a foundation of hardened latches, eliminating the
need for softwaregeneratedtriple-module redundancy (TMR) or other single-
eventupset (SEU) mitigation techniques.
Xilinxhas increased the radiationhardened specification of its space grade
Virtex-5QV FPGA which is available with greater than 1Mrad(Si) total ionising
dose (TID) capabilities NASA sponsored Jet Propulsion
Laboratory and the University of Michigan will be the first to fly a
production Virtex-5QV FPGA.
The FPGAs are designed and tested to provide protection against SEU,total
immunity to single-event latchup (SEL), high tolerance to TID, as wellas data path
protection from single-event transients (SET).
For example, the Virtex-5QV FPGA configuration memory provides nearly
1,000 times the SEU hardness of the standard cell latches in the
commercial device, while configuration control logic and the JTAG
controller have been hardened with embedded triple module redundancy.
This level of rad-hard performance positions FPGAs as an alternative to
space system designs based on one-time-programmable (OTP) devices or
Virtex-5QV FPGAsare built on a second-generation ASMBL columnbased
architecture and integrate many of the same hard-IP system-level
blocks, such as 36kbit/18kbit block RAM/FIFOs, second generation 25x18
DSP slices, power-optimized high-speed serial transceiver blocks and PCI
Express compliant blocks.
The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices
supporting fixed and floating point operations, and 836 user I/Os
programmable to more than 30 different standards for applications and
ease of interfacing to a wide variety of system components.
7.2. FGPA-Based Development for Defense and Aerospace
FPGA-Based COTS Boards
FPGA-based C OTS boards targeted to the defense/aerospace market often share
certain common elements.
For example, they all provide one or more high-density, high-performance FPGAs,
high-speed serial I/O andhigh-performance memory.
Systems engineers evaluating FPGA boards must address certain challenges. These
include how to add their algorithms to the FPGA and how to simulate the design at
the system level to ensure that these algorithms work. Because FPGA development
can be costly, engineers also must evaluate whether their approach will save time
and money and if the resulting solution will be robust and reliable.
To understand the importance of design tools, it is useful to consider how data is
handled by an FPGA board.
In a typical application, data comes in via a high-speed serial interface and is
stored in SDRAM. This data is then pulled out of SDRAM by the end application
and processed via the customer’s algorithm. Intermediate results are stored in
internal or external SRAM and the final result is decimated to a lower data rate.
The FPGA Developers Kit
For DDR SDRAMs, FPGA designers must confront the challenges of aligning data
and data strobes, tight timingconstraints, signal integrity issues and simultaneously
switching output (SSO) noise. In addition, certaindesign issues can prolong design
cycles or force them to accept reduced performance.
To make matters worse, all of these hurdles become more pronounced at high
frequencies. On a read of datafrom SDRAM, the data is valid for only two to three
nanoseconds. Significant effort is required to latch it reliably inside the FPGA and
then synchronize it with the rest of the logic there.
The FPGA designer is thus faced with significant challenges that may take several
man-months to complete, but that can be solved by using the IP in some FPGA
developers kits.In the ideal FPGA developers kit, all of the high-speed IP provided
is fixed to certain regions within the FPGA.This is done to ensure that all critical
paths meet timing, as well as to confine the overall IP designto a small region of
the chip to minimize logic resources.
Fig.FPGA Developers Kit Spartan-6
8. Future Scope Of FPGA Technology
When people think “summer,” visions of a slower pace, time off and less stress come to
mind. In many industries summer is indeed a time when business slows
downMeanwhile, summer for us at COTS Journal is the time when we hold important
planning meetings where we strategize about the upcoming year—deciding what
technology topics will be important in the next calendar year and how to best cover
It’s when we start putting together our editorial calendar for the following year.
As we looked ahead to where military electronics and embedded systems technology is
moving, over and over again the role of FPGAs kept cropping up.
In a recent study conducted by VDC Research, over one third of the total respondents
who answered that they were considering or already using FPGAs were
military/aerospace respondents. FPGAs have become a game changer as an enabler in
key compute-intensive military applications areas,
On the application side, FPGAs have had the most impact in radar/SIGINT, UAV
payloads and tactical military radios. Modern radar systems are operating over an ever
increasing frequency range. Analog conversion technology—both A/D and D/A
converters—is also feeding the radar needs of the military.
High-end military data acquisition is yet another area where FPGAs are playing a
central role. Military system designers face serious challenges when trying to move
signal data in ever-increasing volumes.
Importance of FPGAs is by no means a new phenomenon in military electronics. In a
way, the increasing role of FPGAs is in keeping with the idea that the definition of
“system” has changed. A system once meant simply a rack of board-level systems. Now
that same functionality can be incorporated in a few FPGAs. But as we look into
our crystal ball at the year ahead, they seem to be headed for a new plateau. So, while
you won’t necessarily see the word “FPGA” in every section topic of our upcoming 2010
Editorial Calendar, rest assured that this critical technology area will somehow get
weaved into a majority of them
9. Major Manufacturers
Xilinx and Altera are the current FPGA market leaders and long-time industry
rivals.Together, they control over 80 percent of the market.
Both Xilinx and Altera provide free Windows and Linux design software which
provides limited sets of devices.
Other competitors include Lattice Semiconductor (SRAM based with integrated
configuration Flash, instant-on, low power, live reconfiguration), Actel (now
Microsemi, antifuse, flash-based, mixed-signal), SiliconBlue
Technologies (extremely low power SRAM-based FPGAs with optional integrated
nonvolatile configuration memory; acquired by Lattice in 2011),
In March 2010, Tabula announced their FPGA technology that uses time-
multiplexed logic and interconnect that
claims potential cost savings for high-density applications.
We have presented a survey of field-programmable devices, describing the basic
provides the programmability and a description of many of the architectures in the
We believe that over time programmable logic will become the dominant form of
design and implementation. Their ease of access, principally through the low cost
of the devices,
makes them attractive to small firms and small parts of large companies. The fast
turn-around they provide is an essential element of success in the market. As
CAD tools improve, the disadvantages of FPDs compared to Mask-Programmed
Gate Arrays will
lessen, and programmable devices will dominate.
"To improve affordability and flexibility of our space systems, we are
currently engaged in substantive efforts to insert space qualified FPGA
reconfigurable technology into future missions," said Craig Purcell, (advanced
global comms programme director at Lockheed Martin Space Systems).
1. Wisniewski, Remigiusz (2009). Synthesis of compositional microprogram
control units forprogrammabledevices.ZielonaGóra: University of
ZielonaGóra. pp. 153. ISBN 978-83-7481-293-1.
2. FPGA Architecture for the Challenge
Clarke, EE Times, "Xilinx, ASIC Vendors Talk Licensing
3. (http://www.eetimes.com/story/OEG20010622S0091)." June 22, 2001.
Retrieved February 10, 2009.
4. Funding Universe. ―Xilinx, Inc.
Company-History.html) ‖ Retrieved January 15, 2009.
5. Press Release, "Xilinx Co-Founder Ross Freeman Honored as 2009 National
Inventors Hall of Fame Inductefor Invention of FPGA
6. Cheung, Ken, FPGA Blog. "Xilinx Extensible Processing Platform for
7. Leibson, Steve, Design-Reuse. "Xilinx redefines the high-end
microcontroller with its ARM-based Extensibl
8. Processing Platform - Part 1
basedextensible-processing-platform.html) ."May. 03, 2010.