physical aware timing eco

1. ECOs
Rajesh Mekala

2. Agenda
● Motivation
● Flow
● Specific types of ECOs and examples
● Timing ECO tools
● Conclusions
* Various hyperlinks provided for an in-depth study

3. Definition
● ECO - Engineering Change Order
● Types
○ Timing ECO
■ setup, hold, max_trans, max_cap, max_fanout, min_pulse_width, min_period
■ Metal only timing ECOs
○ Functional ECO
■ Verification bugs
■ Last minute RTL changes
○ Power ECO
■ Leakage recovery
■ Area recovery
■ Dynamic power optimization
■ Metal only leakage recovery
○ Clock ECO
■ Setup, hold

4. Why?
● Implementation tool doesn’t fix all the violations
● Mis-correlation between implementation and sign-off
○ GBA/PBA
○ Sign-off margins are different from PD margins
○ PnR spef (less accurate) v.s. STARRC spef (sign-off)
○ Delay calculation
○ Modeling differences (NDM, .lib, CCS)
○ OCV modeling differences
● More sign-off corners than what is enabled in PnR
● Verification catches bugs
○ Do not want to restart PD, but directly change netlist
● Recover power based on sign-off views
● DFT mode hold violations
● Incremental changes to the design towards closure
○ Revert back the changes if progressing in a wrong direction

5. Why?
● Improve timing for any post-PD changes to design
○ DRC cleanup
○ Metal fill
○ IR drop fixes
● Functional RTL changes
● SI calculation, timing window changes
○ Accurate noise CCS models available in sign-off views
● Flatten all hierarchies in sign-off STA
○ Multibit, soft_macros etc.
● Integration of IPs at chip_top and fixing remaining violations
● Fine-tuned limited SDC constraints not supported by implementation tool
● Cross corner clock skew and jitter variations
● Incremental analysis/flow
● Clock frequency and cell specific (VT/type) margins

6. Need for physical aware ECOs
● Lot of iterations for design closure
○ Back and forth between PD and sign-off
○ Less correlation leads to more iterations
● Lower technology nodes have restrictive rules
○ min_vt_spacing
○ min_vt_area
○ cell specific derates
○ Need for R,C estimation during ECO generation
○ Double patterning DRC violations
● Miscorrelation between estimated and actual routes
● Lower technology nodes demand physical awareness
● Shorter Turnaround time
● Complex IPs and integration needs more automation

7. Timing ECO flow
● 20-30 loops in 4-5 weeks of time
is pretty common in industry
● Physical aware ECOs shorten the
timing closure time
● Multi-voltage, Multi corner and
Multi-mode scenarios need more
time for closure
● Conflicting setup and hold
violation fixes
● Increasing prudence in margining
for more yield and mass
production

8. Timing ECO fixes
setup hold max_trans
● Driver Upsizing
● Vt-swap
● Swap to lower channel length devices
● on-route buffer-insertion
● Re-placement (cluster)
● Net layer promotion (using route guides)
● Nets re-routing (shorter routes)
● Redundant inverter pair/buffer removal
● Flop vt-swap (lower setup requirement)
● Useful skew (clock ECO)
● Minimize clock crosstalk
● Remove data crosstalk
● NDR (remove SI)
● Shield critical nets
● load splitting
● downsize cells in non-critical fanout
● Route straightening (avoid jogs)
● Minimize number of vias
● Reduce clock jitter (better PLL, power grid)
● Register retiming
● 2-sigma timing corners
● Minimize clock tree divergence
● Downsizing
● Vt-swap
● On-route delay cell insertion
● Net layer demotion (route guides)
● Flop vt-swap (lower hold requirement)
● Clock adjustment
● Lockup latch
● Minimize clock crosstalk
● Dummy load insertion
● Net detours
● Upsizing
● Vt-swap
● On-route buffer-insertion
● Load splitting
● Buffer insertion
● SI prevention on high fanout
nets

9. Power ECO
● vt-swap
● downsizing
● Remove redundant inverter pairs/buffers
○ Preserve timing across scenarios
● fix_eco_leakage from synopsys (PTSI)
● Example leakage recovery algorithm

10. Improved Leakage Recovery flow

11. Metal only ECO
● Base layers frozen (dont_touch)
● Only changes in the metal connections
○ Use programmable filler cells
○ Use spare cells
● Use existing filler cells and refill the design in empty spaces
● Parallelize base tapeout and metal tapeouts efforts on hard macros

12. Metal only ECO

13. Timing ECO tools
● In-house MCMM based TCL scripts
● Tweaker (Dorado Automation)
● fix_eco_timing/fix_eco_leakage (Synopsys)
● TimingExplorer (ICScape)
● Tempus (Cadence)

14. Functional ECO
● Implement the incremental RTL change onto the final netlist instead of re-
doing the PD work
● LEC to make sure new netlist and new RTL and equivalent
● Functional metal ECOs after TO
● Conformal is the industry standard

15. Upcoming Technologies
● Clock ECO
○ setup/hold fixes
● Dynamic power optimization
○ SAIF/VCD/Toggle rate
● Route control in timing ECOs
● Automatic mapping and legalization for functional ECO gates
● Robust Minimal Physical Impact flows
● Local placement re-clustering algorithms

16. Appendix

17. Reading Material
● Thesis on spare cells methodology
● Smart timing closure
● MCMM timing closure system
● Dorado website
● Physical aware timing ECOs
● Practical ECOs using conformal