The document summarizes a seminar presentation on fault simulation techniques. It discusses (1) different fault simulation methods like serial, parallel, and concurrent fault simulation, (2) how concurrent fault simulation works using an example circuit, and (3) applications of fault simulation like measuring fault coverage, generating test vectors, and creating fault dictionaries. The presentation concludes with references for further reading on fault simulation and testing techniques.

1. Seminar
Fault Simulation – Application and Methods
Subash John
CGB0911005
VSD 530
M.Sc. [Engg.] in VLSI System Design
Module Title: Reliable Power Aware ASICs
Module Leader: Mr. Padmanaban K.
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2. Contents
• Introduction
• Fault simulation environment
• Fault simulation methods
• Concurrent fault simulation illustration
• Fault simulation applications
• Conclusion
• References
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3. Introduction
• Fault simulation consists of simulating a circuit in the presence of faults
• To test an ASIC, a series of inputs patterns are required that will detect any
faults
• There are several algorithms for fault simulation: serial fault
simulation, parallel fault simulation, concurrent fault simulation and deductive
fault simulation
• Any algorithm consists of 5 specific tasks:
• Fault free circuit simulation
• Fault specification
• Fault insertion (fault list generation and collapsing)
• Fault-effect generation and propagation
• Fault detection and discarding
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4. Fault simulation environment
Test Data
Test Application
Golden Model
Data Response Comparison
Report generation Reports
Fault Test data Validation
Fault able Model
List Fault
Injection
Figure 1. Fault Simulation process [1]
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5. Fault Simulation Methods (1/2)
Serial fault simulation
• Fault free circuit is simulated first and the results are stored in a file
• Next, faulty circuits are simulated one by one
• The output values of the faulty circuit are dynamically compared with the saved fault-
free responses
• For n faults, the CPU time of a serial simulator can be almost n times that of a fault-free
simulator
Parallel fault simulation
• Performed using bitwise logic operations
• Takes advantage of parallelism inherent in host computer to reduce fault simulation time
• A fault is detected if its bit value differs from that of the fault-free circuit at any of the
outputs
• Parallel fault simulation technique is applicable to the unit or zero delay models only
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6. Fault Simulation Methods (2/2)
Concurrent fault simulation
• Parallel fault simulation requires multiple parallel circuits resulting in large
memories and long simulation times
• In concurrent simulation only gates which propagate the faults are duplicated
and simulated, thus saving processing time
Algorithm for concurrent fault simulation
Given test T, n test vectors, t1:n;
Given fault list F, m faults, f1:m; f0 no fault;
Consider all faults for concurrent injection
For i in 1 to n Loop – every t in T
Propagate t1;
If due to fault fj a gate output is faulty
Duplicate gate with faulty output
End if;
End for;
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7. Concurrent fault simulation illustration (1/3)
• Assume that A: ST - 1, C: ST – 0, J: ST – 0.
Table 1. Test for stuck at one fault at node A
Step A B C E=F=L J H K
Initial 0 1 0 1 0 0 1
Faulty 1 1 0 1 0 1 0
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8. Concurrent fault simulation illustration (2/3)
Table 2. Test for stuck at zero fault at node C
Step A B C E=F=L J H K
Initial 0 0 1 1 0 0 1
Faulty 0 0 0 0 1 0 0
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9. Concurrent fault simulation illustration (3/3)
Table 3. Test for stuck at zero fault at node J
Step A B C E=F=L J H K
Initial 1 0 0 0 1 0 0
Faulty 1 0 0 0 1 0 0 1
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10. Fault simulation applications (1/3)
1. Fault coverage (test coverage)
• Ratio of detected faults over total faults in a circuit
Algorithm for concurrent fault coverage Table 4. Fault Coverage [2]
Given Test Set T, n test vectors, t1:n;
Fault Average Repair
Given Fault List F, m faults, f1:m;f0 no fault;
Coverage Defect Cost
For j in 1 to m loop -- every f in F
Level
Inject fj;
For i in 1 to n loop -- every t in T 50% 7% $2Million
While fj is not detected begin 90% 3% $200,000
Simulate faulty circuit;
95% 1% $20,000
Increment DF if fj is detected;
End while; 99% 0.1% $2,000
End for; 99.9% 0.01% $200
Remove fj;
End for;
Record DF, detected fault in F;
Calculate %FC based on m and DF;
Fault coverage = m/DF
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11. Fault simulation applications (2/3)
2. Test generation
• Process of obtaining test vectors for detecting circuit faults
(1) Test refinement
• Test efficiency is the number of faults covered by a test vector
• Test vectors that are low in efficiency, or test vectors that detect faults
already covered by other test vectors can be removed from the test set
• As such, a test set can be refined for the fewest number of tests and the
highest coverage
(2) Random test generation
• Can be regarded as a replacement for costly ATPG algorithms
• By fault simulation, a randomly generated input vector is examined for
detection of faults, and based on this, it is decided whether to keep the
vector as a test vector or to drop it
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12. Fault simulation applications (3/3)
3. Fault Dictionary
• Consists of simulated responses for all faults in fault list, stored in database
• Used by some diagnosis algorithms for convenience:
– Fast: No simulation at time of diagnosis
– Self-contained: net list, simulator, and test set not needed after dictionary
creation
Table 5. Multiplexer fault dictionary [1]
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13. Summary
• Major concerns of fault simulation techniques are the simulation speed and the
required memory
• It is apparent that serial fault simulation is the slowest among all the
techniques
• From the aspect of delay and functional modeling capability, serial fault
simulation does not encounter any difficulty.
• Parallel fault simulation cannot take delay or functional models into account as
they pack the information of multiple faults or test patterns into the same word
and rely on bitwise logic operations
• Being event driven, concurrent fault simulation techniques are capable of
handling functional models
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14. References
[1] Bushnell and Agrawal (2002) Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits. New York: Kluwer Academic
Publishers
[2] Wang, Wu and Wen (2006) VLSI Test Principles and Architectures: Design
for Testability. San Francisco: Morgan Kaufmann Publishers
[3] Zainalabedin Navabi (2011) Digital System Test and Testable Design. New
York: Springer
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15. Thank You
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16. Remarks
Sl. No. Topic Max. marks Marks
obtained
1 Quality of slides 5
2 Clarity of subject 5
3 Presentation 5
4 Effort and question handling 5
Total 20
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