This document proposes a new method called SfW (skewed-load for wrapper) for generating delay fault tests that can be applied through a simple boundary scan chain. The SfW method generates test vectors for transition faults in a way that consecutive vector pairs are generated by one or more bit shifts, reducing the test application time compared to random vectors. Experimental results on combinational and sequential circuits showed the SfW method provides a significant reduction in test vector application time compared to previous methods.
SOC TAM Design to Minimize Test Application TimeHuiting Zhang
This document proposes a new test access mechanism (TAM) design and test scheduling approach to minimize system-on-chip (SoC) test application time under hardware and power constraints. The key aspects of the approach are: 1) Integrating the TAM design with scan chain redesign and core layout arrangement to reduce wiring complexity and make effective use of TAM resources. 2) Considering hardware constraints like predefined shared resources and voltage islands, as well as power constraints, in the test scheduling formulation. 3) Adopting dynamic voltage and frequency scaling in test scheduling to further reduce testing time. Experimental results on ITC'02 benchmark chips show up to 69% reduction in test application time using the proposed TAM design and scheduling
This document summarizes a project that aims to classify heartbeats (ECG signals) into four classes (normal, congestive heart failure, ventricular tachyarrhythmia, atrial fibrillation) using support vector machines with error correcting output codes. The project implements feature extraction via discrete wavelet transform on ECG signals, then uses SVMs with an error correcting code for classification, achieving an average accuracy of classifying 2-3 out of 4 classes correctly. The document outlines the methodology, implementations, experiments and results of the project.
Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping ...IOSR Journals
This document proposes a technique called a bit-swapping linear feedback shift register (BS-LFSR) to reduce average and peak power in built-in self-tests (BISTs). The BS-LFSR swaps the values of two cells in an LFSR based on the value of a third cell, reducing transitions by 50% compared to a standard LFSR. It is combined with an algorithm that orders check cells to further reduce average and peak power during testing. Experimental results on benchmark circuits show up to 65% reduction in average power and 55% reduction in peak power with little impact on fault coverage or test time.
This document discusses a technique called Linear Feedback Shift Register - Bit Complement Test Pattern Generation (LFSR-BCTPG) to minimize test power in VLSI circuits. The LFSR-BCTPG generates test patterns with the LFSR but complements output bits to reduce repeated patterns. This increases unique test vectors and improves fault coverage while reducing circuit size and dynamic power compared to a conventional LFSR. The technique generates test patterns by alternating the enable signals to the two halves of the LFSR flip-flops. Evaluation on ISCAS benchmark circuits showed this method reduces dynamic power consumption during testing.
This document presents a quantum computer architecture tailored for an electron-spin qubit implementation on liquid helium (eSHe) that has highly mobile qubits. The architecture takes advantage of the fast qubit transportation speeds relative to operation times in eSHe. It uses shift registers and buses to transport many qubits in parallel to execution units to enable high parallelism. Error correction procedures are also analyzed and show idle qubits only need refreshing about once every 100 operation cycles. Compiler optimizations can reduce hardware requirements by 25% with no performance loss.
Techniques for Minimizing Power Consumption in DFT during Scan Test ActivityIJTET Journal
1. The document discusses techniques for minimizing power consumption during scan test activity. It proposes a novel circuit technique to eliminate switching in combinational logic during scan shifting by masking logic inputs. Blocking transistors are added to gate the power supply to first-level gates at flip-flop outputs during scan shifting.
2. A selective trigger scan architecture is proposed that reduces switching between scan cells and test vectors by using NOR gates to compare previous and next test vector values and only applying differences. Scan chain reordering is also used to minimize transitions between flip-flops.
3. Experimental results on ISCAS89 benchmarks show the proposed techniques reduce static power by 6.1-11% and area overhead by 47% compared to
SOC TAM Design to Minimize Test Application TimeHuiting Zhang
This document proposes a new test access mechanism (TAM) design and test scheduling approach to minimize system-on-chip (SoC) test application time under hardware and power constraints. The key aspects of the approach are: 1) Integrating the TAM design with scan chain redesign and core layout arrangement to reduce wiring complexity and make effective use of TAM resources. 2) Considering hardware constraints like predefined shared resources and voltage islands, as well as power constraints, in the test scheduling formulation. 3) Adopting dynamic voltage and frequency scaling in test scheduling to further reduce testing time. Experimental results on ITC'02 benchmark chips show up to 69% reduction in test application time using the proposed TAM design and scheduling
This document summarizes a project that aims to classify heartbeats (ECG signals) into four classes (normal, congestive heart failure, ventricular tachyarrhythmia, atrial fibrillation) using support vector machines with error correcting output codes. The project implements feature extraction via discrete wavelet transform on ECG signals, then uses SVMs with an error correcting code for classification, achieving an average accuracy of classifying 2-3 out of 4 classes correctly. The document outlines the methodology, implementations, experiments and results of the project.
Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping ...IOSR Journals
This document proposes a technique called a bit-swapping linear feedback shift register (BS-LFSR) to reduce average and peak power in built-in self-tests (BISTs). The BS-LFSR swaps the values of two cells in an LFSR based on the value of a third cell, reducing transitions by 50% compared to a standard LFSR. It is combined with an algorithm that orders check cells to further reduce average and peak power during testing. Experimental results on benchmark circuits show up to 65% reduction in average power and 55% reduction in peak power with little impact on fault coverage or test time.
This document discusses a technique called Linear Feedback Shift Register - Bit Complement Test Pattern Generation (LFSR-BCTPG) to minimize test power in VLSI circuits. The LFSR-BCTPG generates test patterns with the LFSR but complements output bits to reduce repeated patterns. This increases unique test vectors and improves fault coverage while reducing circuit size and dynamic power compared to a conventional LFSR. The technique generates test patterns by alternating the enable signals to the two halves of the LFSR flip-flops. Evaluation on ISCAS benchmark circuits showed this method reduces dynamic power consumption during testing.
This document presents a quantum computer architecture tailored for an electron-spin qubit implementation on liquid helium (eSHe) that has highly mobile qubits. The architecture takes advantage of the fast qubit transportation speeds relative to operation times in eSHe. It uses shift registers and buses to transport many qubits in parallel to execution units to enable high parallelism. Error correction procedures are also analyzed and show idle qubits only need refreshing about once every 100 operation cycles. Compiler optimizations can reduce hardware requirements by 25% with no performance loss.
Techniques for Minimizing Power Consumption in DFT during Scan Test ActivityIJTET Journal
1. The document discusses techniques for minimizing power consumption during scan test activity. It proposes a novel circuit technique to eliminate switching in combinational logic during scan shifting by masking logic inputs. Blocking transistors are added to gate the power supply to first-level gates at flip-flop outputs during scan shifting.
2. A selective trigger scan architecture is proposed that reduces switching between scan cells and test vectors by using NOR gates to compare previous and next test vector values and only applying differences. Scan chain reordering is also used to minimize transitions between flip-flops.
3. Experimental results on ISCAS89 benchmarks show the proposed techniques reduce static power by 6.1-11% and area overhead by 47% compared to
The document presents a new NoC Interface (MSIQ) that improves performance over the previous MSI by reducing software overhead from interrupt processing. The MSIQ uses queue mechanisms to batch multiple interrupt requests and allow the interrupt service routine to process requests concurrently with hardware message sending and receiving. Performance analysis shows the MSIQ achieves better performance than the MSI with only small additional hardware costs.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document proposes a multi-application multi-step mapping method for mapping multiple applications simultaneously onto a many-core Network-on-Chip (NoC). The method consists of two steps: 1) an application mapping step that finds a region on the NoC for each application using maximal empty rectangle techniques, and 2) a task mapping step that maps the tasks of each application within its region to minimize communication latency and energy consumption. The method aims to optimize the layout of applications and tasks to reduce network latency and energy usage for multi-application mapping on many-core NoCs.
1) Current-steering DACs often have non-linearity due to signal-dependent output impedance, which causes 2nd-order distortion.
2) When used for digital IF generation rather than direct up-conversion, the DAC output contains tones at the desired IF frequency and its harmonics/images.
3) The dominant source of distortion is mixing between the output voltage and digital input signal, generating intermodulation products. Shorting unwanted tones at the DAC output could improve linearity.
The document describes an analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology. The baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF), and an Output Buffer (OBUF). The VGA provides a tunable gain range of 25-34dB. The LPF has a programmable bandwidth of 120-190MHz and provides an additional 8dB of gain. Together, the baseband chain achieves 4nV/√Hz of input-referred noise density and -42dBV of in-band IIP3. The chain occupies
This document proposes a framework for modeling source traffic in a Network on Chip (NoC) that originates from a single source but is destined for multiple destinations, known as multicasting. It presents a model to characterize such traffic as a single stream at the source based on the probabilistic demultiplexing of that stream into multiple streams. The model shows that the burst parameters of the demultiplexed streams are related to those of the original stream. The model is implemented in an NoC simulator and experimental results validate that the demultiplexed streams remain bursty even as their burst parameters change according to the model.
This document reviews Network-on-Chip (NoC) architectures that prioritize selected data streams to reduce communication latency. It categorizes the architectures based on the effect of prioritization (per end-to-end connection, per router, or per path segment) and discusses their pros and cons. Architectures that prioritize at the core-to-core level provide the highest latency reduction by bypassing the NoC, while those prioritizing per router or path segment require redetermining priority at each hop.
Ratan Devpura is passionate about analog and mixed-signal circuit design. He has worked on amplifier, ADC, and DAC designs for mixed-signal systems. As an intern, he worked on migrating analog circuits to newer process technologies and verifying circuit simulation tools. He holds an M.S. in electrical engineering and aims to become an outstanding circuit design engineer through continued learning and innovative analog circuit designs.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
A survey of scan-capture power reduction techniquesIJECEIAES
With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing
IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED...VLSICS Design
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results.
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...ijcisjournal
In this paper methods for testing both software and hardware faults are implemented in analog and digital
signal circuits are presented. They are based on the wavelet transform (WT). The limit which affected by
faults detect ability, for the reference circuits is set by statistical processing data obtained from a set of
faults free circuits .In wavelet analysis it has two algorithm one is based on a discrimination factor using
Euclidean distances and the other mahalanobis distances, are introduced both methods on wavelet energy
calculation. Simulation result from proposed test methods in the testing known analog and digital signal
circuit benchmark are given. The results shows that effectiveness of existing methods two test metrics
against three other test methods, namely a test method based on rms value of the measured signal, a test
method utilizing the harmonic magnitude component of the measured signal waveform
Online and Offline Testing Of C-Bist Using Sramiosrjce
This document summarizes a research paper on online and offline testing of a C-BIST (concurrent built-in self-test) architecture using SRAM (static random-access memory). The proposed C-BIST scheme monitors input vectors during normal circuit operation and uses an SRAM-like structure to store information on detected vectors. It is shown to have lower hardware overhead and faster concurrent test latency compared to previous C-BIST techniques. The document outlines the existing C-BIST system, proposed simultaneous testing and online operation methodology, simulation results demonstrating error detection and output correction, and conclusion that the SRAM-based approach provides an efficient solution for testing VLSI circuits during normal operation.
Heuristic approach to optimize the number of test cases for simple circuitsVLSICS Design
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.
Heuristic approach to optimize the number of test cases for simple circuitsVLSICS Design
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.
Design of accumulator Based 3-Weight Pattern Generation using LP-LSFRIOSR Journals
Abstract: The objective of the BIST is to reduce power dissipation without affecting the fault coverage. Weighted pseudorandom built-in self - test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage. Keywords: Built-in self- test (BIST), test per clock, VLSI testing, weighted test pattern generation, low power linear feedback shift register [LP-LFSR].
Iaetsd power capture safe test pattern determinationIaetsd Iaetsd
The document proposes a method to determine power-safe test patterns for at-speed scan-based testing to address excessive capture power issues. It involves two main processes: 1) test pattern refinement process which refines existing power-safe patterns to detect faults detected by power-risky patterns while satisfying power constraints, and 2) low-power test pattern regeneration process which generates new power-safe patterns if faults remain undetected after refinement. Experimental results show the method can detect over 75% of power-risky faults through refinement with up to 12.76% reduction in test data volume without loss of fault coverage.
This document summarizes a study of built-in self-test (BIST) approaches for detecting single stuck-at faults in combinational logic circuits. Pseudorandom test patterns generated by a linear feedback shift register (LFSR) were applied in parallel and serially to benchmark circuits. Applying patterns in parallel via test-per-clock achieved high fault coverage but required a large LFSR for circuits with many inputs. Reseeding the LFSR improved coverage when an initial seed was ineffective. Seed selection and minimum LFSR size for different application methods were evaluated to optimize BIST fault detection.
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Journals
Abstract Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by using simulator and correctness of these methods are verified. Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.
Development of Seakeeping Test and Data Processing Systemijceronline
This document describes the development of a seakeeping test and data processing system. The system includes two main procedures: wave generation and data processing. In wave generation, a linear filtering method is used to generate irregular waves that meet a target spectrum. In data processing, time domain and frequency domain methods are used to analyze experimental data on irregular waves, ship motions, and hull stresses. The system was tested using experiments on a ship model in irregular waves and showed accurate simulation and reliable data processing.
Performance Analysis in Cellular Networks Considering the QoS by Retrial Queu...IJCNCJournal
In this article, a retrial queueing model will be considered with persevering customers for wireless cellular networks which can be frequently applied in the Fractional Guard Channel (FGC) policies, including Limited FGC (LFGC), Uniform FGC (UFGC), Limited Average FGC (LAFGC) and Quasi Uniform FGC (QUFGC). In this model, the examination on the retrial phenomena permits the analyses of important effectiveness measures pertained to the standard of services undergone by users with the probability that a fresh call first arrives the system and find all busy channels at the time, the probability that a fresh call arrives the system from the orbit and find all busy channels at the time and the probability that a handover call arrives the system and find all busy channels at the time. Comparison between four types of the FGC policy can befound to evaluate the performance of the system.
The document presents a new NoC Interface (MSIQ) that improves performance over the previous MSI by reducing software overhead from interrupt processing. The MSIQ uses queue mechanisms to batch multiple interrupt requests and allow the interrupt service routine to process requests concurrently with hardware message sending and receiving. Performance analysis shows the MSIQ achieves better performance than the MSI with only small additional hardware costs.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document proposes a multi-application multi-step mapping method for mapping multiple applications simultaneously onto a many-core Network-on-Chip (NoC). The method consists of two steps: 1) an application mapping step that finds a region on the NoC for each application using maximal empty rectangle techniques, and 2) a task mapping step that maps the tasks of each application within its region to minimize communication latency and energy consumption. The method aims to optimize the layout of applications and tasks to reduce network latency and energy usage for multi-application mapping on many-core NoCs.
1) Current-steering DACs often have non-linearity due to signal-dependent output impedance, which causes 2nd-order distortion.
2) When used for digital IF generation rather than direct up-conversion, the DAC output contains tones at the desired IF frequency and its harmonics/images.
3) The dominant source of distortion is mixing between the output voltage and digital input signal, generating intermodulation products. Shorting unwanted tones at the DAC output could improve linearity.
The document describes an analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology. The baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF), and an Output Buffer (OBUF). The VGA provides a tunable gain range of 25-34dB. The LPF has a programmable bandwidth of 120-190MHz and provides an additional 8dB of gain. Together, the baseband chain achieves 4nV/√Hz of input-referred noise density and -42dBV of in-band IIP3. The chain occupies
This document proposes a framework for modeling source traffic in a Network on Chip (NoC) that originates from a single source but is destined for multiple destinations, known as multicasting. It presents a model to characterize such traffic as a single stream at the source based on the probabilistic demultiplexing of that stream into multiple streams. The model shows that the burst parameters of the demultiplexed streams are related to those of the original stream. The model is implemented in an NoC simulator and experimental results validate that the demultiplexed streams remain bursty even as their burst parameters change according to the model.
This document reviews Network-on-Chip (NoC) architectures that prioritize selected data streams to reduce communication latency. It categorizes the architectures based on the effect of prioritization (per end-to-end connection, per router, or per path segment) and discusses their pros and cons. Architectures that prioritize at the core-to-core level provide the highest latency reduction by bypassing the NoC, while those prioritizing per router or path segment require redetermining priority at each hop.
Ratan Devpura is passionate about analog and mixed-signal circuit design. He has worked on amplifier, ADC, and DAC designs for mixed-signal systems. As an intern, he worked on migrating analog circuits to newer process technologies and verifying circuit simulation tools. He holds an M.S. in electrical engineering and aims to become an outstanding circuit design engineer through continued learning and innovative analog circuit designs.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
A survey of scan-capture power reduction techniquesIJECEIAES
With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing
IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED...VLSICS Design
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results.
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...ijcisjournal
In this paper methods for testing both software and hardware faults are implemented in analog and digital
signal circuits are presented. They are based on the wavelet transform (WT). The limit which affected by
faults detect ability, for the reference circuits is set by statistical processing data obtained from a set of
faults free circuits .In wavelet analysis it has two algorithm one is based on a discrimination factor using
Euclidean distances and the other mahalanobis distances, are introduced both methods on wavelet energy
calculation. Simulation result from proposed test methods in the testing known analog and digital signal
circuit benchmark are given. The results shows that effectiveness of existing methods two test metrics
against three other test methods, namely a test method based on rms value of the measured signal, a test
method utilizing the harmonic magnitude component of the measured signal waveform
Online and Offline Testing Of C-Bist Using Sramiosrjce
This document summarizes a research paper on online and offline testing of a C-BIST (concurrent built-in self-test) architecture using SRAM (static random-access memory). The proposed C-BIST scheme monitors input vectors during normal circuit operation and uses an SRAM-like structure to store information on detected vectors. It is shown to have lower hardware overhead and faster concurrent test latency compared to previous C-BIST techniques. The document outlines the existing C-BIST system, proposed simultaneous testing and online operation methodology, simulation results demonstrating error detection and output correction, and conclusion that the SRAM-based approach provides an efficient solution for testing VLSI circuits during normal operation.
Heuristic approach to optimize the number of test cases for simple circuitsVLSICS Design
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.
Heuristic approach to optimize the number of test cases for simple circuitsVLSICS Design
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.
Design of accumulator Based 3-Weight Pattern Generation using LP-LSFRIOSR Journals
Abstract: The objective of the BIST is to reduce power dissipation without affecting the fault coverage. Weighted pseudorandom built-in self - test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage. Keywords: Built-in self- test (BIST), test per clock, VLSI testing, weighted test pattern generation, low power linear feedback shift register [LP-LFSR].
Iaetsd power capture safe test pattern determinationIaetsd Iaetsd
The document proposes a method to determine power-safe test patterns for at-speed scan-based testing to address excessive capture power issues. It involves two main processes: 1) test pattern refinement process which refines existing power-safe patterns to detect faults detected by power-risky patterns while satisfying power constraints, and 2) low-power test pattern regeneration process which generates new power-safe patterns if faults remain undetected after refinement. Experimental results show the method can detect over 75% of power-risky faults through refinement with up to 12.76% reduction in test data volume without loss of fault coverage.
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IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
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In this article, a retrial queueing model will be considered with persevering customers for wireless cellular
networks which can be frequently applied in the Fractional Guard Channel (FGC) policies, including
Limited FGC (LFGC), Uniform FGC (UFGC), Limited Average FGC (LAFGC) and Quasi Uniform FGC
(QUFGC). In this model, the examination on the retrial phenomena permits the analyses of important
effectiveness measures pertained to the standard of services undergone by users with the probability that a
fresh call first arrives the system and find all busy channels at the time, the probability that a fresh call
arrives the system from the orbit and find all busy channels at the time and the probability that a handover
call arrives the system and find all busy channels at the time. Comparison between four types of the FGC
policy can befound to evaluate the performance of the system.
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2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
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This summary provides the key details about the document in 3 sentences:
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This paper presents a second-order delta-sigma modulator designed for pressure sensor applications. The modulator utilizes correlated double sampling in the first integrator to reduce flicker noise. It was implemented in a 0.35-μm CMOS process and consumes 14μA of current. Measurements showed a signal-to-noise ratio of 86dB at a 14-bit resolution level when using an input sampling rate of 1/4 and sampling capacitors of 50pF. The modulator provides a flexible design that allows tuning the sampling frequency and capacitor size to tradeoff between power consumption and performance.
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[3] Simulation results and theoretical analysis are presented to support that the proposed architecture can provide similar performance
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This paper presents an improved hardware acceleration scheme for Java method calls in the REALJava coprocessor. The strategy is implemented in an FPGA prototype and allows for measuring real performance increases. It validates the coprocessor concept for accelerating Java bytecode execution in embedded systems with limited CPU performance and memory availability. The coprocessor architecture is highly modular, separating communication from the execution core to improve reusability and allow for system scalability.
1. SfW Method: Delay Test Generation for Simple
Chain Wrapper Architecture
Marcel Baláž
Institute of Informatics
Slovak Academy of Sciences
845 07 Bratislava, Slovakia
E-mail: marcel.balaz@savba.sk
Abstract—The aim of the presented work is to improve the II. S CAN - BASED D ELAY T EST
quality of testing of SoC digital cores surrounded with test
wrappers. The paper presents a new effective delay fault test A test for delay faults, unlike tests for most of other
generation method for the transition faults based on the skewed- faults, consists of vector-pairs. The first vector of a vector-
load test. The generated delay fault test can be applied to
a SoC core through a test wrapper architecture with only a pair ensures the initial state of a core and the second one sets
simple boundary scan chain. This eliminates the necessity to the propagation state of the core. The transition between the
use an enhanced boundary scan chain for the application of two states can result in a delay fault in the functional operation
the delay fault test. The effectiveness of the developed method mode. Therefore, the transition has to be excited at the rated-
for a transition delay test generation was verified on the set of speed clock in the test mode as well. The main challenges
combinational and sequential circuits. The experiments show a
significant reduction of test vector application time. in the scan-based delay fault testing constitute transportation
or generation of an exciting vector and its application at full
I. I NTRODUCTION circuit speed.
Embedded digital blocks and their interconnections have to Three basic approaches should be considered for a vector-
be verified by an at-speed testing to satisfy the quality and the pair test application through core’s internal scan chains: a
reliability of nowadays SoCs. Once a chip is fabricated, it must skewed-load test [4], a broadside test [5] and an enhanced
be tested for a pre-specified clock frequency and therefore, the scan test. The skewed-load and the broadside tests use scan
testing has to cover also speed related faults. chain composed of simple scan cells (one memory element
Many delay fault models and related test generation tech- per one cell — Figure 1a). The first vector of a vector-pair
niques have been defined and used in digital circuits [1]. The is shifted in as a standard test vector. The difference between
common feature of most of the delay fault models is that these two test approaches lies in the way how to produce the
the test is composed of vector-pairs v1, v2 , where v1 is second vector. The broadside test uses circuit’s response and
the initialization vector and v2 is the excitation vector for the skewed-load test uses one additional shift to produce the
delay fault detection. The basic delay fault models are: the desired excitation vector. On the other hand, the enhanced scan
transition fault-, the gate delay fault-, and the path delay fault test uses enhanced scan cells (two memory elements per one
model. The transition and the path delay fault models are the cell — Figure 1b). The test architecture is much larger in
most frequently applied ones to combinational and scan-based comparison with simple scan chains but its advantage is in
sequential circuits. Several new models [2], [3] have been the capability of arbitrary vector-pairs application.
developed to use or combine some of the positive features The adaptation of existing scan methods to core-based SoCs
of the basic models. is an open issue, in particular in terms of test development for
The scan chain design is the most frequently used method core providers and test access mechanism (TAM) development
to increase testability of deeply embedded cores in SoC. for system integration. Although IEEE Std. 1500-2005 [6]
However, using the scan-based test architectures in vector-pair and recent research advances support structural scan tests,
testing is not a trivial problem. Test generation algorithms the most achievements are based on one-vector tests. Several
for combinational and scan-based synchronous circuits are approaches deal with vector-pair application for test wrapper
well known while test application techniques through test structures differently. The oscillation test method [7] requires
wrappers are still under development. This paper presents special address registers in each scan cell. Other test methods
a new developed method — called SfW (skewed-load for use principles of one of the three basic test approaches for
wrapper). The SfW method generates a test for the transition internal scan chains. The approach in [8] is based on the broad-
fault model applicable through a simple boundary scan chain. side test and requires only simple scan cells (with one memory
The paper is organized as follows. Delay test issues for scan- cell). The broadside effect is not achieved inside one core
based architectures are described in Section II. The proposed separately but it is obtained among several cores. The necessity
SfW method is described in Section III, and experimental of other cores assistance during a test restricts widespread
results are presented in Section IV. usage of this approach. The most common approach for
978-1-4244-8971-8/10$26.00 c 2010 IEEE
2. Strategy 2. The vector-pairs covering the transition faults
create one sequence of binary values in which each vector-pair
corresponds to Strategy 1 and also two consecutive vector-
pairs are generated by one or more bit shifts.
Example 1. Let delay fault test for a core with three in-
puts consist of following vector-pairs: 110, 100 , 001, 010 ,
101, 011 . Then the test sequence according to Strategy 1
and 2 is 11001011. The application of the test sequence is
illustrated in Figure 2. The simple boundary scan chain is
created with WC_SD1_CII scan cells (Figure 1a) which are
compliant with IEEE Std. 1500-2005 [6]. Every step of the test
application corresponds to one shift in scan chain. In the third
step the first initializing vector 110 is applied to the core.
In the fourth step the first excitation vector 100 is applied
Figure 1. a) An example of simple scan cell, and b) enhanced scan cell
and thus the first vector-pair as well. The eighth step is the
last step when the last excitation vector 011 is applied.
providing a delay test on embedded cores is the enhanced scan The transition fault test consists of vector-pairs where one
test (enhanced scan cells with two memory elements in each vector-pair covers one or more transition faults. The excitation
are used, e. g. [9]). No approach uses simple boundary scan vector of a vector-pair is actually a stuck-at test vector
chain without assistance of surrounding cores. The vector-pair according to basic principle of the delay fault test. For this
test approaches, which use simple scan chain are mostly based reason, the majority of existing automatic test generator for
on (pseudo)random vectors (the first presented skewed-load transition faults is based on test vectors for stuck-at-0 and
test used 100,000 random vector-pairs [10]). In comparison stuck-at-1 faults.
with the deterministic stuck-at test the application time of this The bit sequence formed by random or pseudo-random
type of delay test is multiple times longer. vectors corresponds to Strategy 1 and 2. This type of bit
The main idea was to develop a method to generate a sequence is very long (more than thousands of vector-pairs),
delay test which would, together with its ability to use test which leads to intolerable increase of test application time
wrapper with a simple boundary scan chain, have comparable for larger circuits. This solution also needs the use of a fault
application time with a deterministic stuck-at test. simulator to determine the fault coverage.
The proposed SfW method for generating a bit sequence
III. S F W M ETHOD is based on deterministic tests and thus it generates a de-
The new method was developed for a delay fault test terministic test sequence for transition faults. However, it is
generation aimed at embedded cores. The proposed method is not possible to use standard tests for stuck-at faults like it
designated for a transition faults test generation with primary is used in other test generators for delay faults [11], [12].
application through the simple boundary scan chain (one Existing stuck-at tests are optimized mostly for a minimal
memory element per one scan cell). The simple boundary scan number of test vectors. For that reason selection of appropriate
chain occupies smaller area than the enhanced boundary scan vectors for the transition fault test in accordance to Strategy 1
chain but for its simpler construction it is not suitable for and 2 is very limited due to shift dependency. Therefore, the
an ordinary delay fault test. Therefore, it was necessary to SfW method uses modified stuck-at test, which consists of
propose a method to generate tests for delay faults applicable sets of test vectors for every detectable stuck-at fault in the
through the simple boundary scan chain. The method is core. This approach increased the probability of delay fault
based on the skewed-load test (launch-on-shift test) for the test generation for test Strategy 1 and 2, and also the overall
internal scan chains and the basic principle is characterized coverage of delay faults.
by Strategy 1. Initialization and excitation vectors can be merged into a
one bit sequence if the corresponding bits are identical, or
Strategy 1. A vector-pair to detect transition faults is applied
at least one of them is undefined. This condition is known
through a simple boundary scan chain as a one bit sequence,
as vector consistency and the bit sequence is referred to as
where an excitation vector is created by one bit shift of an
m-vector.
initialization vector.
Definition 1. Let v1 denote the initialization vector and v2
The basic requirements of the proposed method for a
the excitation vector in the circuit with N inputs then m =
optimal test length of a generated test for transition faults
(m1 , m2 , . . . mN +1 ) with m1 = v11 , mN +1 = v2N is m-
were (1) a test application via a simple boundary scan chain
vector only if mi for i = 2, 3, . . . N is determined by one of
without the use of neighboring test cores (Strategy 1), and
the possibilities in Table I.
(2) the minimal test application time. The second strategy was
formulated to minimize the test application time. M-vector is the bit sequence N + 1 bits long, where
3. Figure 2. An example of the test application to test wrapper with the simple boundary scan chain
Table I
A LLOWED BIT COMBINATION FOR DEFINING M - VECTOR Each singular m-vector covers a transition fault as the only
v1i v2i−1 mi one; therefore it must certainly be included in the generated
0 0 0 test sequence. The application of a initialization vector and a
0 X 0
X 0 0
excitation vector consequently creates a partial sensitive path
1 1 1 in the core. The sensitive path is created between the primary
1 X 1
X 1 1
inputs and a wire where the transition fault is tested. M-vector
X X X may also cover other transition faults which occur on the
sensitive path.
Definition 3. Let ms ∈ S be the singular m-vector and mf ∈
excitation vector (v2) is generated by one shift operation of Mf be the m-vector covering the transition fault f , then mf
the initialization vector (v1). overlaps ms if (msi = 0 ∧ mf i = 1) ∨ (msi = 1 ∧ mf i = 0)
for i = 1, 2, . . . N , where N is number of bits of mf (and ms).
To find an appropriate initialization vector, the SfW method
uses a set of excitation vectors for the second type of transition If the set Mf contains only one m-vector, which can overlap
fault on the same wire. The set of excitation vectors does not one singular m-vector, this overlap is performed. If the set Mf
cover the whole set of initialization vectors for the second contains more vectors, which can overlap the same singular
transition fault on the same wire. Therefore, the proposed m-vector the selection of the best one is performed in several
method includes a simulator of initialization values. It per- steps. The number of replaced undefined bits in the singular m-
forms two basic operations: (1) In case no vector from the set vector is considered and also overlapping m-vectors for fault
is suitable for m-vector creation the simulator is used to find f are compared with overlapping m-vectors for other faults.
a suitable initialization vector. (2) If there is a vector from If the set Mf contains no m-vector, which overlaps any
the set, which is also an initialization vector for a opposite singular m-vector, it is necessary to choose the representing
transition fault, the simulator finds its minimal form (vector m-vector of the set Mf . The selection of the best m-vectors
bits, which initially provide test value propagation to outputs for transition faults without any overlap on singular m-vectors
are replaced by undefined values) and thus also provides a is made with the constraint to find the minimal number of
minimal form of m-vector. m-vectors, which would cover all remaining faults.
One of the method requirements is the shortest test applica- The SfW method generates a minimized set of m-vectors,
tion of the generated test sequence which is achieved only by which covers all diagnosable transition faults in the core
a short generated test sequence. The length of the sequence under test. The set can be formed into one of three test
is determined by two factors: (1) the number of m-vectors in types. Each type is applicable to various types of test wrapper
the sequence, and (2) the capability to cover more transition architectures.
faults by one m-vector.
IV. E XPERIMENTAL R ESULTS
The SfW method generates more m-vectors for each transi-
tion fault. Set of m-vectors for each transition fault is searched The SfW method for delay test generation was validated
to find the minimal number of m-vectors, which would cover with numerous experiments. The test pattern generator Ata-
all faults in the core. Searching the set of m-vectors starts with lanta [13] was used to generate excitation vectors. This stuck-
singular m-vectors. at fault generator provides generation of multiple test vectors
for every fault. This feature was mandatory, since the proposed
Definition 2. M-vector is known as singular m-vector only if method is based on it. Experiments were performed using
none of other m-vectors can cover the transition fault. combinational benchmark circuits ISCAS’85 and sequential
4. Table II
E XPERIMENTAL RESULTS OF S F W METHOD AND P RIORITY- BASED E XTENSION METHOD [11]
circuit number of number of test sequence test sequence test coverage test coverage
m-vectors [SfW] vector-pairs [11] length (bit) [SfW] length (bit) [11] [SfW] [11]
c880 203 257 7 523 30 840 85,0% 100,0%
c1355 545 461 17 565 37 802 59,8% 99,8%
c1908 739 440 16 596 29 040 82,1% 99,7%
c3540 801 755 12 905 75 500 73,6% 96,3%
c5315 1 690 421 96 327 149 876 87,3% 99,5%
s344 51 96 614 4 608 92,2% 100,0%
s382 46 120 473 5 760 86,1% 100,0%
s526 85 209 914 10 032 85,6% 99,9%
s832 119 450 854 20 700 71,3% 99,2%
s1196 238 532 2 443 34 048 80,3% 100,0%
s1423 220 382 13 462 69 524 90,2% 99,1%
s5378 430 1 069 40 871 457 532 82,0% 99,8%
benchmark circuits ISCAS’89 with internal scan chains. Two method based on the skewed-load test principle generates a
parameters were observed: the transition fault coverage and delay fault test which is suitable for test wrappers with the
the test application time. simple boundary scan chain; this eliminates the necessity to
The SfW method was developed with the goal to reduce use the extended boundary scan chain for the application of
the application time for delay test through a core wrapper. a delay fault test. The test generated by the SfW method is
The test application time depends on the length of the test multiple times shorter in comparison with the standard delay
sequence. As mentioned earlier, the application of the standard test application. The SfW method offers a good alternative
deterministic delay test in the embedded cores is provided to other approaches which use the enhanced scan cells or
through the core wrapper with extended scan cells. For this assistance of surrounding cores.
application type, the test sequence is given by equation 2×D×
ACKNOWLEDGMENT
N where D represents the number of vector-pairs and N is the
number of core inputs (the length of input scan chain). Table II This work has been supported by Slovak national project
reports the experimental results for the proposed SfW method VEGA 2/0135/08.
and Priority-based Extension method [11]. For the majority R EFERENCES
of the presented circuits, the number of m-vectors is smaller
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