This document discusses types of adders and provides details on half adders and full adders. It begins by identifying half adders and full adders as types of adders. It explains that digital computers perform arithmetic operations like addition and the basic operation is adding two binary digits. When adding more than two bits, the operation is called a full adder. Truth tables are provided for half adders and full adders. The document then shows the simplified sum of products form for a full adder using K-maps and provides the logic diagram. It concludes with assigning short notes on topics like manufacturing testing, functional testing, files and text I/O, and differentiating CPLD and FPGA architectures.

1. DESIGN OF
ADDERS
BY
R.PRABHU
132912
01-4-2015

2. TYPES OF ADDER:
HALF ADDER
FULL ADDER

3. INTRODUCTION:
 Digital computers perform various arithmetic operation
 Basic arithmetic operation is addition of two binary digits.
 The first three operations produce a sum whose length is one
digit but when the last operation is performed sum is two digits.
 The higher bit is called carry.
 And lower bit is called sum.
 This operation is called half adder.
 The circuit which performs addition of three bits is a full adder.

4. HALF ADDER:
TRUTH TABLE:

5. FULL ADDER:
TRUTH TABLE:
 S UM= Sm(1,2,4,7)
 CARRY = Sm(3,5,6,7)

6. Using K-map, simplified SOP form is:
C = XY + XZ + YZ
S = X'Y'Z + X'YZ'+XY'Z'+XYZ
1
0 1
1 0
00
YZ
0
0 1
1 0
01
11
10
X 1
0 0
0 1
00
YZ 0
1 1
0 1
01
11
10
X
0
1
3
2
0
1
3
2
4
5
7
6
4
5
7
6
Z

7. LOGIC DIAGRAM:
 C = XY + (XY)Z
 S = XYZ
X
Y S
C
Z
(XY)

8. Assignment
WRITE A SHORT NOTES ON
1. MANUFACTURING TESTING.
2. FUNCTIONAL TESTING.
3. FILES AND TEXT I/O.
4. DIFFERENTIATE THE CPLD AND FPGA
ARCHITECTURE.

9. Test Benches
 Testing a design by simulation
 Use a test bench model
 an architecture body that includes an instance of the design under test
 applies sequences of test values to inputs
 monitors values on output signals
 either using simulator
 or with a process that verifies correct operation

10. Test Bench Example
entity test_bench is
end entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process is
begin
d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns;
en <= ’0’; clk <= ’0’; wait for 20 ns;
en <= ’1’; wait for 20 ns;
clk <= ’1’; wait for 20 ns;
d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns;
en <= ’0’; wait for 20 ns;
…
wait;
end process stimulus;
end architecture test_reg4;

11. Introduction
What is a VHDL test bench?
Test bench structures
Examples

12. What Is The VHDL Test Bench (TB)?
VHDL test bench (TB) is a piece of VHDL code, which
purpose is to verify the functional correctness of HDL
model.
The main objectives of TB is to:
– Instantiate the design under test (DUT)
– Generate stimulus waveforms for DUT
– Generate reference outputs and compare them with the
outputs of DUT
– Automatically provide a pass or fail indication
Test bench is a part of the circuits specification.
Its a good idea to design the test bench before the DUT,
why?

13.  Simple Test Bench
 Only the DUT is instantiated into test bench.
 Stimulus is generated inside the test bench
 Poor reusability.
 Suitable only for relatively simple designs.

14. THANKING YOU