Digital System Design Lab Report - VHDL ECE

NATIONAL INSTITUTE OF TECHNOLOGY CALICUT
Department of Electronics and Communication Engineering
Monsoon 2016
EC6101 DIGITAL SYSTEM DESIGN LAB REPORT
SUBMITTED BY
BHUKYA RAMESH NAIK

DSD LAB REPORT PART A SEPTEMBER 2016
BHUKYA RAMESH NAIK Page 2
INDEX
MODULE MODEL PROGRAM PAGE
I. DATA FLOW MODEL
1. HALF ADDER 3
2. FULL ADDER 6
3. COMPARATOR (4 BIT) 10
4. SHIFT REGISTER (16 BIT AND 64 BIT) 15
5. MULTIPLEXER 2x1 WITH TRISTATING 19
6. DECODER 2x4 WITH TRI STATING 22
II. BEHAVIORAL MODEL
1. COUNTER (UP/DOWN DECADE) 26
2. BCD SUBTRACTOR AND ADDER 31
3. FLIP FLOPS (JK FF,D FF,T FF) 35
4. MEMORY 47
5. LIFO STACK 51
6. FIFO STACK 55
III. STRUCTURAL MODEL
1. FULL ADDER 59
2. 4 BIT BINARY ADDER 64
3. 4 BIT COUNTER 69
4. 4 BIT COUNTER (GENERATE STATEMENT) 75
5. 4 BIT SHIFT REGISTER 80
6. 4 BIT RING COUNTER 85
7. 4 BIT TWISTED RING COUNTER 90
IV. DESIGN OF 16 x 4 MEMORY 95
V. DESIGN OF 64 x 8 MEMORY 100

MODULE I: Design the following in Data flow model.
1.HALF ADDER:
Aim: To implement a half adder using VHDL in data flow model.
Software: Xilinx ISE Design Suite 13.2 with ISim (VHDL/Verilog) simulator.
Theory of operation: This program can add input Boolean variables A and B. According to
that it can generates the Sum and the Carry output. It uses one XOR-gate to generate SUM and
one AND-gate to generate Carry.
Truth Table:
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_df is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half_df;
architecture Behavioral of half_df is
begin
s<= a xor b;
c<= a and b;
end Behavioral;
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sum= A XOR B Carry = A and B

Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_half_df IS
END tb_half_df;
ARCHITECTURE behavior OF tb_half_df IS
COMPONENT half_df
PORT(
a : IN std_logic;
b : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal s : std_logic;
signal c : std_logic;
BEGIN
uut: half_df
PORT MAP (
a => a,
b => b,
s => s,
c => c
);
stim_proc: process
begin
a<='0';b<='0';
wait for 100 ns;
a<='0';b<='1';
wait for 100 ns;
a<='1';b<='0';
wait for 100 ns;
a<='1';b<='1';
wait for 100 ns;
end process;
END;

RTL and Technology Schematic Diagrams:
Fig:RTL Schematic Fig:Technology Schematic
Simulation Waveform:
Fig:Simulation Waveform
Result:
The half adder is designed and same is verified using dataflow model.

2.FULL ADDER:
Aim: To implement a full adder using VHDL in data flow model.
Theory of operation: This program can add input Boolean variables A ,B and Cin. According
to that it can generates the Sum and the Carry output. It uses two XOR-gates to generate Sum and
one AND-gate, one OR-gate and one XOR-gate to generate carry.
Truth Table:
VHDL Code
library IEEE;
entity fulladder is
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
sum<= a xor b xor cin;
carry<= (a and b) or (b and cin) or (cin and a);
end Behavioral;
A B CIN Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum=A xor B xor Cin Carry =(A and B) or (B and Cin) or (Cin and A)

Test Bench
LIBRARY ieee;
ENTITY tb_fulladder IS
END tb_fulladder;
ARCHITECTURE behavior OF tb_fulladder IS
COMPONENT fulladder
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
signal cin : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fulladder PORT MAP (
a => a,
b => b,
cin => cin,
sum => sum,
carry => carry
);
-- Stimulus process
stim_proc: process
begin
a<='0';b<='0';cin<='0';
wait for 100 ns;
a<='0';b<='0';cin<='1';
wait for 100 ns;
a<='0';b<='1';cin<='0';
wait for 100 ns;
a<='0';b<='1';cin<='1';
wait for 100 ns;
a<='1';b<='0';cin<='0';
wait for 100 ns;

a<='1';b<='0';cin<='1';
wait for 100 ns;
a<='1';b<='1';cin<='0';
wait for 100 ns;
a<='1';b<='1';cin<='1';
wait for 100 ns;
wait;
end process;
END;
Fig:RTL Schematic

Fig:Technology Schematic
Result:
The full adder is designed and same is verified using dataflow model.

3.COMPARATOR:
Aim: To implement a comparator using VHDL in data flow model.
Theory: A digital comparator is a hardware electronic device that takes two numbers as input in
binary form and determines whether one number is greater than, less than or equal to the other
number.
Truth Table:
Inputs A>B A<B A=B
A3>B3 X X X H L L
A3=B3 A2>B2 X X H L L
A3=B3 A2=B2 A1>B1 X H L L
A3=B3 A2=B2 A1=B1 A0>B0 H L L
A3=B3 A2=B2 A1=B1 A0=B0 L L H
A3<B3 X X X L H L
A3=B3 A2<B2 X X L H L
A3=B3 A2=B2 A1<B1 X L H L
A3=B3 A2=B2 A1=B1 A0<B0 L H L
Table: 4-bit comparator
VHDL Code
library IEEE;
entity comparator4bit_when_else is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
l : out STD_LOGIC;
e : out STD_LOGIC;
g : out STD_LOGIC);
end comparator4bit_when_else;
architecture Behavioral of comparator4bit_when_else is

begin
l<='1' when (a<b) else '0';
g<='1' when (a>b) else '0';
e<='1' when (a=b) else '0';
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_fourbit_when_else IS
END tb_fourbit_when_else;
ARCHITECTURE behavior OF tb_fourbit_when_else IS
COMPONENT comparator4bit_when_else
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
l : OUT std_logic;
e : OUT std_logic;
g : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal l : std_logic;
signal e : std_logic;
signal g : std_logic;
BEGIN
uut: comparator4bit_when_else PORT MAP (
a => a,
b => b,
l => l,
e => e,
g => g
);
-- Stimulus process

stim_proc: process
begin
a<="1111";b<="1000";
wait for 100 ns;
a<="0111";b<="1000";
wait for 100 ns;
a<="1111";b<="1111";
wait for 100 ns;
end process;
END;
Fig:RTL Schematic

Fig: Simulation Waveform
Result:
The 4 bit comparator is designed and same is verified using dataflow model.

4.Shift Register 16 bit and 64 bit:
Aim: To implement Shift register 16 bit and 64 bitusing VHDL in data flow model.
Theory of operation: This program shift right the value stored in the input register by 1 bit
position when positive edge of the clock encountered and stores the new value in an output register.
VHDL Code
library IEEE;
entity shitreg16and64bit is
Port ( i,j : in STD_LOGIC;
clk : in STD_LOGIC;
shift16,shift64 : in STD_LOGIC;
q1 : out STD_LOGIC_vector(15 downto 0);
q2 : out STD_LOGIC_vector(63 downto 0));
end shitreg16and64bit;
architecture Behavioral of shitreg16and64bit is
signal s:std_logic_vector(15 downto 0):=x"FFFF";
signal y:std_logic_vector(63 downto 0):=x"FFFFFFFFFFFFFFFF";
begin
s<=i & s(15 downto 1) when clk='1' and clk'event and shift16='1'else s;
q1<=s;
y<=y(62 downto 0)& j when clk='1' and clk'event and shift64='1' else y;
q2<=y;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_shift16and64bit IS
END tb_shift16and64bit;
ARCHITECTURE behavior OF tb_shift16and64bit IS
COMPONENT shitreg16and64bit
PORT(
i : IN std_logic;
j : IN std_logic;
clk : IN std_logic;
shift16 : IN std_logic;
shift64 : IN std_logic;

q1 : OUT std_logic_vector(15 downto 0);
q2 : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal i : std_logic := '0';
signal j : std_logic := '0';
signal clk : std_logic := '0';
signal shift16 : std_logic := '0';
signal shift64 : std_logic := '0';
--Outputs
signal q1 : std_logic_vector(15 downto 0);
signal q2 : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
uut: shitreg16and64bit PORT MAP (
i => i,
j => j,
clk => clk,
shift16 => shift16,
shift64 => shift64,
q1 => q1,
q2 => q2
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
end process;
-- Stimulus process
stim_proc: process
begin
i<='0';shift16<='1'; j<='0';shift64<='1';wait for 10 ns;
j<='0';shift64<='1';wait for 10 ns;

wait;
end process;
END;
Fig:RTL Schematic

Result:
Shift registers of 16 bit and 64 bit are designed and same are verified using dataflow model.

5. MULTIPLEXER WITH TRI-STATE:
Aim: To implement Multiplexer 2x1 with tri-state input using VHDL in data flow model.
Theory of operation: This program builds a 2:1 multiplexer which functions only when the
tri-state input is high else enter into high impedance state. That is tri-state is like an enable if it is
‘1’ then output will depend on select line and if tri-state is 0 then output remain in high impedance
state.
VHDL Code
library IEEE;
entity mux_2x1_tristate is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
en : in std_logic;
o : out STD_LOGIC);
end mux_2x1_tristate;
architecture Behavioral of mux_2x1_tristate is
begin
o<=((not s) and i0) or (s and i1) when en='1' else '0';
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_mux_2x1_tristate IS
END tb_mux_2x1_tristate;
ARCHITECTURE behavior OF tb_mux_2x1_tristate IS
COMPONENT mux_2x1_tristate
PORT(
i0 : IN std_logic;
i1 : IN std_logic;
s : IN std_logic;
en : IN std_logic;
o : OUT std_logic
);
END COMPONENT;
--Inputs
signal i0 : std_logic := '0';
signal i1 : std_logic := '0';

signal en: std_logic:='0';
signal s : std_logic := '0';
--Outputs
signal o : std_logic;
BEGIN
uut: mux_2x1_tristate PORT MAP (
i0 => i0,
i1 => i1,
en => en,
s => s,
o => o
);
-- Stimulus process
stim_proc: process
begin
i0<='1';i1<='0';en<='0';
s<='1'; wait for 100 ns;
i0<='1';i1<='0';en<='1';
end process;
END;
Fig:RTL Schematic

Result:
Multiplexer 2:1with tristate enable is designed and same are verified using dataflow model.

6. DECODER WITH TRISTATE:
Aim: To implement Decoder 2x4 with tri-state input using VHDL in data flow model.
Theory of operation: This program builds a 2x4 decoder which functions only when the tri-
state input is high else enter into high impedance state. That is tri-state is like an enable if it is ‘1’
then output will depend on inputs and if tri-state is 0 then output remain in high impedance state.
VHDL Code
library IEEE;
entity decoder2x4_tristate is
b : in STD_LOGIC;
enable : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end decoder2x4_tristate;
architecture Behavioral of decoder2x4_tristate is
begin
z(3)<=(a and b) when enable='1' else 'Z';
z(2)<=(a and (not b))when enable='1' else 'Z';
z(1)<=((not a) and b)when enable='1' else 'Z';
z(0)<=((not a) and (not b) )when enable='1' else 'Z';
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_decoder2x4_tristate IS
END tb_decoder2x4_tristate ;
ARCHITECTURE behavior OF tb_decoder2x4_tristate IS
COMPONENT decoder2x4_tristate
PORT(
a : IN std_logic;
b : IN std_logic;
enable : IN std_logic;
z : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal enable : std_logic := '0';
--Outputs
signal z : std_logic_vector(3 downto 0);
BEGIN
uut: decoder2x4_tristate PORT MAP (
a => a,
b => b,
enable => enable,
z => z
);
-- Stimulus process
stim_proc: process
begin
a<='0';b<='0';enable<='1';
wait for 100 ns;
a<='0';b<='1';enable<='0';
wait for 100 ns;
a<='1';b<='0';enable<='1';
wait for 100 ns;
a<='1';b<='1';enable<='0';
wait for 100 ns;
a<='0';b<='0';enable<='0';
wait for 100 ns;
a<='0';b<='1';enable<='1';
wait for 100 ns;
a<='1';b<='0';enable<='0';
wait for 100 ns;
a<='1';b<='1';enable<='1';
wait for 100 ns;
wait;
end process;
END;

Fig:RTL Schematic

Result:
Decoder 2x4 with tristate enable input is designed and same are verified using dataflow model.

MODULE II: Design the following in Behavioral model (Process model).
1. BINARY UP/DOWN DECADE COUNTER:
Aim: To simulate 4 bit UP/DOWN decade counter using VHDL in process model.
Theory of operation: A counter which is reset at 10th
clock pulse is called decade counter.
The decade counter is otherwise is called divide by 10 counter, MOD-10 counter or BCD counter.
A decade counter is one that counts in decimal digits, rather than binary. A decade counter is a
binary counter that is designed to count to 1010, or 10102.It counts from 0 to 9 and then resets to
zero. The counter output can be set to zero by the reset input. The count then increments or
decrements on each clock pulse until it reaches 1001 (decimal 9).
Truth Table:
UP decade count DOWN decade count
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
On 10th
clock pulse it is reset to “0000”
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
On 10th
clock pulse it is reset to “1001”

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decade_counter is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
qout_up : out std_logic_vector(3 downto 0);
qout_down : out std_logic_vector(3 downto 0));
end decade_counter;
architecture Behavioral of decade_counter is
signal count1:std_logic_vector(3 downto 0):=x"0";
signal count2:std_logic_vector(3 downto 0):=x"9";
begin
process(clk,reset)
begin
if(reset='1')then
count1<=x"0";
count2<=x"9";
elsif(rising_edge(clk) and count1<10 and count2>0) then
count1<=count1+1;
count2<=count2-1;
end if;
qout_up<=count1;
qout_down<=count2;
end process;
end Behavioral;
Test Bench
LIBRARY ieee;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_decade_counter IS
END tb_decade_counter;
ARCHITECTURE behavior OF tb_decade_counter IS
COMPONENT decade_counter
PORT(
reset : IN std_logic;
clk : IN std_logic;
qout_up : OUT std_logic_vector(3 downto 0);
qout_down : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal reset : std_logic := '0';
--Outputs
signal qout_up : std_logic_vector(3 downto 0);
signal qout_down : std_logic_vector(3 downto 0);
BEGIN
uut: decade_counter PORT MAP (
reset => reset,
clk => clk,
qout_up => qout_up,
qout_down => qout_down
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1'; wait for 10 ns;
reset<='0'; wait for 200 ns;
wait;
end process;
END;

Fig:RTL Schematic

Result:
Decade up/down counter is designed and same are verified using behavioral model.

2. BCD SUBTRACTOR AND ADDER:
Aim:To simulate a 4 bit BCD subtractor and adder using VHDL in process model.
Theory of Operation:
In this code, each decimal digit, 0 troughs 9, is coded by a 4-bit binary number. It is also
called natural binary code because of the 8-4-2-1 weighs attached to it. There are six illegal
combinations in this code (1010, 1011, 1100, 1101, 1110 and 1111).
FOR BCD Addition :
The BCD addition is performed individually adding the corresponding digits of the decimal
numbers expressed in 4-bit binary groups starting from the LSD. If there is a carry out of one group
to the next group or if the result is illegal code, then 610 (0110) is added to the sum term of that
group and the resulting carry is added to the next group (This is done trough to skip the six illegal
conditions).
FOR BCD Subtraction:
The BCD Subtraction is performed by subtracting the digits of each 4-bit group of the
subtrahend from the corresponding 4-bit group of the minuend in binary starting from the LSB. If
there is a borrow from the next group, then 610 (0110) is subtracted from the difference term of this
group (This is done trough to skip the six illegal conditions).
VHDL CODE
library IEEE;
USE ieee.std_logic_unsigned.ALL;
entity bcd_add_sub is
port(a,b : in std_logic_vector(3 downto 0);
mode : in std_logic;
sign : out std_logic;
output : out std_logic_vector(4 downto 0)
);
end bcd_add_sub;

architecture Behavioral of bcd_add_sub is
begin
process(a,b,mode)
variable x:std_logic_vector(4 downto 0):="00000";
begin
if(mode='1') then
x:=('0'& a)+('0'& b);
if(x>9) then
x:=x+6;
sign<='0';
else
x := x;
sign<='0';
end if;
elsif(mode='0') then
if(a>b or a=b) then
x:=('0'& a)-('0'& b);
sign<='0';
else
x:=('0'&b)-('0'& a);
sign<='1';
end if;
end if;
output<=x;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
ENTITY tb_bcd_add_sub2 IS
END tb_bcd_add_sub2;
ARCHITECTURE behavior OF tb_bcd_add_sub2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_add_sub
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
mode : IN std_logic;
sign : OUT std_logic;
output : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;

--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal mode : std_logic := '0';
--Outputs
signal sign : std_logic;
signal output: std_logic_vector(4 downto 0);
BEGIN
uut: bcd_add_sub PORT MAP (
a => a,
b => b,
mode => mode,
sign => sign,
output => output
);
-- stimulus process
stim_proc: process
begin
a<="0101";b<="0011"; mode<='1'; wait for 50 ns;
end process;
END;
Fig:RTL Schematic Fig:Technology Schematic

Result:
BCD adder and subtracter is designed and same is verified using behavioral model.

3.1 JK FLIP-FLOP:
Aim: To simulate JK flip-flop using VHDL in process model.
Theory of Operation:The JK flip-flop augments the behavior of the SR flip-flop (J=Set,
K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the
combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a
command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-
flop, i.e., change its output to the logical complement of its current value.
Truth Table:
VHDL CODE
library IEEE;
entity jkflip is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end jkflip;
architecture Behavioral of jkflip is
signal state:std_logic:='0';
signal input:std_logic_vector(1 downto 0);
begin
input<=j&k;
process(j,k,clk)
begin
if(rising_edge(clk)) then
case input is
when "01" => state <= '0';
when "10" => state <= '1';
when "11" => state <= not state;
when others=> null;

end case;
end if;
end process;
q <= state;
qbar <= not state;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tb_jkflip IS
END tb_jkflip;
ARCHITECTURE behavior OF tb_jkflip IS
COMPONENT jkflip
PORT(
j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal j : std_logic := '0';
signal k : std_logic := '0';
--Outputs
signal q : std_logic;
signal qbar : std_logic;
BEGIN
uut: jkflip PORT MAP (
j => j,
k => k,
clk => clk,
q => q,
qbar => qbar
);

begin
clk <= '1';
clk <= '0';
end process;
stim_proc: process
begin
j<='1';k<='0'; wait for 50 ns;
j<='0';k<='1'; wait for 50 ns;
j<='1';k<='1'; wait for 50 ns;
j<='0';k<='0'; wait for 50 ns;
end process;
END;
Fig:RTL Schematic

Result:
JK flip flop is designed and same is verified using behavioral model.

3.2 D FLIP-FLOP:
Aim: To simulate D flip-flop using VHDL in process model.
Theory of Operation: It is also known as a data or delay flip-flop. The D flip-flop captures
the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the
clock). That captured value becomes the Q output. At other times, the output Q does not change.
Truth Table:
VHDL CODE
library IEEE;
entity dflip is
Port ( a,reset : in STD_LOGIC;
clk : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end dflip;
architecture Behavioral of dflip is
signal state:std_logic:='0';
begin
process(clk,reset)
begin
if(reset='1')then
state<='0';
elsif(clk='0'and clk'event)then
state<=a;
end if;
end process;
q <= state;
qbar <= not state;
end Behavioral;
TEST BENCH

LIBRARY ieee;
ENTITY tb_dflip IS
END tb_dflip;
ARCHITECTURE behavior OF tb_dflip IS
COMPONENT dflip
Port ( a,reset : in STD_LOGIC;
clk : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
END COMPONENT;
--Inputs
signal a,reset : std_logic := '0';
--Outputs
signal q,qbar : std_logic;
BEGIN
uut: dflip PORT MAP (
a => a,
reset => reset,
clk => clk,
q => q,
qbar => qbar
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1'; a<='0'; wait for 100 ns;
reset<='0'; a<='1';wait for 100 ns;
a<='0';wait for 100 ns;
end process;
END;

Fig:RTL Schematic

Result:
D flip flop is designed and same is verified using behavioral model.

3.3 T FLIP-FLOP:
Aim: To simulate t flip-flop using VHDL in process model.
Theory of Operation: If the T input is high, the flip-flop changes state ("toggles") whenever
the clock input is high. If the T input is low, the flip-flop holds the previous value.
Truth Table:
VHDL CODE
library IEEE;
entity tflipflop is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end tflipflop;
architecture Behavioral of tflipflop is
signal temp:std_logic;
begin
process(t,clk,reset)
begin
if (reset='1') then
temp<='0';
elsif(clk='1' and clk'event)then
case t is
when '1' => temp <= '0';
when '0' => temp <= '1';
when others => null;
end case;
end if;
end process;
q <= temp;

qbar <= not temp;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tb_tflipflop IS
END tb_tflipflop;
ARCHITECTURE behavior OF tb_tflipflop IS
COMPONENT tflipflop
PORT(
t : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal t : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal q : std_logic;
signal qbar : std_logic;
BEGIN
uut: tflipflop PORT MAP (
t => t,
clk => clk,
reset => reset,
q => q,
qbar => qbar
);
begin
clk <= '1';
clk <= '0';
end process;
-- Stimulus process
stim_proc: process
begin
t<='1';reset<='1'; wait for 100 ns;

t<='0';reset<='0';wait for 100 ns;
t<='0'; wait for 100 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
T flip flop is designed and same is verified using behavioral model.

4.MEMORY 16 BIT
Aim: To simulate memory 16 bit using VHDL in process model .
Theory of Operation: In computing, memory refers to the physical devices used to store
programs (sequences of instructions) or data (e.g. program state information) on a temporary or
permanent basis for use in a computer or other digital electronic device. This stored data or
program can be randomly read or write by some command signal. The command signal should be
READ or WRITE.
Truth Table:
VHDL CODE
library IEEE;
entity memory is
Port ( din : in STD_LOGIC_VECTOR (15 downto 0) ;
dout : out STD_LOGIC_VECTOR (15 downto 0) ;
read1 : in STD_LOGIC;
clk : in std_logic;
writ1 : in STD_LOGIC);
end memory;
architecture Behavioral of memory is
signal memory16 : std_logic_vector(15 downto 0):=x"0000" ;
begin
process(clk)
begin
if(clk='1' and clk'event) then
if(writ1='1' and read1='0') then
memory16<=din;
elsif(read1='1' and writ1='0') then
dout<=memory16;
end if;
end if;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; LIBRARY ieee;
ENTITY tb_mem IS
END tb_mem;

ARCHITECTURE behavior OF tb_mem IS
COMPONENT memory
PORT(
din : IN std_logic_vector(15 downto 0);
dout : OUT std_logic_vector(15 downto 0);
read1 : IN std_logic;
clk : IN std_logic;
writ1 : IN std_logic
);
END COMPONENT;
--Inputs
signal din : std_logic_vector(15 downto 0) := (others => '0');
signal read1 : std_logic := '0';
signal writ1 : std_logic := '0';
--Outputs
signal dout : std_logic_vector(15 downto 0);
BEGIN
uut: memory PORT MAP (
din => din,
dout => dout,
read1 => read1,
clk => clk,
writ1 => writ1
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
din<=x"0001"; read1<='1';writ1<='0';
wait for 100 ns;
din<=x"0001"; read1<='0';writ1<='1';
wait for 100 ns;
din<=x"0010"; read1<='1';writ1<='0';

wait for 100 ns;
din<=x"0011"; read1<='0';writ1<='1';
wait for 100 ns;
din<=x"0011"; read1<='1';writ1<='0';
wait for 100 ns;
end process;
END;
Fig:RTL Schematic

Result:
16 bit memory is designed and same is verified using behavioral model.

5. LIFO:
Aim: To simulate memory LIFO bit using VHDL in process model.
Theory of Operation: Stand for "Last In, First Out." LIFO is a method of processing data in
which the last items or data entered are the first to be removed. This is the opposite of FIFO (First
In, First Out)in which items are removed in the order they have been entered.
To better understand LIFO, imagine stacking a deck of cards by placing one card on top of the
other, starting from the bottom. Once the deck has been fully stacked, you begin to removethe
cards, starting from the top. This process is an example of the LIFO method, because the lastcards
to be placed on the deck are the first ones to be removed.The LIFO method is sometimes used by
computers when extracting data from an array or data buffer.
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_Arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity lifo is
Port ( clk,pop,push : in STD_LOGIC;
stack_full,stack_empty: out std_logic;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end lifo;
architecture Behavioral of lifo is
type stack is array(7 downto 0) of std_logic_vector(15 downto 0);
signal temp:stack;
begin
write_1:process(clk,data_in,push,pop)
variable a: integer :=0;
begin
if clk'event and clk='1' then
if push='1' and pop='0' then
if a<8 then
temp(a)<= data_in;
a:=a+1;
stack_full<='0';
else
stack_full<='1';
end if;
end if;
end if;
end process write_1;
read_1:process(clk,data_in,push,pop)
variable b: integer :=7;
begin

if pop='1' and push='0' then
if b>=0 then
data_out<=temp(b);
b:=b-1;
else
stack_empty<='1';
end if;
end if;
end if;
end process read_1;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_arith.ALL;
ENTITY tb_lifo IS
END tb_lifo;
ARCHITECTURE behavior OF tb_lifo IS
COMPONENT lifo
PORT(
clk : IN std_logic;
pop : IN std_logic;
push : IN std_logic;
stack_full : OUT std_logic;
stack_empty : OUT std_logic;
data_in : IN std_logic_vector(15 downto 0);
data_out : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal pop : std_logic := '0';
signal push : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal stack_full : std_logic;
signal stack_empty : std_logic;
signal data_out : std_logic_vector(15 downto 0);
BEGIN
uut: lifo PORT MAP (

clk => clk,
pop => pop,
push => push,
stack_full => stack_full,
stack_empty => stack_empty,
data_in => data_in,
data_out => data_out
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
data_in <= x"f123",x"E234" after 10 ns,x"D465" after 20ns,x"C398" after 30ns,
x"B638" after 40 ns,x"A629" after 50 ns, x"C192" after 60ns,
x"E340" after 70 ns;
push<= '1','0' after 90 ns;
pop<= '0','1' after 90 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
LIFO is designed and same is verified using behavioral model.

6. FIFO:
Aim: To simulate memory FIFO using VHDL in process model.
Theory of Operation: Stand for "First In, First Out." LIFO is a method of processing data in
which the First items or data entered are the first to be removed. This is the opposite of LIFO.To
better understand LIFO, imagine stacking a deck of cards by placing one card on top of the other,
starting from the bottom. Once the deck has been fully stacked, you begin to remove the cards,
starting from the bottom. This process is an example of the FIFO method, because the first cards
to be placed on the deck are the first ones to be removed.
VHDL CODE
library IEEE;
entity fifo is
Port ( data_in : in std_logic_vector(15 downto 0);
Clk : in STD_LOGIC;
push,pop : in STD_LOGIC;
data_out : out STD_LOGIC_vector(15 downto 0);
stack_full,stack_empty: out STD_LOGIC );
end fifo ;
architecture Behavioral of lifo is
type stack is array(7 downto 0) of std_logic_vector(15 downto 0);
signal temp:stack;
begin
a1:process(data_in,clk,push,pop)
variable a: integer :=0;
begin
if a<16 then
temp(a)<= data_in ;
a:=a+1;
stack_full<='0';
else
stack_full<='1';
end if;
end if;
end if;
end process a1;
b1:process(data_in,clk,push,pop)
variable b :integer :=0;
begin

if b<16 then
data_out<=temp(b);
b:=b+1;
else
stack_empty<='1';
end if;
end if;
end if;
end process b1;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tb_fifo IS
END tb_fifo;
ARCHITECTURE behavior OF tb_fifo IS
COMPONENT fifo
PORT(data_in : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
push : IN std_logic;
pop : IN std_logic;
data_out : OUT std_logic_vector(15 downto 0);
stack_full : OUT std_logic;
stack_empty : OUT std_logic);
END COMPONENT;
--Inputs
signal data_in : std_logic_vector(15 downto 0) ;
signal push : std_logic := '1';
signal pop : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(15 downto 0);
signal stack_full : std_logic;
signal stack_empty : std_logic;
BEGIN
uut: fifo PORT MAP
( data_in => data_in,
clk => clk,
push => push,
pop => pop,
data_out => data_out,

stack_full => stack_full,
stack_empty => stack_empty);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
data_in<=x"fe00",x"ef01" after 10 ns,x"ff11" after 20 ns,x"aa10" after 30ns,
x"ab01" after 40 ns,x"bc11" after 50 ns,x"cc11" after 60ns,x"cb10"
after 70 ns,x"fc11" after 80 ns,x"ff01" after 90 ns;
pop<='0','1' after 100 ns;
push<='1','0' after 100 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
FIFO is designed and same is verified using behavioral model.

MODULE III: Design the following in Structural model.
1. FULL ADDER:
Aim: To implement a full adder using VHDL in structural model.
Theory of operation: This program can add input Boolean variables A ,B and Cin. According
to that it can generates the Sum and the Carry output. It uses two XOR-gates to generate Sum and
one AND-gate, one OR-gate and one XOR-gate to generate carry.
TRUTH TABLE:
.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; entity fa_struc is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fa_struc;
architecture Behavioral of fa_struc is
A B CIN Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum=A xor B xor Cin Carry =(A and B) or (B and Cin) or (Cin and A)

component halfadd_beh is
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
signal l,m,n:std_logic;
begin
ha1:halfadd_beh port map(x,y,l,m);
ha2:halfadd_beh port map(l,z,sum,n);
carry<= m or n;
end Behavioral;
 Component Code
Code for half adder
library IEEE;
entity halfadd_beh is
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end halfadd_beh;
architecture Behavioral of halfadd_beh is
begin
process(a,b)
begin
if(a='0' and b='0') then s<='0';c<='0';
elsif(a='0' and b='1') then s<='1';c<='0';
end if;
end process;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_fa_struc IS
END tb_fa_struc;

ARCHITECTURE behavior OF tb_fa_struc IS
COMPONENT fa_struc
PORT(
x : IN std_logic;
y : IN std_logic;
z : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
uut: fa_struc PORT MAP (
x => x,
y => y,
z => z,
sum => sum,
carry => carry
);
-- Stimulus process
stim_proc: process
begin
x<='0';y<='0';z<='0';wait for 100 ns;
x<='0';y<='0';z<='1';wait for 100 ns;
x<='0';y<='1';z<='0';wait for 100 ns;
x<='0';y<='1';z<='1';wait for 100 ns;
x<='1';y<='0';z<='0';wait for 100 ns;
x<='1';y<='0';z<='1';wait for 100 ns;
x<='1';y<='1';z<='0';wait for 100 ns;
x<='1';y<='1';z<='1';wait for 100 ns;
end process;
END;

Fig:RTL Schematic

Result:
The full adder is designed and same is verified using structural model.

2. 4 BIT BINARY ADDER:
Aim: To implement a 4 bit binary adder using VHDL in structural model.
Theory of operation: A full adder is capable of adding two 1-bit binary numbers and a carry-
in. When two N-bit binary numbers are to be added, the number of full adder required will be equal
to the number of bits N in each number. So the 4-bit binary adder required 4 full adders. In which
the carry out of each full adder is the carry in of next higher order full adder. A parallel adder is
used to add two numbers in parallel form and to produce the sum bits as parallel outputs.
VHDL Code
library IEEE;
entity binadd_stru is
port(x:in std_logic_vector (3 downto 0);
y:in std_logic_vector (3 downto 0);
zin:in std_logic;
rst1:in std_logic;
s1:out std_logic_vector (3 downto 0);
c1:out std_logic
);
end binadd_stru;
architecture Behavioral of binadd_stru is
component fulladd_beh is
port(a,b,cin,rst : in std_logic;
sum,carry : out std_logic);
end component;
signal temp:std_logic_vector(2 downto 0);
begin
fa1:fulladd_beh port map(x(0),y(0),zin,rst1,s1(0),temp(0));
fa2:fulladd_beh port map(x(1),y(1),temp(0),rst1,s1(1),temp(1));
fa3:fulladd_beh port map(x(2),y(2),temp(1),rst1,s1(2),temp(2));
fa4:fulladd_beh port map(x(3),y(3),temp(2),rst1,s1(3),c1);
end Behavioral;

 Component Code
Code for Full adder
library IEEE;
entity fulladd_beh is
port(a,b,cin,rst : in std_logic;
sum,carry : out std_logic);
end fulladd_beh;
architecture Behavioral of fulladd_beh is
begin
process(a,b,cin,rst)
begin
if(a='0' and b='0' and cin='0') then sum<='0';carry<='0';
elsif(a='0' and b='0' and cin='1') then sum<='1';carry<='0';
end if;
end process;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_binadd_stru IS
END tb_binadd_stru;
ARCHITECTURE behavior OF tb_binadd_stru IS
COMPONENT binadd_stru
PORT(
x : IN std_logic_vector(3 downto 0);
y : IN std_logic_vector(3 downto 0);
zin : IN std_logic;
rst1 : IN std_logic;
s1 : OUT std_logic_vector(3 downto 0);

c1 : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic_vector(3 downto 0) := (others => '0');
signal y : std_logic_vector(3 downto 0) := (others => '0');
signal zin : std_logic := '0';
signal rst1 : std_logic := '0';
--Outputs
signal s1 : std_logic_vector(3 downto 0);
signal c1 : std_logic;
BEGIN
uut: binadd_stru PORT MAP (
x => x,
y => y,
zin => zin,
rst1 => rst1,
s1 => s1,
c1 => c1
);
-- Stimulus process
stim_proc: process
begin
rst1<='1';wait for 100 ns;rst1<='0';
x<="0001";y<="0001";wait for 100 ns;
x<="0011";y<="0001";wait for 100 ns;
x<="0101";y<="0001";wait for 100 ns;
x<="0001";y<="0111";wait for 100 ns;
x<="0001";y<="0001";wait for 100 ns;
x<="1001";y<="0001";wait for 100 ns;
x<="1101";y<="0001";wait for 100 ns;
x<="1101";y<="0001";wait for 100 ns;
x<="1101";y<="0001";wait for 100 ns;
x<="1111";y<="0001";wait ;
end process;
END;

Fig:RTL Schematic

Result:
The 4 bit binary adder is designed and same is verified using structural model.

3. 4 BIT COUNTER:
Aim: To implement a 4 bit counter using VHDL in structural model.
Theory of operation: A binary counter is a machine (like a computer) which counts in binary.
A counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. A digital circuit which has a
clock input and a number of count outputs which give the number of clock cycles. The output may
change either on rising or falling clock edges. The circuit may also have a reset
input which sets all outputs to zero when asserted.
TRUTH TABLE:
VHDL Code
library IEEE;
entity SUN_DOWN_COU is
Port ( J,K,PRE,RT,CLK : in STD_LOGIC;
Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0));
end SUN_DOWN_COU;
architecture Behavioral of SUN_DOWN_COU is
signal s1,s2,s3: STD_LOGIC;

component JK_FF
Port ( J,K,PRE,RT,CLK : in STD_LOGIC;
Q,Qbar : inout STD_LOGIC);
end component;
component And_gate_2_input
port (a,b: in std_logic;
Z: out std_logic);
end component;
begin
s1<=Qbar(0);
TS5: And_gate_2_input port map(Q(1),Q(0),s2);
TS6: And_gate_2_input port map(s2,Q(2),s3);
TS1: JK_FF port map('1','1',PRE,RT,CLK,Q(0),Qbar(0));
TS2: JK_FF port map(s1,s1,PRE,RT,CLK,Q(1),Qbar(1));
end Behavioral;
 Component Code
Code for JK Flip Flop
library IEEE;
entity JK_FF is
Port ( J,K,preset,rst,clk : in STD_LOGIC;
Q,Qbar : out STD_LOGIC);
end JK_FF;
architecture Behavioral of JK_FF is
signal w: std_logic:='0';
begin
JK_FF: process(preset,rst,clk,J,K)
begin
if preset='0' and rst='1' then
w<= '0';
elsif preset='1' and rst='0' then
w<= '1';
w<= 'X';
elsif clk='1' and clk'event then
if J='0' and K='0' then
w<=w;

elsif J='0' and K='1' then
w<='0';
w<='1';
w<= not w;
end if;
end if;
end if;
end process;
Q<=w;
Qbar<= not w;
end Behavioral;
Code for AND gate
library IEEE;
entity And_gate_2_input is
Port ( A,B : in STD_LOGIC;
Z : out STD_LOGIC);
end And_gate_2_input;
architecture Behavioral of And_gate_2_input is
begin
Z<= A and B;
end Behavioral;
Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY tb_SUN_DOWN_COU IS
END tb_SUN_DOWN_COU;
ARCHITECTURE behavior OF tb_SUN_DOWN_COU IS
COMPONENT SUN_DOWN_COU
PORT(
J : IN std_logic;
K : IN std_logic;
PRE : IN std_logic;
RT : IN std_logic;
CLK : IN std_logic;
Q : INOUT std_logic_vector(3 downto 0);
Qbar : INOUT std_logic_vector(3 downto 0)
);

END COMPONENT;
--Inputs
signal J : std_logic := '0';
signal K : std_logic := '0';
signal PRE : std_logic := '0';
signal RT : std_logic := '0';
signal CLK : std_logic := '0';
--BiDirs
signal Q : std_logic_vector(3 downto 0);
signal Qbar : std_logic_vector(3 downto 0);
constant CLK_period : time := 10 ns;
BEGIN
uut: SUN_DOWN_COU PORT MAP (
J => J,
K => K,
PRE => PRE,
RT => RT,
CLK => CLK,
Q => Q,
Qbar => Qbar
);
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
RT<='1','0' after 50 ns;
PRE<= '0','0' after 50 ns;
wait;
end process;
END;

Fig:RTL Schematic

Result:
The 4 bit counter is designed and same is verified using structural model.

4. 4 BIT COUNTERS(Generate):
Aim: To implement a 4 bit counter using VHDL in structural model.
Theory of operation: A binary counter is a machine (like a computer) which counts in binary.
A counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. A digital circuit which has a
clock input and a number of count outputs which give the number of clock cycles. The output may
change either on rising or falling clock edges. The circuit may also have a reset
input which sets all outputs to zero when asserted.
TRUTH TABLE:
.

VHDL Code
library IEEE;
entity counter_gen is
Port ( clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0) ;
dbarout : out STD_LOGIC_VECTOR (3 downto 0)) ;
end counter_gen;
architecture Behavioral of counter_gen is
component JK_FF is
Port ( J,K: in STD_LOGIC;
preset,rst: in STD_LOGIC :='0';
clk : in STD_LOGIC;
end component;
signal s :std_logic;
signal clk1:std_logic_vector(4 downto 0);
begin
s<='1';
dout<=clk1(4 downto 1);
clk1(0)<=clk;
G1: for i in 0 to 3 generate
F1: JK_FF port map(J=>s,K=>s,clk=>clk1(i),Q=>clk1(i+1),Qbar=>dbarout(i));
end generate G1;
end Behavioral;
 Component Code
Code for JK Flip Flop
library IEEE;
entity JK_FF is
Port ( J,K,preset,rst,clk : in STD_LOGIC;
end JK_FF;
architecture Behavioral of JK_FF is
signal w: std_logic:='0';
begin
JK_FF: process(preset,rst,clk,J,K)
begin
w<= '0';

w<= '1';
w<= 'X';
elsif clk='1' and clk'event then
if J='0' and K='0' then
w<=w;
w<='0';
w<='1';
w<= not w;
end if;
end if;
end if;
end process;
Q<=w;
Qbar<= not w;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_count_gen IS
END tb_count_gen;
ARCHITECTURE behavior OF tb_count_gen IS
COMPONENT counter_gen
PORT(
clk : IN std_logic;
dout : OUT std_logic_vector(3 downto 0);
dbarout : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
--Outputs
signal dout : std_logic_vector(3 downto 0);
signal dbarout : std_logic_vector(3 downto 0);
BEGIN
uut: counter_gen PORT MAP (
clk => clk,

dout => dout,
dbarout => dbarout
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
clk <= '0';
clk <= '1';
end process;
END;
Fig:RTL Schematic

Result:
The 4 bit counter using generate is designed and same is verified using structural model.

5. 4 BIT SHIFT REGISTER:
Aim: To implement a 4 bit shift register using VHDL in structural model.
Theory of operation: Shift registers are a type of sequential logic circuit, mainly for storage
of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-
flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal
sequence of states. All flip flops are driven by a common clock, and all are set or reset
simultaneously.
VHDL Code
library IEEE;
entity SHIFT_REGISTER is
Port ( D,CLK,RT,PRE : in STD_LOGIC;
SHIFT : inout STD_LOGIC);
end SHIFT_REGISTER;
architecture Behavioral of SHIFT_REGISTER is
Component D_FF
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
PRESET: in STD_LOGIC;
DATA : in STD_LOGIC;
end component;
signal S:STD_LOGIC_VECTOR(7 downto 0);
begin
TS1: D_FF port map (CLK,RT,PRE,D,S(0),S(4));
TS2: D_FF port map (CLK,RT,PRE,S(0),S(1),S(5));
TS3: D_FF port map (CLK,RT,PRE,S(1),S(2),S(6));
TS4: D_FF port map (CLK,RT,PRE,S(2),SHIFT,S(7));
end Behavioral;

 Counter Component Code
D- Flip Flop Code
library IEEE;
entity D_FF is
end D_FF;
architecture Behavioral of D_FF is
begin
process( CLK,RESET)
begin
if PRESET='1' and RESET='0' then
Q<='1';
elsif PRESET='0' and RESET='1' then
Q<='0';
Q<='X';
if CLK='1' and CLK'event then
Q<=DATA;
else
Q<=Q;
end if;
end if;
end process;
Qbar<= not Q;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_SHIFT_REGISTER IS
END tb_SHIFT_REGISTER;
ARCHITECTURE behavior OF tb_SHIFT_REGISTER IS
COMPONENT SHIFT_REGISTER

PORT( D : IN std_logic;
CLK : IN std_logic;
RT : IN std_logic;
PRE : IN std_logic;
SHIFT: inOUT std_logic);
END COMPONENT;
--Inputs
signal D : std_logic := '0';
--BiDirs
signal SHIFT: std_logic;
BEGIN
uut: SHIFT_REGISTER PORT MAP
( D => D,
CLK => CLK,
RT => RT,
PRE => PRE,
SHIFT => SHIFT );
begin
CLK <= '0';
CLK <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
RT<='1','0' after 10 ns;
PRE<='0','1' after 10 ns,'0' after 20 ns;
D<='0' after 20 ns,'1' after 110 ns,'0' after 120 ns;
wait;
end process;

Fig:RTL Schematic

Result:
The 4 bit shift register is designed and same is verified using structural model.

6. 4 BIT RING COUNTER:
Aim: To implement a 4 bit ring counter using VHDL in structural model.
Theory of operation: A ring counter is a Shift Register (a cascade connection of flip-flops)
with the output of the last flip flop connected to the input of the first. It is initialized such that only
one of the flip flop output is 1 while remain is 0. The 1 bit is circulated so the state repeats every
n clock cycles if n flip-flops are used. The "MOD" or "MODULUS" of a counter is the number of
unique states. The MOD of the n flip flop ring counter is n.
It can be implemented using D-type flip.
TRUTH TABLE:

VHDL Code
library IEEE;
entity RING_COUNTER_4_BIT is
Port ( D,CLK,RT,PRE : in STD_LOGIC;
Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0));
end RING_COUNTER_4_BIT;
architecture Behavioral of RING_COUNTER_4_BIT is
component D_FF
end component;
begin
TS1: D_FF port map (CLK,RT,PRE,Q(3),Q(0),Qbar(0));
TS2: D_FF port map (CLK,RT,'0',Q(0),Q(1),Qbar(1));
end Behavioral;
 Ring Counter Component Code
D- Flip Flop Code
library IEEE;
entity D_FF is
end D_FF;
architecture Behavioral of D_FF is
begin
process( CLK,RESET)
begin
Q<='1';
Q<='0';
Q<='X';
Q<=DATA;

else
Q<=Q;
end if;
end if;
end process;
Qbar<= not Q;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_RING_COUNTER_4_BIT IS
END tb_RING_COUNTER_4_BIT;
ARCHITECTURE behavior OF tb_RING_COUNTER_4_BIT IS
COMPONENT RING_COUNTER_4_BIT
PORT(D : IN std_logic;
CLK : IN std_logic;
RT : IN std_logic;
PRE : IN std_logic;
Qbar : INOUT std_logic_vector(3 downto 0) );
END COMPONENT;
--Inputs
--BiDirs
BEGIN
uut: RING_COUNTER_4_BIT PORT MAP
(D => D,
CLK => CLK,
RT => RT,
PRE => PRE,
Q => Q,
Qbar => Qbar );
begin
CLK <= '0';
CLK <= '1';
end process;

-- Stimulus process
stim_proc: process
begin
PRE<='1' after 10 ns,'0' after 20 ns;
RT<='1', '0' after 10 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
The 4 bit Ring counter is designed and same is verified using structural model.

7. 4 BIT TWISTED COUNTER:
Aim: To implement a 4 bit twisted counter using VHDL in structural model.
Theory of operation: A Johnson counter is a modified ring counter, where the inverted output
from the last flip flop is connected to the input to the first. The register cycles through a sequence
of bitpatterns.The MOD of the Johnson counter is 2n if n flip-flops are used. The main advantage
of the Johnson counter is that it only needs half the number of flip-flops compared to the standard
ring counter for the same MOD.
It can be implemented using D-type flip-flops.

TRUTH TABLE:
VHDL Code
library IEEE;
entity JOHN_COUNTER is
Port ( D,CLK,PRE,RT : in STD_LOGIC;
Q,Qbar : inout STD_LOGIC_VECTOR (3 downto 0)); end JOHN_COUNTER;
architecture Behavioral of JOHN_COUNTER is
component D_FF
PRESET : in STD_LOGIC;
end component;
end component;
begin
TS1: D_FF port map (CLK,RT,'0',Qbar(3),Q(0),Qbar(0));
end Behavioral;
 Johson Counter Component Code
Code for D-Flip Flop
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is

PRESET : in STD_LOGIC;
end D_FF;
end D_FF;
architecture Behavioral of D_FF is begin
process( CLK,RESET) begin
Q<='1';
Q<='0';
Q<='X';
Q<=DATA;
else
Q<=Q;
end if; end if; end process;
Qbar<= not Q;
end Behavioral;
Test Bench
LIBRARY ieee;
ENTITY tb_JOHN_COUNTER IS
END tb_JOHN_COUNTER;
ARCHITECTURE behavior OF tb_JOHN_COUNTER IS
COMPONENT JOHN_COUNTER
PORT( D : IN std_logic;
CLK : IN std_logic;
PRE : IN std_logic;
RT : IN std_logic;
Qbar : INOUT std_logic_vector(3 downto 0) );
END COMPONENT;
--Inputs
--BiDirs

BEGIN
uut: JOHN_COUNTER PORT MAP
( D => D,
CLK => CLK,
PRE => PRE,
RT => RT,
Q => Q,
Qbar => Qbar);
begin
CLK <= '0';
CLK <= '1';
end process;
-- Stimulus process stim_proc: process
begin
RT<='1','0' AFTER 10 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
The John Son(twisted ring counter) is designed and same is verified using structural model.

MODULE IV: RAM Memory
Aim: To simulate memory 16x4 using VHDL in process model.
Theory of Operation: Stand Random-access memory (RAM) is a form of computer data
storage. A random-access device allows stored data to be accessed directly in any random order.
Random access memory, or RAM, allows us to store even larger amounts of data.
The basic capabilities of a memory:
– It should be able to store a value.
– We should be able to read the value that was saved.
– We should be able to change the stored value.
A RAM is similar, except that it can store many values.
– An address will specify which memory value we’re interested in.
– Each value can be a multiple-bit word.
A RAM should be able to:
- Store many words, one per address.
-Read the word that was saved at a particular address.
- Change the word that’s saved at a particular address.
– A Chip Select, CS, enables or disables the RAM.
– Address specifies the address or location to read from or write to.
– WR and RD selects between reading from or writing to the memory.
 To write from memory, WR should be set to 1 and RD should be set to 0.
 To read from memory, WR should be set to 0 and RD should be set to 1.
VHDL CODE
library IEEE;
entity RAM is
Port ( INP_DATA : in STD_LOGIC_VECTOR (3 downto 0);
ADDRESS : in STD_LOGIC_VECTOR (3 downto 0);
CLK,RT,CE,WR,RD : in STD_LOGIC;
OPT_DATA : out STD_LOGIC_VECTOR (3 downto 0));
end RAM;

architecture Behavioral of RAM is
signal POSITION : integer range 0 to 15;
type RAM_ARRAY is array (0 to 15) of STD_LOGIC_VECTOR(3 downto 0);
signal temp: RAM_ARRAY;
begin
POSITION<= (CONV_integer(ADDRESS));
process (CLK,RT,WR,RD,CE)
begin
if (CE='0' and RT='0') then
OPT_DATA<="ZZZZ";
elsif (CE='0' and RT='1') then
OPT_DATA<="ZZZZ";
if WR='1' and RD='0' then
temp(position)<=INP_DATA;
elsif WR='0' and RD='1' then
OPT_DATA<=temp(position);
end if;
else
temp(position)<=temp(position);
end if;
end if;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tb_RAM IS
END tb_RAM;
ARCHITECTURE behavior OF tb_RAM IS
COMPONENT RAM
PORT(INP_DATA : IN std_logic_vector(3 downto 0);
ADDRESS : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
RT : IN std_logic;
CE : IN std_logic;
WR : IN std_logic;
RD : IN std_logic;
OPT_DATA : OUT std_logic_vector(3 downto 0) );
END COMPONENT;
--Inputs
signal INP_DATA : std_logic_vector(3 downto 0):=(others => '0');
signal ADDRESS : std_logic_vector(3 downto 0):=(others => '0');

signal CE : std_logic := '0';
signal WR : std_logic := '0';
signal RD : std_logic := '0';
--Outputs
signal OPT_DATA : std_logic_vector(3 downto 0);
BEGIN
uut: RAM PORT MAP
( INP_DATA => INP_DATA,
ADDRESS => ADDRESS,
CLK => CLK,
RT => RT,
CE => CE,
WR => WR,
RD => RD,
OPT_DATA => OPT_DATA);
begin
CLK <= '0';
CLK <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
RT<='1','0' after 10 ns;
CE<='0' after 5 ns,'1' after 10 ns;
WR<='1' after 20 ns,'0' after 100 ns;
RD<='1' after 100 ns;
ADDRESS <= X"0",X"1" after 20 ns,X"A" after 30 ns,X"5" after 40ns,X"4" after 50
ns,X"3" after 60 ns,X"8" after 70 ns,X"6" after 80 ns,X"7" after 90 ns,X"9"
after 100 ns,X"0" after 110 ns,X"6" after 120 ns,X"1" after 130 ns,X"7" after
140 ns,X"A" after 150 ns;
INP_DATA<=X"0",X"A" after 20 ns,X"F" after 30 ns,X"C" after 40 ns,X"E" after 50
ns,X"2" after 60 ns,X"A" after 70 ns,X"B" after 80 ns,X"6" after 90 ns,X"5"
after 100 ns,X"8" after 110 ns,X"4" after 120 ns,X"D" after 130 ns,X"1" after
140 ns,X"9" after 150 ns;
wait;
end process;
END;

Fig:RTL Schematic

Result:
16x4 memory is designed and same is verified using behavioral model.

MODULE V: 64 X 8 Memory
Aim: To simulate memory 64x8 using VHDL in process model.
Theory of Operation: The 64 X 8 memory can be making by using 16 X 4 RAM. In which
the 2-bit MSB of address line are uses as the chip enable signal to enable the RAM out of eight 16
X 8 RAM
VHDL CODE
library IEEE;
library work;
entity MEMORY_64X8 is
Port ( IP_DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK,WT,RD,CE,RT : in STD_LOGIC;
OUT_DATA : out STD_LOGIC_VECTOR (7 downto 0);
ADDRESS : in STD_LOGIC_VECTOR (5 downto 0));
end MEMORY_64X8;
architecture Behavioral of MEMORY_64X8 is
signal P: STD_LOGIC_VECTOR(3 downto 0);
component RAM
end component;
for all: RAM use entity WORK.RAM(Behavioral);
begin
TS:for I in 0 to 3 generate
with I select
P(I) <= ((NOT ADDRESS(5)) and (NOT ADDRESS(4)))and CE when 0,(NOT ADDRESS(5)
and ADDRESS(4)) and CE when 1,(ADDRESS(5) and (NOT ADDRESS(4))) and CE when
2,( ADDRESS(5) and ADDRESS(4)) and CE when others;
TS1: RAM port map (IP_DATA(3 downto 0),ADDRESS(3 downto0),CLK,RT,P(I),WT,RD,
OUT_DATA(3 downto 0));
TS2: RAM port map (IP_DATA(7 downto 4),ADDRESS(3 downto 0),CLK,RT,P(I),WT,RD,
OUT_DATA(7 downto 4));
end generate TS;
end Behavioral;

 Component Code
Code for RAM:
library IEEE;
use IEEE.std_logic_unsigned.all;
entity RAM is
end RAM;
architecture Behavioral of RAM is
signal POSITION : integer range 0 to 15;
type RAM_ARRAY is array (0 to 15) of STD_LOGIC_VECTOR(3 downto 0);
signal temp: RAM_ARRAY;
begin
POSITION<= (CONV_integer(ADDRESS));
process (CLK,RT,WR,RD,CE)
begin
if (CE='0' and RT='0') then
OPT_DATA<="ZZZZ";
OPT_DATA<="ZZZZ";
if WR='1' and RD='0' then
temp(position)<=INP_DATA;
elsif WR='0' and RD='1' then
OPT_DATA<=temp(position);
end if;
else
temp(position)<=temp(position);
end if;
end if;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tb_MEMORY_64X8 IS
END tb_MEMORY_64X8;

ARCHITECTURE behavior OF tb_MEMORY_64X8 IS
COMPONENT MEMORY_64X8
PORT(IP_DATA : IN std_logic_vector(7 downto 0);
CLK : IN std_logic;
WT : IN std_logic;
RD : IN std_logic;
CE : IN std_logic;
RT : IN std_logic;
OUT_DATA : OUT std_logic_vector(7 downto 0);
ADDRESS : IN std_logic_vector(5 downto 0) );
END COMPONENT;
--Inputs
signal IP_DATA : std_logic_vector(7 downto 0):= (others => '0');
signal WT : std_logic := '0';
signal RD : std_logic := '0';
signal CE : std_logic := '0';
signal ADDRESS : std_logic_vector(5 downto 0):= (others => '0');
--Outputs
signal OUT_DATA : std_logic_vector(7 downto 0);
BEGIN
uut: MEMORY_64X8 PORT MAP
( IP_DATA => IP_DATA,
CLK => CLK,
WT => WT,
RD => RD,
CE => CE,
RT => RT,
OUT_DATA => OUT_DATA,
ADDRESS => ADDRESS);
begin
CLK <= '0';
CLK <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
IP_DATA<=X"10" after 10 ns,X"15" after 20 ns,X"A0" after 30ns,
X"1B" after 40 ns,X"1F" after 50 ns,X"16" after 60 ns,
X"F0" after 70 ns,X"1C" after 80 ns,X"AC" after 90 ns,
X"10" after 100 ns,X"B0" after 110 ns,X"AF" after 120 ns,
X"BD" after 130 ns,X"1F" after 140 ns,X"0C" after 150 ns;

WT<='1' after 10 ns,'0' after 130 ns;
RD<='1' after 130 ns;
CE<='0','1' after 10 ns;
RT<='1','0' after 10 ns;
ADDRESS<="001010","001011" after 20 ns,"000111" after 30 ns,"011000" after 40
ns,"011111" after 50 ns,"011001"after 60 ns,"100011" after 70 ns,"100001" after
80 ns,"101011" after 90 ns,"101101" after 100 ns,"110111" after 110 ns,"110101"
after 120 ns,"111001" after 130ns,"001011" after 140ns,"011111" after 150
ns,"100011"after 160 ns,"110111" after 170 ns;
wait;
end process;
END;
Fig:RTL Schematic

Result:
64x8 memory is designed and same is verified using behavioral model.

Digital System Design Lab Report - VHDL ECE

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Digital System Design Lab Report - VHDL ECE