The document describes the design and implementation of a three-bit binary adder using discrete gates on an FPGA board. It details the iterative cell design technique, using full and half adder schematics, along with Verilog code representations. A test plan is included to validate the design against truth tables and ensure correct operation.

1. Katrina Little
Experiment #4:
Three- Bit Binary Adder

2. Katrina
Little
Page number 2
OBJECTIVES:
 To design a Binary Adder which will add two binary words (three bits
each) using discrete gates.
 To introduce iterative cell design techniques.
 Expand knowledge of Xilinx’s ISE using buses.
EQUIPMENT LIST:
 FPGA BASYS1 board (Spartan3e, device XC3S100E, package type TQ144)
 Xilinx ISE program
 Flash Drive
 BIT file
BLOCK DIAGRAM:
DESIGN SPECIFICATION PLAN:
A parallel adder is to be designed to add two binary digits (three bits each), X: (X2X1X0)
and Y: (Y2Y1Y0). The adder can be designed using “brute force” method in which, three
six variable Karnaugh Maps are used to implement the functions representing the
outputs of a three-bit addition. Since this method is not very efficient, the iterative cell
technique will be used. With this method, two binary numbers are presented in parallel
to the cell as inputs. The rightmost cell adds the least significant bit (LSB) X0 and Y0 to
form a sum digit S0 and carry digit C0. The next cell adds the carry digit C0 to bits X1 and
Y1 to form a sum digit S1 and a carry digit C1. The last cell adds the Carry C1 to bits X2
and Y2 to form a sum digit S2 and a carry digit Cout.
Figure (1)
One- Bit
Full Adder
Sin
Yin
Xin
Cout
Cin
One- Bit
Half Adder
Sin
Yin Cout
Xin
Figure (2)

3. Katrina
Little
Page number 3
To design a network, a typical cell should be designed which adds a carry Ci to bits Xi
and Yi to generate a sum digit Si and a new Carry Cout as shown in Figure 1 above. The
circuit that realizes this function is referred to as the “full adder” cell. NOTE: this does
not include the carry-in on the LSB of X and Y. Figure 2 represents the “Half-Adder” cell.
The full and half adder only represent 1-bit.
DESIGN METHODOLOGY:
Equations for Full and half adders are as follows:
Half Adder:
Si = Xi Yi
Ci = XiYi
Full Adder:
Si = Xi Yi Ci-1,
Ci= (XiYi) + (XiCi-1) + (YiCi-1)
From the Boolean Algebra it can be seen that the Sums will use an EXOR gate and the Carries will use a
series of AND/OR gates.
Xi Yi Ci Si Ci-1 Xi Yi Si Ci
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 1 0
1 0 0 1 0 1 0 1 0
1 1 1 0 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Figure 3 (above- left) shows the truth table for the half adder and Figure 4 (above-right) shows
the truth table for the Full adder.
3-Bit Binary
Adder
Y2 X2 Y1 X0X1 Y0
Cout S2 S1 S0

4. Katrina
Little
Page number 4
DETAILED SCHEMATIC DIAGRAM:
Xi
Yi
Xi
Yi
Si
Ci
Xi
Ci-1
Yi
Si
Ci
Figure 5 (left ) shows the configuration for
the Half- Adder using 1 AND gate and 1 XOR
gate Half- Adder has two inputs: Xi and Yi
Figure 6 (below) shows the configuration for
the Full-Adder to connect the three inputs:
Xi, Yi, and Ci-1 using 3 AND gates and 2 XOR
gates.

5. Katrina
Little
Page number 5
VERILOG REPRESENTATION OF SCHEMATIC:
module(X,Y,S,C0;
input [2:0]X;
input [2:0]Y;
output [2:0]S;
output C;
wire[2:0] X;
wire[2:0]Y;
wire[2:0]S;
assign S[0] = X[0]^Y[0];
assign S[1] = (X[0]&Y[0]^(X[1]^Y[1]);
assign S[2] =(((X[0]&Y[0])&X[1])) + ((X[0]&Y[0])&Y[1]) +(X[1]&Y[1]))^(X[2]^Y[2]);
assign C = ((((X[0]&Y[0])&X[1]) + ((X[0]&Y[0])&Y[1]) + ((X[1]&Y[1])&X[2]) + ((((X[0]&Y[0])&X[1])
+((X[0]&Y[0])&Y[1]) + (X[1]&Y[1])&Y[2]) +(X[2]&Y[2]);
endmodule
Input/Output Switch LED Pin #
X[0] SW0 38
X[2] SW2 29
Y[0] SW5 12
Y[2] SW7 6
S[0] LED0 15
S[2] LED2 8
Cout LED7 2
Figure 7 (left) displays the Pin connections
for the Switches and LED’s of the inputs and
outputs of the Schematics.

6. Katrina
Little
Page number 6
TEST PLAN (PROCEDURE):
The test plan was broken into three parts essentially:
I. Use the schematic capture tool to create a one bit half adder.
II. Use the schematic capture tool to create a one bit full-adder
III. Using buses for X, Y, and S, connect the one-bit full/half adders
a. Generate a timing diagram (test bench) to cycle through all possible bit
combinations
b. Simulate model behavior
c. Assign Pin connections for LED’s and switches
d. Generate a bit file a program it to the BASYS board.
IV. Use the Verilog language to create the design (Repeat steps a-d in part III)
V. Test your design using switches on the BASYS board and make sure they match truth tables.
I.

7. Katrina
Little
Page number 7
II:
III.

8. Katrina
Little
Page number 8
III.b
IV.

9. Katrina
Little
Page number 9
IV.b:
RESULTS:
The results matched the truth tables in figures 3 and 4.
CONCLUSIONS (QUESTIONS):
1) Using full adder and half adder block diagrams, draw an 8-bit adder
2) Comment on the feasibility of designing an 8-bit adder.
The brute force method would be very time consuming because you would have to use many
Karnaugh maps. Using the iterative method makes more sense because you only have to build truth
tables for a half and full adder
3) Identify the advantages and disadvantages of the brute force method.
The advantage of using the brute force method is that the Karnaugh map would directly indicate
to you the outputs based on the inputs. However, this methodology, initially, is very time
consuming and can require the use of many Karnaugh maps. Karnaugh maps are much easier to
read.

10. Katrina
Little
Page number 10
4) Identify the advantages and disadvantages of the iterative cell method.
The iterative method would require use of Karnaugh maps repeatedly, but construction the 8-bit
adder takes a lot less time The 8 bit-adder is harder to read.
5) Have you met all requirements of the Design Specification plan?
Yes, the full and half adders were constructed and put together using buses. The Verilog
language schematic was also implemented successfully. The Plans were tested on the BASYS
board and functioned as predicted.
6) How should our design be tested (Test Plan)?
See Above
Half
X
0
Y
0
S
0
C
0 FullX
1Y
1
S
1
C
1
FullX
2Y
2
S
2
C
2
Full
C
2X
3Y
3
S
3
C
3 FullX
4Y
4
S
4
C
4 FullX
5Y
5
S
5
C
5
Full
C
5X
6Y
6
S
6
C
6 FullX
7Y
7
S
7
C
7