Leakage power optimization for ripple carry adder by NAVEEN TOKAS

1. SUBMITTED BY:
NAVEEN TOKAS

2.  Day by day IC technology is getting advanced in
terms of style, proportions and its performance
exploration. A fast way with reduced leakage
power and smaller planetary is implied to the
latest electronic style.
 Addition is normally used mathematical process in
silicon chip, DSP etc. It can be used as a basic
block for synthesis of all arithmetic setups. The
binary adder structure becomes an badly
essential hardware unit. In any book on pc
arithmetic, we will detect that there happens an
large variety of rather completely different circuit
designs relating different performance features.
Whereas adders are made for lots of numerical

3.  Ripple carry adder comprises of cascaded full
adders. It is designed by cascading full adder
blocks non-parallel with each other. The output
carry of 1 stage works as input carry for second
stage and so on.
 In other words we can say full adder is basic
building block of ripple carry adder. In this work
we will construct full adder using 3T based logic
gates.
 The design of a ripple-carry adder is simple,
which permits for fast design time; however, the
ripple-carry adder is relatively slow, since each full
adder need to wait for the carry bit to be

5.  Ever since its initiation, the design of full adder
has been experiencing a significant improvement,
which includes three basic design goals for eg.
minimizing the transistor count, reducing the
power consumption and increasing the speed.
 A custom transistor level can be used to
implement full adder circuit or implantation via
composed of other gates. We can understand it
by given equations :
SUM =A B CIN and COUT =
(A*B)+[CIN*(A+B)] .

6.  The 3 transistors based logic gates design is
based on PMOS and NMOS Pass Transistor
Logic (PTL). The 3T universal gates (NAND and
NOR) design is based on CMOS inverter and
PTL. Output voltage deterioration occurs
across the PMOS and NMOS because of
threshold voltage drop while passing the logic 0
or logic 1 respectively in relation to the input. The
voltage deterioration caused by threshold drop
can be extensively minimized by increasing the
W/L ratio of the pass transistor.

7.  XOR gates form the major building block of full
adders. Improving the performance of the XOR
gates can significantly enhance the performance
of the adder. A survey of collected works discloses
a wide range of different types of XOR gates that
have been recognized over the years. The
previous designs of XOR gates were designed by
either eight transistors or six transistors that are
usually used in most designs.
 In this work we are going to use XOR gate with 3T
which can reduce its power consumption,
increase its operating speed and reduce its size.

8.  In previous research we were using GDI
techniques, feed through logic. Now I’m going to
implement ripple carry adder using full adder
which is based on 3T xor gate. By adopting this
method we can reduce area, complexity, and
power consumption, delay and cost of the device.
Because these are most important parameters in
designing a device, for a designer in today’s era.
 Mentor Graphics Corporation today announced a
new version of the transistor-level analog
simulator that offers improved raw speed
performance without compromising accuracy. The
speed up targets very large post-layout
simulations that are mandatory at 45nm
processes and below to thoroughly verify a
complex design.

9.  As discussed above I am going to use 3 transistor
based XOR gate to implement full adder. Full
adder is basic building block of ripple carry adder
so primarily it is necessary to reduce power
dissipation of full adder(FA) for low power ripple
carry adder.
 As we know XOR gate is an essential part of full
adder so we can say that to decrease power
dissipation of FA it is essential to use low power
consuming XOR gate and other elements to
make full adder.
 So I have made a 3 transistor based XOR gate on
mentor graphics software at 35nm technology. On