The document discusses different types of adders used in digital signal processing. It describes half adders and full adders as basic building blocks. It then summarizes several high-speed adder circuits used to address speed limitations in ripple carry adders, including carry lookahead adders. The presentation evaluates adder designs based on their area requirements, maximum operational speeds, and power consumption to determine the best design for different applications.

1. HIGH SPEED ADDER USED IN DSP
HIGH SPEED ADDER USED IN
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
DIGITAL SIGNAL PROCESSING
Presented by
Banasree Nag
Under the guidance of
Mr M. Suresh

2. HIGH SPEED ADDER USED IN DSP
INTRODUCTION
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
Among the various arithmetic operation
addition is the simplest operation.
A combinational circuit that performs the
addition of two bits known as half adder.
And that performs the addition of three bits
known as full adder.
A full adder can be implemented from two
half adders

3. HIGH SPEED ADDER USED IN DSP
HALF ADDER
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
 Half adder circuit
needs two binary
inputs and two
binary outputs
 X and Y to the
inputs and S and C
to the outputs.
U1A
74ALS32
1
2
3
U4A
74ALS808A
1
2
3
S
U2A
74ALS808A
1
2
3
C
X
Y
1 2
U6A
1 2
74ALS35A
U5A
74ALS35A
U3A
74ALS808A
1
2
3

4. HIGH SPEED ADDER USED IN DSP
FULL ADDER
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
X
1
2 12
13
U4A
1
2 12
13
74ALS11A
U6A
1
2 12
13
74ALS11A
Z
U3A
1 2
Y
S
U4A
1
2 12
13
74ALS11A
U7A
74ALS32
1
2
3
U5A
74ALS32
1
2
3
U2A
1 2
U4A
74ALS11A
U1A
1 2
U8A
74ALS32
1
2
3
Z
U10A
74ALS1032A
1
2
3 C
U10A
74ALS1032A
1
2
3
Y
U6A
7408
1
2
3
U5A
7408
1
2
3
U7A
7408
1
2
3
X
Carry of full
adder Sum of full adder

5. HIGH SPEED ADDER USED IN DSP
 This simple adder has some draw back.
 It is slow and it will not produce the
correct result unless the signals are
given enough time to propagate through
the gates connected from the inputs to
the outputs.
 The solution for reducing the delay of
the circuit is to employ faster gates with
reduced delays.
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051

6. HIGH SPEED ADDER USED IN DSP
There is some other adder, which takes minimum time
to perform the addition operation.
These are-
•Ripple Adder,
• Carry Look Ahead Adder,
•Carry Select Adder,
•2’s Complement Adder,
•Conditional Sum Adder,
•Carry Save Adder.
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051

7. HIGH SPEED ADDER USED IN DSP
RIPPLE CARRY ADDER
 In a ripple-carry adder the result of an addition of two
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
bits depends on the carry generated by the addition of
the previous two bits. Thus, the Sum of the most
significant bit is only available after the carry signal
has rippled through the adder from the least
significant stage to the most significant stage.

8. HIGH SPEED ADDER USED IN DSP
DELAY IN RIPPLE CARRY ADDER
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
 In the ripple carry adder, the addition of (1+1 = 102) in
the least significant stage causes a carry bit to be
generated. This carry bit will consequently generate
another carry bit in the next stage, and so on, until the
final carryout bit appears at the output.
 As a result, the final Sum and Carry bits will be valid
after a considerable delay

9. HIGH SPEED ADDER USED IN DSP
CONTINUED…………..
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
The disadvantage of the ripple-carry adder is that it can
get very slow when one needs to add many bits. For
instance, for a 32-bit adder, the delay would be about 66
ns if one assumes a gate delay of 1 ns.

10. HIGH SPEED ADDER USED IN DSP
CARRY LOOK AHEAD ADDERS
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
 For first addition operation the most widely
used is the principle of look-ahead carry.
 Adder design with this consideration in mind
are called high speed adder.

11. Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
HIGH SPEED ADDER USED IN DSP

12. HIGH SPEED ADDER USED IN DSP
DELAY IN CARRY LOOK AHEAD
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
ADDER

13. HIGH SPEED ADDER USED IN DSP
DISCUSSION
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
The implementation of six adder structures
is presented.

14. Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
HIGH SPEED ADDER USED IN DSP
ACTIVE CAPACITANCE

15. Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
HIGH SPEED ADDER USED IN DSP
MAXIMUM OPERATION FREQUENCY

16. HIGH SPEED ADDER USED IN DSP
10. CONCLUSION
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
 Most of the adder structures discussed in this
paper are applicable to general-purpose designs,
with a few exceptions.
 This paper has presented a comprehensive
comparison of the six most commonly used
adder structures.

17. HIGH SPEED ADDER USED IN DSP
Technical Seminar Presentation 2004 Presented by – Banasree Nag EI200198051
 A detailed analysis of the area requirement, the
maximum operational speed and the power
consumption has provided a convenient way to
compare the advantages and trade-offs of each
design. Thus, the adder best suited to any given
design may be easily selected using the data
presented.
THANK YOU……
continued……..