Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz. Simulate, synthesize and physical design your adder. Follow the directions below to create the 32-bit CSA • Create a 4-bit Carry Look Ahead (CLA) adder • combine 8-stages of the CLA adder to create the 32-bit CSA • use 4-bit 2-to-1 mux to choose the sum from each set of CLA • use 1-bit 2-to-1 mux to select the carry for the next stage