The document provides an overview of the 8086 microprocessor, including: - It was launched by Intel in 1978 and has a 16-bit data bus, 20-bit address bus, and 4-bit control bus. - The 8086 uses parallel processing with a bus interface unit that fetches instructions and data and an execution unit that decodes and executes instructions. - It has 14 16-bit registers including general purpose registers, segment registers, flags register, instruction pointer register, and pointer/index registers. - The 8086 can address up to 1MB of memory using segmentation and can prefetch multiple instructions via pipelining to improve performance.

1. Introduction to 8086
Microprocessor
Presented by :
Ahmed Abdel Hafeez
Supervised By:
DR/ Gamal Selim

2. What’s next?
 History
 8086 Overview
 8086 Internal Architecture
 Architecture Diagram of 8086
 Registers
 Pipelining
 Memory Segmentation
 Interrupts
 Instruction set
 Pin diagram of 8086 Microprocessor
 References

3. History
(List of Intel microprocessors)
 The 4-bit processors
4004, 4040
 The 8-bit processors
8008, 8080, 8085
 The 16-bit processors: Origin of x86
8086, 8088, 80186, 80188, 80286
 The 32-bit processors: Non x86
iAPX 432, 80960, 80860, XScale
 The 32-bit processors: The 80386 Range
80386DX, 80386SX, 80376, 80386SL, 80386EX
 The 32-bit processors: The 80486 Range
80486DX, 80486SX, 80486DX2, 80486SL, 80486DX4
 The 32-bit processors: The Pentium (“I”)
Pentium, Pentium MMX
 The 32-bit processors: P6/Pentium M
Pentium Pro, Pentium II, Celeron, Pentium III, PII and III Xeon
Celeron(PIII), Pentium M, Celeron M, Intel Core, Dual Core Xeon LV
 The 32-bit processors: NetBurst microarchitecture
Pentium 4, Xeon, Pentium 4 EE
 The 64-bit processors: IA-64
Itanium, Itanium 2
 The 64-bit processors: EM64T-NetBurst
Pentium D, Pentium Extreme Edition, Xeon
 The 64-bit processors: EM64T- Core microarchitecture
Xeon, Intel Core 2

4. 8086 Microprocessor
Belongs to a popular microprocessor
series
• 8086, 80186, 80286, 80386, 80486, Pentium
INTEL launched 8086 in 1978
8086 is a 16-bit microprocessor with
• 16-bit Data Bus
• 20-bit Address Bus
• 4-bit Control Bus

5. 8086 Overview
Having Total 40 Pins.
HMOS Microprocessor.
Consumes Low Power (i.e. 360 mA on
5v).
Clock Frequencies of 5,8 &10 MHz.
Contains About 29000 Transistors.
Can Address up to 1 Mbytes of Memory.
It has more than 20,000 instructions.
Provides fourteen 16-Bit registers. 5

6.  It requires single phase clock with 33% duty
cycle to provide internal timing.
 • 8086 is designed to operate in two modes,
Minimum and Maximum.
 • It can prefetches up to 6 instruction bytes from
memory and queues them in order to speed up
instruction execution.
 Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has a
separate address.
8086 Overview

7. 8086 Internal Architecture
 8086 employs parallel processing
 8086 CPU has two parts which operate at the
same time
• Bus Interface Unit
• Execution Unit
 CPU functions
1. Fetch
2. Decode
3. Execute
8086 CPU
Bus Interface
Unit (BIU)
Execution Unit
(EU)

8. Bus Interface Unit
Sends out addresses for memory
locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input/Output ports

9. Execution Unit
Tells BIU (addresses) where to fetch
instructions or data
Decodes & Executes instructions
Dividing the work between BIU & EU
speeds up processing

10. Architecture Diagram of 8086

11. AH AL
BH BL
CH CL
DH DL
STACK POINTER (SP)
BASE POINTER (BP)
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
EXTRA SEGMENT (ES)
CODE SEGMENT (CS)
STACK SEGMENT (SS)
DATA SEGMENT (DS)
INSTRUCTION POINTER (IP)
CONTROL
SYSTEM
6 5 4 3 2 1
ARITHMETIC
LOGIC UNIT
FLAGS
Instruction Queue
OPERANDS
∑
Memory
Interface
EU
BIU
Instruction
Decoder

12. Execution Unit
Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers

13. Instruction Decoder
 Translates instructions fetched from memory
into a series of actions which EU carries out
Control System
 Generates timing and control signals to
perform the internal operations of the
microprocessor
Arithmetic Logic Unit
 EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers

14. Registers
General purpose Segment

15. General Purpose Registers
 EU has 8 general
purpose registers
 Can be individually
used for storing 8-bit
data
 AL register is also
called Accumulator
 Two registers can also
be combined to form
16-bit registers
 The valid register pairs
are – AX, BX, CX, DX
AH AL
BH BL
CH CL
DH DL
AH AL AX
BH BL BX
CH CL CX
DH DL DX

16. EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O
(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register) 16

17. Pointer And Index Registers
 used to keep offset addresses.
 Used in various forms of memory addressing.
 In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be
discussed under the BIU)
 The index registers (SI & DI) and the BX generally default
to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

18.  SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI
register points to memory locations in the data segment
which is addressed by the DS register. Thus, SI is
associated with the DS in string operations.
 DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register. Thus,
DI is associated with the ES in string operations.
 The SI and the DI registers may also be used to access
data stored in arrays

19. Flag Register
 A flag is a flip flop which indicates some conditions
produced by the execution of an instruction or
controls certain operations of the EU .
 8086 has a 16-bit flag register
 Contains 9 active flags
 There are two types of flags in 8086
• Conditional flags – six flags, set or reset by EU on
the basis of results of some arithmetic operations
• Control flags – three flags, used to control
certain operations of the processor

20. U U U U OF DF IF TF SF ZF U AF U PF U CF
Flag Register
1. CF CARRY FLAG Conditional Flags
(Compatible with 8085,
except OF)
2. PF PARITY FLAG
3. AF AUXILIARY CARRY
4. ZF ZERO FLAG
5. SF SIGN FLAG
6. OF OVERFLOW FLAG
7. TF TRAP FLAG
Control Flags
8. IF INTERRUPT FLAG
9. DF DIRECTION FLAG

21. EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic
instruction
execution. S=1; negative, S=0 21

22. Flag Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging
feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
Overflow occurs when signed numbers are added or
subtracted. An overflow indicates the result has exceeded
the capacity of the Machine
22

23. Execution unit – Flag Register
 Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
 For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
23

24. Bus Interface Unit
Main Components are
• Instruction Queue
• Segment Registers
• Instruction Pointer

25. AH AL
BH BL
CH CL
DH DL
STACK POINTER (SP)
BASE POINTER (BP)
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
EXTRA SEGMENT (ES)
CODE SEGMENT (CS)
STACK SEGMENT (SS)
DATA SEGMENT (DS)
INSTRUCTION POINTER (IP)
CONTROL
SYSTEM
6 5 4 3 2 1
ARITHMETIC
LOGIC UNIT
FLAGS
Instruction Queue
OPERANDS
∑
Memory
Interface
EU
BIU
Instruction
Decoder

26. Instruction Queue
 8086 employs parallel processing
 When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
 At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
 BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
 When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU

27. Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Fetching the next instruction while the
current instruction executes is called
pipelining

28. Segmented Memory
Code segment (64KB)
Data segment (64KB)
Extra segment (64KB)
Stack segment (64KB)
28
1MB
 8086 has a 20-bit
address bus So it can
address a maximum of
1MB of memory
 8086 can work with only
four 64KB segments at
a time within this 1MB
range
 The Complete
physically available
memory may be divided
into a number of logical
segments.
00000
FFFFF
Physical Memory

29. Code Segment
 That part of memory from where BIU is
currently fetching instruction code bytes
Stack Segment
 A section of memory set aside to store
addresses and data while a subprogram
executes
Data & Extra Segments
 Used for storing data values to be used in the
program

30. Address of a segment is 20-bits
A segment register stores only upper 16-
bits
BIU always inserts zeros for the lowest 4-
bits of the 20-bit starting address.
E.g. if CS = 348AH, then the code
segment will start at 348A0H
A 64-KB segment can be located
anywhere in the memory, but will start at
an address with zeros in the lowest 4-bits

31. 34BA
44EB
54EB
695E
31
CSR
DSR
ESR
SSR
Segment Registers
BIU
CODE (64k)
DATA (64K)
EXTRA (64K)
STACK (64K)
1MB
00000
34BA0
44B9F
44EB0
54EAF
54EB0
64EAF
695E0
795DF
Each segment register store the
upper 16 bit of the starting
address of the segments
MEMORY

32. Instruction Pointer (IP) Register
a 16-bit register
Holds 16-bit offset, of the next instruction
byte in the code segment
BIU uses IP and CS registers to generate
the 20-bit address of the instruction to be
fetched from memory

33. 33

34. 1
Data
Segment
3
4
Code
Segment
Extra
Segment
7
8
9
10
11
12
13
14
15
Stack
Segment
Memory
00000H
FFFFFH
1MB
Address
Range
348A H
4214 H
38AB4 H
CS
IP
Physical Address
Start of Code Segment
348A0H
Code Byte MOV AL, BL38AB4H
IP = 4214H
+
0

35. Segment and Address register combination
CS:IP
SS:SP SS:BP
DS:BX DS:SI
DS:DI (for other than string operations)
ES:DI (for string operations)
35

36. Summary of Registers & Pipeline of 8086 µP
AH AL
BH BL
CH CL
DH DL
36
SP
BP
SI
DI
FLAGS
D
E
C
O
D
E
R
ALU
AX
BX
CX
DX
EUEU
Timing
control
SP
BP
Default Assignment
BIUBIU
IP
CS DS ES SS
PIPELINE
(or)
QUEUE
C
O
D
E
O
U
T
C
O
D
E
I
N
IP BX
DI
SI
DI
Fetch &
store code
bytes in
PIPELINE

37. Stack Segment (SS) Register
Stack Pointer (SP) Register
Upper 16-bits of the starting address of
stack segment is stored in SS register
It is located in BIU
SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
It is located in EU

38. Other Pointer & Index Registers
Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data
word in one of the segments

39. Interrupts
The interrupt I/O is a process of data
transfer where by an external device or a
peripheral can inform the processor
that it is ready for communication and
it requests attention
 INTR is a maskable hardware interrupt
NMI is a non-maskable interrupt
Software interrupts

40. Instruction Set
 The entire group of instructions determines what
functions the microprocessor Can perform is
called instruction set.
 The instruction set is classified in three groups
according to the word size:
 1-byte instruction
 2-byte instruction
 3-byte instruction

41.  Instruction set of Intel 8086 processor consists of the
following instructions:
 Data moving instructions.
 Arithmetic - add, subtract, increment, decrement, convert
byte/word and compare.
 Logic - AND, OR, exclusive OR, shift/rotate and test.
 String manipulation - load, store, move, compare and
scan for byte/word.
 Control transfer - conditional, unconditional, call
subroutine and return from subroutine.
 Input/output instructions.
 Other - setting/clearing flag bits, stack operations,
software interrupts, etc.

42. Pin diagram 8086
Microprocessor

43. 8086 CPU
1
20
16
2
GND
VCC
AD15
17
18
19
AD14 TO
AD0
A16-A19
& S3-S6
GND
CLK
NMI
INTR
22
23
24
25
26
28
29
35
40
34
33
32
BHE/S7
MN/MX
RD
31
30
27
RQ/GTO(HOLD)
RQ/GT1(HLDA)
LOCK (WR)
READY
TEST
S2 (M/IO)
S1 (DT/R)
S0 (DEN)
QS0 (ALE)
QS1(INTA)
21RESET

44.  AD15-AD0: These are the time multiplexed memory
I/O address and data lines.
 A19/S6,A18/S5,A17/S4,A16/S3:These are the time
multiplexed address and status lines.
 During T1 these are the most significant address
lines for memory operations.
 During I/O operations, these lines are low.
 The S4 and S3 combination indicates which
segment register is presently being used for
memory accesses.
44
Function Of Pins of 8086

45. 45
Function Of Pins of 8086
BHE (Bus High Enable) /S7: The bus high
enable is used to indicate the transfer of
data over the higher order ( D15-D8 ) data
bus as shown in table.
 INTR-Interrupt Request: This is a triggered
input. If any interrupt request is pending, the
processor enters the interrupt acknowledge
cycle. This can be internally masked by
resulting the interrupt enable flag. This
signal is active high and internally
synchronized

46. RD: This signal on low indicates the
peripheral that the processor is performing
memory or I/O read operation.
READY: This is the acknowledgement from
the slow device or memory that they have
completed the data transfer.
46
Function Of Pins of 8086

47. TEST: This input is examined by a ‘WAIT’
instruction. If the TEST pin goes low,
execution will continue, else the processor
remains in an idle state
CLK- Clock Input: The clock input provides
the basic timing for processor operation and
bus control activity.
MN/MX: The logic level at this pin decides
whether the processor is to operate in either
minimum or maximum mode.
47
Function Of Pins of 8086

48. References
 [1] http://en.wikipedia.org/wiki/List_of_Intel_microprocessors
 [2] http://en.wikipedia.org/wiki/SSSE3
 [3] http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2748
 [4] http://en.wikipedia.org/wiki/Instruction_set
 [5] http://download.intel.com/technology/architecture/new_architecture_06.pdf
 [6] http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2748&p=3
 [7] http://searchsmb.techtarget.com/sDefinition/0,,sid44_gci212451,00.html
 [8] http://www.intel.com/cd/products/services/emea/tur/processors/287176.htm
 [9] http://techreport.com/reviews/2006q3/core2/index.x?pg=1

49. Any question
Thank you
END OF 8086 ARCHITECTURE