8086 microprocessor

Advanced
microprocessor
Unit-1
By: V. R. Gupta
lecturer
Department of Electronics & Telecommunication

Syllabus
Unit-1
1. Architecture of 8086,
2. Segmentation of memory
3. Physical address formation
4. Pin diagram of 8086
5. Minimum mode
6. Maximum mode
7. Addressing modes
8. Instruction set
9. Programming.
2Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Learning outcomes
After studying unit -1
1. You will learn architecture of 8086 and
functions of various pins.
2. Minimum & Maximum mode of 8086
3. Addressing modes & Instruction set of 8086
4. The most important is you will learn to write
assembly language program.

8086 microprocessor
4
1.Introduced in 1978.
2.It was first 16-bit µP.
3.Its clock speed is 4.77 MHz, 8 MHz and 10 MHz,
depending on the version.
4.Its data bus is 16-bit and address bus is 20-bit.
5.It had 29,000 transistors.
6. Could execute 2.5 million instructions per second.
7.It could access 1 MB of memory.
8.It had 22,000 instructions.
9.It had Multiply and Divide instructions.
10.It can be operated in minimum or maximum
mode.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Features
 It is a 16-bit μp.
 8086 has a 20 bit address bus can access up to 220
memory
locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Word size is 16 bits and double word size is 4 bytes.
 It has multiplexed address and data bus AD0- AD15 and
A16 – A19.
 It requires single phase clock with 33% duty cycle to
provide internal timing. 5Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

 8086 is designed to operate in two modes, Minimum
and Maximum.
 It can prefetches up to 6 instruction bytes from memory
and queues them in order to speed up instruction
execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has a separate
address.

ALU (16)ALU (16)
Decoding
circuit
Decoding
circuit
MEMORY ADDRESSS & DATA
BUS INTERFACE
Address conversion mechanism
( adder)
Address conversion mechanism
( adder)
IP
6
5
4
3
2
1
Timing and
control unit
Timing and
control unit
Clock and
control signals
Instruction
byte queue 6
byte
Flags(16)Flags(16)
B
U
S
I
N
T
E
R
F
A
C
E
U
N
I
T
E
X
E
C
U
T
I
O
N
U
N
I
T Register Bank
Address/Data bus
AD0-AD15
Address/ Status bus
A16/S3-A19/S6
Figure: Architecture of 8086

Architecture of 8086
 8086 has two blocks BIU and EU.
 The BIU(bus interface unit) handles all transactions of data and
addresses on the buses for EU(execution unit).
 The BIU performs all bus operations such as instruction
fetching, reading and writing operands for memory and
calculating the addresses of the memory operands.
 EU executes instructions from the instruction system byte
queue.

• Both units operate asynchronously to give the 8086
an overlapping instruction fetch and execution
mechanism which is called as Pipelining.
• This results in efficient use of the system bus and
system performance.
• BIU contains Instruction queue, Segment registers,
Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction decoder,
ALU, Pointer and Index register, Flag register.

EXECUTION UNIT – General Purpose Registers
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
11
8 bits 8 bits
16 bits
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
AX
BX
CX
DX
Pointer
Index
8 bits 8 bits
16 bits
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O
(Used to hold I/O address during I/O instructions. If the result is more than 16-bits,
the lower order 16-bits are stored in accumulator and higher order 16-bits are
stored in DX register) 12Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Pointer And Index Registers
 used to keep offset addresses.
SP: Stack pointer
Used with SS to access the stack segment
BP: Base Pointer
Primarily used to access data on the stack
Can be used to access data in other segments
SI: Source Index register
is required for some string operations
It points to memory locations in the data segment which is addressed
by the DS register. Thus, SI is associated with the DS in string operations.
DI: Destination Index register
is also required for some string operations.
it points to memory locations in the extra segment which is addressed
by the ES register. Thus, DI is associated with the ES in string operations.

EXECUTION UNIT – Flag Register
X X X X OF DF IF TF SF ZF X AF X PF X CF
14
 A flag is a flip flop which indicates some conditions produced by the
execution of an instruction or controls certain operations of the EU .
 In 8086 The EU contains
 a 16 bit flag register
 9 of the 16 are active flags and remaining 7 are undefined.
 6 flags indicates some conditions- status flags
 3 flags –control Flags
Carry
Over flow Direction
Interrupt
Trap
Sign
Zero
Auxiliary
Parity
X - Unused

EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=0

Flag Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging
feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
Overflow occurs when signed numbers are added or
subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

Execution unit – Flag Register
 Six flags are status indicators reflecting properties
of the last arithmetic or logical instruction.
 For example, if register AL = 7Fh and the
instruction ADD AL,1 is executed then the
following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed

BUS INTERFACE UNIT (BIU)BUS INTERFACE UNIT (BIU)
Contains
 6-byte Instruction Queue (Q)
 The Segment Registers (CS, DS, ES, SS).
 The Instruction Pointer (IP).
 The Address Summing block (Σ)

Segment registers
• In 8086/88 the processors have 4 segments
registers
• Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.

34BA
44EB
54EB
695E
20
Segment Registers
BIU
CODE (64k)
DATA (64K)
EXTRA (64K)
STACK (64K)
1MB
00000
34BA0
44B9F
44EB0
54EAF
54EB0
64EAF
695E0
795D
F
Each segment register store the
upper 16 bit of the starting
address of the segments
MEMORY
CSR
DSR
ESR
SSR

THE QUEUE (Q)
• The BIU uses a mechanism known as an
instruction stream queue to implement a
pipeline architecture.
• This queue permits pre-fetch of up to 6 bytes of
instruction code.
• Whenever the queue of the BIU is not full, it has
room for at least two more bytes and at the
same time the EU is not requesting it to read or
write operands from memory, the BIU is free to
look ahead in the program by pre-fetching the
next sequential instruction.

• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.
• After a byte is loaded at the input end of the queue, it
automatically shifts up through the FIFO to the
empty location nearest the output.
• The EU accesses the queue from the output end. It
reads one instruction byte after the other from the
output of the queue.
• The intervals of no bus activity, which may occur
between bus cycles are known as Idle state.

23
Opcode
Data
Opcode queue
From
memory
Repeat the same procedure
for successive contents of Q
Execute it with data bytes
decoded by the decoder
Take 2nd
byte from Q as
opcode, decode 2nd
byte
opcode
Execute it with data bytes
decoded by the decoder
Is it
Single
byte?
Take 2nd byte from Q as
opcode, decode 2nd byte
opcode
(Decode also decides the no. of
data bytes for the instructions)
Update
queue
Opcode 2nd
byte
yes
No
The Queue Operation

34BA
44EB
54EB
695E
24
CSR
DSR
ESR
SSR
Segment Registers
BIU
CODE (64k)
DATA (64K)
EXTRA (64K)
STACK (64K)
1MB
00000
34BA0
44B9F
44EB0
54EAF
54EB0
64EAF
695E0
795D
F
Each segment register store the
upper 16 bit of the starting
address of the segments
MEMORY

MEMORY SEGMENTATION

Segmented Memory
Code segment (64KB)
Data segment (64KB)
Extra segment (64KB)
Stack segment (64KB)
26
1MB
The memory in an 8086/88
based system is organized as
segmented memory.
The CPU 8086 is able to
address 1Mbyte of memory.
The Complete physically
available memory may be
divided into a number of logical
segments.
00000
FFFFF
Physical Memory

27Figure: Memory SegmentationTuesday, April 25, 2017 guptavikas.1051@rediffmail.com

 The size of each segment is 64 KB
 A segment is an area that begins at any location which
is divisible by 16.
 A segment may be located any where in the memory
 Each of these segments can be used for a specific
function.
 Code segment is used for storing the instructions.
 The stack segment is used as a stack and it is used to store
the return addresses.
 The data and extra segments are used for storing data byte.
* In the assembly language programming, more than one
data/ code/ stack segments can be defined. But only
one segment of each type can be accessed at any time.

 The 4 segments are Code, Data, Extra and Stack segments.
 A Segment is a 64kbyte block of memory.
 The 16 bit contents of the segment registers in the BIU actually
point to the starting location of a particular segment.
 Segments may be overlapped or non-overlapped
Advantages of Segmented memory Scheme
 Allows the memory capacity to be 1Mb although the actual addresses
to be handled are of 16 bit size.
 Allows the placing of code, data and stack portions of the same
program in different parts (segments) of the m/y, for data and code
protection.
 Permits a program and/or its data to be put into different areas of
memory each time program is executed, i.e. provision for relocation
may be done .
 The segment registers are used to allow the instruction, data or stack
portion of a program to be more than 64Kbytes long. The above can be
achieved by using more than one code, data or stack segments.

Physical Address Formation
 The instruction pointer register contains a 16-bit offset address of
instruction that is to be executed next.
 The IP always references the Code segment register (CS).
 The value contained in the instruction pointer is called as an offset
because this value must be added to the base address of the code
segment, which is available in the CS register to find the 20-bit
physical address.
 The value of the instruction pointer is incremented after executing
every instruction.
 To form a 20bit address of the next instruction, the 16 bit address
of the IP is added (by the address summing block) to the address
contained in the CS , which has been shifted four bits to the left.30Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

31
segment address (base address) 0000
Effective address (offset address)
Adder
20 bit Physical Address
1) Segment
address is 4-bit
left shifted
2) Add effective
address to the 4-bit left
shifted segment
address
3) 20-bit physical
address
Flowchart for physical address formation

• The following examples shows the CS:IP
scheme of address formation:
32
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR
four binary digits left
3 4 B A 0 ( C S ) +
8 A B 4 ( I P )
3 D 6 5 4 (next address)
34BA 8AB4CS IP
34BA0
3D645
44B9F
Code segment
8AB4 (offset)

Example For Address Calculation (segment:
offset)
• If the data segment starts at location 1000h and a
data reference contains the address 29h where is
the actual data?
33
Physical Address
Offset address
Segment Address
0000 0000 0010 1001
0000
0001 0000 0000 0010 1001
0001 0000 0000 0000

Segment and Address register
combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)

Pin Diagram Of 8086

Pin Diagram of 8086
36
 It is available as 40-pin Dual-
Inline-Package (DIP).
 The 8086 signals can be
categorized in three groups
1.Common pins
2.Minimum mode pins
3.Maximum mode pins

37
AD0 – AD15
Pin 16-2, 39 (Bi-directional)
These lines are multiplexed bi-
directional address/data bus.
During T 1 , they carry lower
order 16-bit address.
In the remaining clock cycles,
they carry 16-bit data.
AD 0 -AD 7 carry lower order
byte of data.
AD 8 -AD 15 carry higher order
byte of data.

38
A19/S6, A18/S5, A17/S4,A16/S3
Pin 35-38 (Unidirectional)
These lines are multiplexed
unidirectional address and status
bus.
 During T1 , they carry higher order
4-bit address.
In the remaining clock
cycles, they carry status signals.

39
BHE / S7
BHE stands for Bus High Enable.
BHE signal is used to indicate the
transfer of data over higher order
data bus (D 8 – D 15 ).
It is multiplexed with status pin S7 .
The status information is available
during T2, T3 and T4.

40
•RD [Read]: This signal on low indicates the peripheral that the processor is
performing memory or I/O read operation. RD is active low and
shows the state for T2, T3, Tw of any read cycle. The signal remains
tristated during the hold acknowledge.
.
•READY: This is the acknowledgement from the slow device or memory that
they have completed the data transfer. The signal made available by
the devices is synchronized by the 8284A clock generator to provide
ready input to the 8086. the signal is active high.
•INTR-Interrupt Request: This is a triggered input. This is sampled during the
last clock cycles of each instruction to determine the availability of
the request. If any interrupt request is pending, the processor enters
the interrupt acknowledge cycle.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

41
•TEST: This input is examined by a ‘WAIT’ instruction. If the
TEST pin goes low, execution will continue, else the processor
remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock.
•CLK- Clock Input: The clock input provides the basic timing for
processor operation and bus control activity. Its an asymmetric
square wave with 33% duty cycle .
•MN/MX: The logic level at this pin decides whether the processor
is to operate in either minimum or maximum mode.

42
Pin Functions For The Minimum Mode
M / IO – Memory / IO: This is a status line .
1. When it is low, it indicates the CPU is having an
I/O operation
2. when it is high, it indicates that the CPU is having
a memory operation.
3. becomes active high in the previous T4 and
remains active till final T4 the current cycle.
4. It is tristated during local bus “hold acknowledge “.

43
INTA : Interrupt Acknowledge: This signal is used
as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has
accepted the interrupt.
•ALE – Address Latch Enable: This output signal
indicates the availability of the valid address on
the address/data lines, and is connected to
latch enable input of latches. This signal is
active high and is never tristated.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

44
•DT/R – Data Transmit/Receive: This output is used to decide the direction of
data flow through the transreceivers (bidirectional buffers). When the
processor sends out data, this signal is high and when the processor is
receiving data, this signal is low.
•DEN – Data Enable: This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers ( bidirectional
buffers ) to separate the data from the multiplexed address/data signal.
It is active from the middle of T2 until the middle of T4. This is tristated
during ‘ hold acknowledge’ cycle.
•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access.

45
The following pin function are applicable for maximum mode
operation of 8086:-
•S2, S1, S0 – Status Lines: These are the status lines which
reflect the type of operation, being carried out by the processor.
These become activity during T4 of the previous cycle and active
during T1 and T2 of the current bus cycles.

46
QS1and QS0
Pin 24 and 25 (Output)
These pins provide the status of instruction
queue.
QS1 QS0 Status
0 0 No operation
0 1 1st
byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue

47
This signal indicates that other processors
should not ask CPU to relinquish the system
bus.
When it goes low, all interrupts are masked
and HOLD request is not granted.
This pin is activated by using LOCK prefix on
any instruction.
LOCK
Pin 29 (Output)

48
RQ/GT1 and RQ/GT0
Pin 30 and 31 (Bi-directional)
These are Request/Grant pins.
Other processors request the CPU through
these lines to release the system bus.
After receiving the request, CPU sends
acknowledge signal on the same lines.
RQ/GT 0 has higher priority than RQ/GT 1 .

49
Minimum ModeMinimum Mode
Of 8086Of 8086

51
In this mode the microprocessor 8086 is
operated in minimum mode by strapping its
MN/MX pin to logic 1.
In this mode, all the control signals are given
out by the microprocessor chip itself. There is
a single microprocessor in the minimum mode.
The remaining components in the system are
latches, transreceivers, clock generator, memory
and I/O devices.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

52
 Latches are generally buffered output D-type flip-
flops like 74LS373 or 8282. They are used for
separating the valid address from the multiplexed
address/data signals and are controlled by the ALE
signal generated by 8086.
Transreceivers are the bidirectional buffers,
used to separate the valid data from the time
multiplexed address/data signals.
They are controlled by DEN and DT/R. The DEN
signal indicates the direction of data, i.e. from or to
the processor. The system contains memory for the
monitor and users program storage.

53
Read Cycle Timing Diagram For Minimum Mode

54
 The read cycle begins in T1 with the assertion of
address latch enable (ALE) signal and also M / IO
signal.
 During the negative going edge of this signal, the
valid address is latched on the local bus.
 The BHE and A0 signals address low, high or
both bytes.
 From T1 to T4 , the M/IO signal indicates a
memory or I/O operation.
 At T2, the address is removed from the local bus
and is sent to the output.
 The bus is then tristated. The read (RD) control
signal is also activated in T2.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

55
 The read (RD) signal causes the address device to
enable goes low, the valid data is available on the
data bus.
 The addressed device will drive the READY line high.
 When the processor returns the read signal to high
level, the addressed device will again tristate its bus
drivers.
 The read cycle begins in T1 with the assertion of
address latch enable (ALE) signal and also M / IO
signal.

56
Write Cycle Timing Diagram For Minimum Mode

57
A write cycle also begins with the assertion of
ALE and the emission of the address.
The M/IO signal is again asserted to indicate a
memory or I/O operation.
 In T2, after sending the address in T1, the
processor sends the data to be written to the
addressed location.

58
The data remains on the bus until middle of T4
state. The WR becomes active at the beginning of
T2 (unlike RD is somewhat delayed in T2 to
provide time for floating).
The BHE and A0 signals are used to select the
proper byte or bytes of memory or I/O word to be
read or write. The M/IO, RD and WR signals
indicate the type of data transfer as specified in
tableTuesday, April 25, 2017 guptavikas.1051@rediffmail.com

59
Maximum mode of 8086Maximum mode of 8086

61
Addressing modesAddressing modes
of 8086of 8086

62
Definition: An instruction acts on any number of operands.
The way an instruction accesses its operands is called its
Addressing modes.
Operands may be of three types :
Implicit
Explicit
Both Implicit and Explicit.
Addressing Modes of 8086

Types of Addressing Modes
• Immediate addressing mode
• Direct addressing mode
• Register addressing mode
• Register indirect
• Indexed
• Register relative
• Based indexed
• Relative based indexed
• Intra segment direct mode
• Intra segment indirect mode
• Inter segment direct mode
• Inter segment indirect mode

Immediate addressing mode
• Immediate data is a part of the instruction
• Immediate data appears in the form of
successive byte or bytes
• E.g.
MOV AX, 0005H
In this instruction 0005H is the immediate
data.
The immediate data may be 8 bit or 16 bit in
size. 64Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Direct addressing mode
• In this addressing mode 16 bit memory address
(offset ) is directly specified in the instruction as a
part of it.
• E.g. MOV AX, [5000H]
• In this instruction [5000H] denotes the effective
address (offset) of the operand. The data resides
in a memory location in the data segment, the 20
bit physical address is generated as
10H*DS+5000H

Register addressing mode
• The data is stored in the register
• The data is referred by using that particular
register in the instruction
• All the registers except IP may be used in this
mode.
• E.g. MOV BX, AX
• In this instruction the data present in AX
register is transferred to the BX register

Register indirect
• In this addressing mode , the offset address of the
data is in either BX or SI or DI register
• The default segment is either Ds or ES.
• E.g. MOV AX, [BX]
• Here, data is present in a memory location in data
segment whose offset address is in BX
• The effective address of the data is given as
10H*DS+ BX

Indexed addressing mode
• In this addressing mode , the offset address of the
operand is stored in one of the index register {SI or
DI}
• DS is the default segment for index register SI & DI
• E.g. MOV AX, [SI]
• Here, data is present in a memory location in data
segment whose offset address is in SI
• The effective address of the data is given as 10H*DS+
SI

Register relative addressing mode
• The data is available at an address
formed by adding an 8 bit or 16 bit
displacement with the content of any one
of the registers BX, BP, SI & DI in the
default segment
• E.g. MOV AX, 50H[BX]
• Here the physical address is given by:
• 10H*DS+ 50H+BX 69Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Based Indexed Addressing Mode
• In this addressing mode 20 bit physical address is
formed by adding content of a base register (BX or
BP) to the content of index register (SI or DI) .
• The default segment register may be Ds or ES.
• E.g. MOV AX, [BX][SI]
• Here BX is the base register
SI is the index register
The physical address is computed as
10H*DS+BX+SI

Relative based indexed
 The physical address is formed by adding an 8
or 16 bit displacement with the sum of
contents of any one of the base registers (BX
or BP) & any one of the index register in the
default segment.
 E.g. MOV AX, 50H[BX][SI]
 Here 50H is the displacement, BX is abase
register & SI is an index register.
 The physical address of the operand is
computed as
 10H*DS+ 50H+BX+SI

72
Instruction set ofInstruction set of
8086 Microprocessor8086 Microprocessor

Classification of Instruction Set
The instruction set of 8086 microprocessor is
classified as follows:
•Data Transfer Instructions
•Arithmetic Instructions
•Logical instruction
•Flag manipulation instructions
•Shift & Rotate Instructions
•Branch Instructions
•Loop instructions
• String Instructions
•Processor Control Instructions (machine control)

Data Transfer InstructionsData Transfer Instructions

75
Mnemonic Meaning Format Operation Flags affected
MOV Move MOV D,S (S)  (D) None
MOVMOV
Destination Source
Memory Accumulator
Accumulator Memory
Register Register
Register Memory
Memory Register
Register Immediate
Memory Immediate
Seg reg Reg 16
Seg reg Mem 16
Reg 16 Seg reg
Memory Seg reg
NO MOV
Memory
Immediate
Segment Register
Memory
Segment Register
Segment Register
EX: MOV AL, BL

XCHGXCHG
XCHG Exchange XCHG D,S (S) (D) None
Destination Source
Accumulator Reg 16
Memory Register
Register Register
Register Memory
76
Example: XCHG AX, BX
NO XCHG
Memory
SEG Rrgisters

Data Transfer Instructions – LEA, LDS, LES
Mnemo
nic
Meaning Format Operation Flags
affected
LEA Load
Effective
Address
LEA Reg16,EA EA  (Reg16) None
LDS Load
Register
And DS
LDS Reg16,MEM32 (MEM32)  (Reg16)
(Mem32+2)  (DS)
None
LES Load
Register
and ES
LES Reg16,MEM32 (MEM32)  (Reg16)
(Mem32+2)  (DS)
None
77
LEA SI DATA (or) MOV SI Offset DATA

The XLAT InstructionThe XLAT Instruction
Mnemonic Meaning Format Operation Flags
XLAT Translate XLAT ((AL)+(BX)+(DS)0)  (AL) None
78
Example:
Assume (DS) = 0300H, (BX)=0100H, and (AL)=0DH
XLAT replaces contents of AL by contents of memory
location with
PA=(DS)0 +(BX) +(AL)
= 03000H + 0100H + 0DH = 0310DH
Thus
(0310DH)  (AL)

Arithmetic Instructions: ADD, ADC, INC, AAA, DAAArithmetic Instructions: ADD, ADC, INC, AAA, DAA
affected
ADD Addition ADD D,S (S)+(D)  (D)
carry  (CF)
AF CF OF
PF SF ZF
ADC Add with
carry
ADC D,S (S)+(D)+(CF)  (D)
Carry  (CF)
AF CF OF
PF SF ZF
INC Increment by
one
INC D
(D)+1 (D)
AF OF PF
SF ZF
AAA ASCII adjust
for addition
AAA
(AX) ubcd (AL)hex
AF,CF
[OF PF SF
ZF are
undefined]
DAA Decimal
adjust for
addition
DAA Adjust AL for decimal
Packed BCD
AF CF OF
PF SF ZF

ASCII & BCD Numbers
• ASCII coded no are binary codes for numeric characters. ASCII 30h to
39h are the codes for the characters 0 to 9.
• BCD no are decimal equivalent binary no that vary from 0000b to 1001b,
or 0 to 9 decimal.
• Packed BCD & Unpacked BCD
• No represented as one BCD digit per byte are called UBCD
• For the application in which We are going to perform mathematical
operations on the BCD no we usually combine two BCD digits in a
single byte this form is called PBCD

81
EXAMPLE
ASCII 5 0011 0101 = 35H
ASCII 9 0011 1001 = 39H
UBCD 5 0000 0101 = 05H
UBCD 9 0000 1001 = 09H
UBCD 5 0101 0000 = 50H
MOVED TO UPPER NIBBLE
PBCD 59 0101 1001 = 59H

AAA {ASCII adjust after
addition}
82
Invalid ASCII no . In AL
register
Valid unpacked BCD in
AX register
Mnemonic Size Format Operation Flags
AAA W AAA (AX) ubcd (AL)hex AF,CF
[OF PF SF ZF are
undefined]
• AAA examines the lower 4 bits of AL to check whether it contains a valid
BCD no in the range 0 to 9.
• If it is between 0 to 9 and AF = 0 , AAA will set 4 higher order bits of AL to
zero.
• AH must be cleared before addition .
• If the lower digit of AL is between 0 to 9 & AF is set , 06 is added to AL; the
upper 4 bits of AL are cleared and AH is incremented by 1;
• If the value in the lower nibble of AL is greater than 09 then the AL is
incremented by 06 ; AH is incremented by 1; AF & CF are set to 1 & the 4
MSB of AL are set to zero.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Examples:
Ex.1 ADD AX,BX
ADC AX,CX
Ex.2 INC BX
INC WORD PTR [BX]
Ex.3 ASCII CODE 0-9 = 30-39h
MOV AX,38H ; (ASCII code for number 8)
ADD AL,39H ; (ASCII code for number 9)
AL71h
AAA ; used for addition AH01;
AL07
ADD AX,3030H ; answer to ASCII 0107
AX3137
83
Ex.4 AL contains 25 (packed BCD)
BL contains 56 (packed BCD)
ADD AL, BL
DAA
25
+ 56
--------
7B 81

• AL
• AL
• AL
• AH
84
5 7
0 7
5 A
0 0
Before to AAA
After AAA execution
Previous to AAA
A > 9, hence A+6 = 1010+0110
= 10000
= 10H
•AX Previous to AAA
•AX After execution to AAA
005A
0100

DAA {Decimal adjust after addition}
85
Hex . no . In AL register Valid packed BCD in AL
register
DAA B DAA
(AL) Pbcd (AL) hex
AF,CF,
PF,SF,ZF
•DAA is used to convert the result of the addition of two packed BCD
nos. & adjusts the answer to packed BCD. The result has to be only in
AL
•If the lower nibble is greater than 9 or AF is set , it will add 06h to the
lower nibble of AL.
•If the upper nibble of AL is greater than 9 or after addition CF is set
then it will add 60h to upper nibble of AL.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Examples:
86
53
+ 29
--------
7CH
ADD AL, BL; AL [ AL] +
[ CL]
AL 9CH
DAA ; AL 02 & CF
= 1
73
+ 29
--------
9CH
+06
------------
A2
+60
----------------
AL  02
CF 1
ADD AL, BL; AL [ AL] +[ CL]
AL 7CH
DAA ; AL 7C + 06 (as C > 9)
AL 82

Arithmetic Instructions – SUB, SBB, DEC, AAS, DAS,
NEG
affected
SUB Subtract SUB D,S (D) - (S)  (D)
Borrow  (CF)
All
SBB Subtract
with
borrow
SBB D,S (D) - (S) - (CF)  (D) All
DEC Decrement
by one
DEC D (D) - 1  (D) All but CF
NEG Negate NEG D 2’s complement of specified
destination
(D)  0 - (D)
All
DAS Decimal
adjust for
subtraction
DAS Convert the result in AL to
packed decimal format
All
AAS ASCII
adjust for
subtraction
AAS (AL) difference
(AH) dec by 1 if borrow
CY,AC

DAS{Decimal adjust after subtraction}
88
Hex . no . In AL register Valid packed BCD in AL
register
DAS B DAA (AL) Pbcd (AL)hex AF,CF,
PF,SF,ZF
•DAS converts the result of subtraction of two packed BCD no. to a
valid BCD no. The result has to be only in AL.
•If the lower nibble of AL is greater than 9 or AF is set , it will subtract
06h from the lower nibble of AL.
•If the upper nibble of AL is greater than 9 or after subtraction CF is
set then it will subtracts 60h from upper nibble of AL.

Examples:
89
SUB AL, BL; AL [ AL] -[ CL]
AL 2FH
DAS ; AL 2F - 06 (as F > 9)
AL 29
75
- 46
--------
2FH
- 06
-----------
29
SUB AL, BL; AL [ AL] -[ CL]
AL D7H CF=1
DAS ; AL 77 & CF = 1
38
- 61
---------------------
CF=1 D7H
- 60
--------------------------
77
CF 1

AAS {ASCII adjust for subtraction}
90
Invalid ASCII no . In AL
register
Valid unpacked BCD in
AX register
AAS W AAA (AX) ubcd (AL)hex
AF,CF
[OF PF SF
ZF are
undefined]
•AAS examines the lower 4 bits of AL
•If it is greater than 9 or AF = 1 , AL is
decremented by 6 & AH is decremented by 1. the
CF & AF are set to 1.
•Otherwise CF & AF are set to zero , the result
needs no correction.

Examples: DAS
MOV BL, 28H
MOV AL, 83H
SUB AL,BL ; AL=5BH
DAS ; adjust as AL=55H
MOV AL, 38H
MOV BL, 39H;
SUB AL,BL; AL = FF
AAS ; AL = 09
(Borrow one from AH )
OR AL,30H ; AL=39
91
28
- 83
------------
5B before DAS
- 06
-----------------
55 after DAS
28
5
B
55
AL BL
83
38
- 39
------------
FF before
DAS
- 06
-----------------
09 after DAS

Multiplication and Division
92

93
Multiplication
(MUL or IMUL)
Multiplicand Operand
(Multiplier)
Result
Byte*Byte AL Register or memory AX
Word*Word AX Register or memory DX :AX
Dword*Dword EAX Register or memory EAX :EDX
Division
(DIV or IDIV)
Dividend Operand
(Divisor)
Quotient:
Remainder
Word/Byte AX Register or Memory AL : AH
Dword/Word DX:AX Register or Memory AX : DX
Qword/Dword EDX: EAX Register or Memory EAX : EDX
Multiplication and Division

Multiplication and Division Examples
Ex1: Assume that each instruction starts from these values:
AL = 85H, BL = 35H, AH = 0H
1. MUL BL → AL . BL = 85H * 35H = 1B89H → AX = 1B89H
DIV BL → = = 02 (85-02*35=1B)
1B 89
1B 02
94
0085
35
H
H
AH AL
BL
AX
AH AL

95
Mnemonic Meaning Format Operation Flags Affected
AND
OR
XOR
NOT
Logical AND
Logical Inclusive
OR
Logical Exclusive
OR
LOGICAL NOT
AND D,S
OR D,S
XOR D,S
NOT D
(S) · (D) → (D)
(S)+(D) → (D)
(S) (D)→(D)
_
(D) → (D)
OF, SF, ZF, PF,
CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
None
+
Logical Instructions
Destination Source
Register
Register
Memory
Register
Memory
Accumulator
Register
Memory
Register
Immediate
Immediate
Immediate
Destination
Register
Memory

96
CWB Convert byte
to word
CWB W  B None
CWD Convert
word to
double word
CWD D  W None
CWB & CWD INSTRUCTION

LOGICAL Instructions
• AND
– Uses any addressing mode except memory-to-
memory and segment registers
– Especially used in clearing certain bits
(masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
– Examples: AND BL, 0FH
AND AL, [345H]
• OR
– Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)

• XOR
– Used in Inverting bits
xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’
-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit
5 of register CL:
AND CL, OFCH ; 1111 1100B
OR CL, 0C0H ; 1100 0000B
XOR CL, 020H ; 0010 0000B
98

Shift and Rotate Instructions
 SHL/SAL: shift logical left/shift
arithmetic left
 SHR: shift logical right
 SAR: shift arithmetic right
 ROL: rotate left
 ROR: rotate right
 RCL: rotate left through carry
 RCR: rotate right through carry

Logical vs Arithmetic Shifts
A logical shift fills the newly created bit position with zero:
100
• An arithmetic shift fills the newly created bit
position with a copy of the number’s sign
bit:

101
Mnemo
-nic
Affected
SAL/SHL
SHR
SAR
Shift
arithmetic
Left/shift
Logical left
Shift
logical
right
Shift
arithmetic
right
SAL/SHL D, Count
SHR D, Count
SAR D, Count
Shift the (D) left by the
number of bit positions
equal to count and fill the
vacated bits positions on
the right with zeros
Shift the (D) right by the
the left with zeros
Shift the (D) right by the
the left with the original
most significant bit
CF,PF,SF,ZF
AF undefined
OF undefined
if count ≠1
CF,PF,SF,ZF
AF undefined
OF undefined
if count ≠1
CF,PF,SF,ZF
AF undefined
OF undefined
if count ≠1
Shift Instructions

102
Allowed operands
Destination Count
Register
Register
Memory
Memory
1
CL
1
CL

SHL Instruction
The SHL (shift left) instruction performs a logical left shift
on the destination operand, filling the lowest bit with 0.
104
• Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL

Fast Multiplication
105
mov dl,5
shl dl,1
Shifting left 1 bit multiplies a number by 2
mov dl,5
shl dl,2 ; DL = 20
Shifting left n bits multiplies the operand by
2n
For example, 5 * 22
= 20

106
Ex.
; Multiply AX by 10
SHL AX, 1
MOV BX, AX
MOV CL,2
SHL AX,CL
ADD AX, BX

SHR Instruction
The SHR (shift right) instruction performs a
logical right shift on the destination operand.
The highest bit position is filled with a zero.
107
MOV DL,80
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
Shifting right n bits divides the operand by 2n

SAR Instruction
• SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.
108
An arithmetic shift preserves the number's sign.
MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10

Rotate InstructionsRotate Instructions
Mnem
-onic
Meaning Format Operation Flags Affected
ROL Rotate
Left
ROL D, Count Rotate the (D) left by the
number of bit positions equal
to Count. Each bit shifted out
from the left most bit goes
back into the rightmost bit
position.
CF
OF undefined
if count ≠ 1
ROR Rotate
Right
ROR D,Count Rotate the (D) right by the
number of bit positions equal
to Count. Each bit shifted out
from the rightmost bit goes
back into the leftmost bit
position.
CF
OF undefined
if count ≠ 1
RCL Rotate
Left
through
Carry
RCL D,Count Same as ROL except carry is
attached to (D) for rotation.
CF
OF undefined
if count ≠ 1
RCR Rotate
right
through
RCR D,Count Same as ROR except carry is
attached to (D) for rotation.
CF
OF undefined
if count ≠ 1

ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the
Carry flag and into the lowest bit
No bits are lost
110
MOV Al,11110000b
ROL Al,1 ; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4 ; DL = F3h

ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag
and into the highest bit
No bits are lost
111
MOV AL,11110000b
ROR AL,1 ; AL = 01111000b
MOV DL,3Fh
ROR DL,4 ; DL = F3h

RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
112
CF
CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b

RCR Instruction
• RCR (rotate carry right) shifts each bit to the right
• Copies the Carry flag to the most significant bit
• Copies the least significant bit to the Carry flag
113
STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0

114
Destination Count
Register
Register
Memory
Memory
1
CL
1
CL
Rotate Instructions

Flag control instructions
MNEM-
ONIC
MEANING OPERATION Flags
Affected
CLC Clear Carry Flag (CF)  0 CF
STC Set Carry Flag (CF)  1 CF
CMC Complement
Carry Flag
(CF)  (CF)l CF
CLD Clear Direction
Flag
(DF)  0
SI & DI will be auto incremented while
string instructions are executed.
DF
STD Set Direction
Flag
(DF)  1
SI & DI will be auto decremented
while string instructions are executed.
DF
CLI Clear Interrupt
Flag
(IF)  0 IF
STI Set Interrupt
Flag
(IF)  1 IF

Compare Instruction, CMP
Mnemo
nic
Affected
CMP Compare CMP D,S (D) – (S) is used in
setting or resetting the
flags
CF, AF, OF,
PF, SF, ZF
116
(D) = (S) ; ZF=0
(D) > (S) ; ZF=0, CF=0
(D) < (S) ; ZF=0, CF=1
Allowed Operands
Destination Source
RegisterRegister
RegisterMemory
Memory Register
RegisterImmediate
Memory Immediate
Accumulator Immediate

String?
• An array of similar data bytes or
words located in sequential
memory location
• Supported String Operations
– Copy (move, load)
– Search (scan)
– Store
– Compare

String Instruction Basics
Source DS:SI, Destination ES:DI
You must ensure DS and ES are initialized for
source & destination string respectively.
You must ensure SI and DI are offsets of DS and
ES respectively
Direction Flag (0 = Up, 1 = Down)
CLD – clear direction flag {Increment addresses }
STD – set direction flag {Decrement addresses }

String InstructionsString Instructions
Prefix Used with Meaning
REP
REPE/REPZ
REPNE/REP
NZ
MOVS
STOS
CMPS
SCAS
CMPS
SCAS
Repeat while not end of string
CX ≠ 0
and strings are equal. CX ≠ 0
and ZF = 1
and strings are not equal. CX ≠
0 and ZF = 0
119
Instruction prefixes

InstructionsInstructions
Mnemo-
Nic
meaning format Operation Flags
effect
-ed
MOVS Move string
DS:SI
ES:DI
MOVSB/
MOVSW
((ES)0+(DI))  ((DS)0+(SI))
(SI)  (SI) ± 1 or 2
(DI)  (DI) ± 1 or 2
none
CMPS Compare
string
DS:SI
ES:DI
CMPSB/
CMPSW
Set flags as per
((DS)0+(SI)) - ((ES)0+(DI))
(SI)  (SI) ± 1 or 2
(DI)  (DI) ± 1 or 2
All
status
flags

Mnemo-
Nic
meaning format Operation
SCAS Scan string
AX – ES:DI
SCASB/
SCASW
Set flags as per
(AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2
LODS Load string
DS:SI  AX
LODSB/
LODSW
(AL or AX)  ((DS)0+(SI))
(SI)  (SI) ± 1 or 2
STOS Store string
ES:DI  AX
STOSB/
STOSW
((ES)0+(DI))  (AL or A) ± 1 or 2
(DI)  (DI) ± 1 or 2

122
11
22
33
55
66
77
88
99
11SEG. ADD
OFFSET
ADD.
SEG. ADD
OFFSET
ADD
*10H *10H
+
+
20 BIT PHYSICAL
ADDRESS
20 BIT PHYSICAL
ADDRESS
DS
ES
SI DI
Source
string
Destination
stringREP MOVSB
If DF is reset
SI  SI+1
DI  DI+1
CX  CX -1
repeat if count is
not zero

123
11
22
33
55
66
77
88
99
11
22
SEG. ADD
OFFSET
ADD.
SEG. ADD
OFFSET
ADD
*10H *10H
+
+
20 BIT PHYSICAL
ADDRESS
20 BIT PHYSICAL
ADDRESS
DS
ES
SI DI
Source
string
Destination
stringREP MOVSW
If DF is reset
SI  SI+2
DI  DI+2
CX  CX -1
repeat if count is
not zero

124
Branch group of instructionsBranch group of instructions
Branch instructions provide lot of convenience to the programmer to
perform operations selectively, repetitively etc.
Branch group of instructions
Conditional
jumps
Unconditi
onal jump
Iteration
instructions
CALL
instructions
Return
instructions

SUBROUTINE & SUBROUTINE HANDILING
INSTRUCTIONS
125
Call subroutine A
Next instruction
Call subroutine A
Next instruction
Main program
Subroutine A
First Instruction
Return

 A subroutine is a special segment of program that can be
called for execution from any point in a program.
 An assembly language subroutine is also referred to as a
“procedure”.
 Whenever we need the subroutine, a single instruction is
inserted in to the main body of the program to call
subroutine.
 To branch a subroutine the value in the IP or CS and IP
must be modified.

127
After execution, we want to return the control to the
instruction that immediately follows the one called the
subroutine i.e., the original value of IP or CS and IP must
be preserved.
Execution of the instruction causes the contents of IP to
be saved on the stack. (this time (SP)  (SP) -2 )
A new 16-bit (near-proc, mem16, reg16 i.e., Intra
Segment) value which is specified by the instructions
operand is loaded into IP.
Examples: CALL 1234H
CALL BX
CALL [BX]

• Inter Segment
– At starting CS and IP placed in a stack.
– New values are loaded in to CS and IP given by
the operand.
– After execution original CS, IP values placed as it
is.
Far-proc
Memptr32
128
These two words (32 bits) are loaded directly into IP and
CS with execution at CALL instruction.
First 16  IP
Next 16  CS

Mnem
onic
Affected
CALL Subroutine
call
CALL operand Execution continues from the
address of the subroutine
specified by the operand.
Information required to
return back to the main
program such as IP and CS
are saved on the stack.
none
129
OperandOperand
Near-proc
Far – proc
Memptr 16
Regptr 16
Memptr 32Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

RETURNRETURN
• Every subroutine must end by executing an instruction that returns control
to the main program. This is the return (RET) instruction.
• By execution the value of IP or IP and CS that were saved in the stack to
be returned back to their corresponding regs. (this time (SP)  (SP)+2 )
Mnem
onic
Affected
RET Return RET Return to the main program
by restoring IP (and CS for
far-proc). If operands is
present, it is added to the
contents of SP.
None
130
OperandOperand
NoneTuesday, April 25, 2017 guptavikas.1051@rediffmail.com

Loop InstructionsLoop Instructions
• These instructions are used to repeat a set of instructions several times.
• Format: LOOP Short-Label
• Operation: (CX)  (CX)-1
• Jump is initialized to location defined by short label if CX≠0. otherwise, execute
next sequential instruction.
• Instruction LOOP works w.r.t contents of CX. CX must be preloaded with a
count that represents the number of times the loop is to be repeat.
• Whenever the loop is executed, contents at CX are first decremented then
checked to determine if they are equal to zero.
• If CX=0, loop is complete and the instruction following loop is executed.
• If CX ≠ 0, content return to the instruction at the label specified in the loop
instruction.

132
General format : LOOP r8 ; r8 is 8-bit signed value.
It is a 2 byte instruction.
Used for backward jump only.
Maximum distance for backward jump is only 128 bytes.
LOOP AGAIN is almost same as: DEC CX
JNZ AGAIN
LOOP instruction does not affect any flags.
LOOP Instruction contd.LOOP Instruction contd.

Mnemonic meaning format Operation
LOOP Loop Loop short-label (CX)  (CX) – 1
Jump to location given by
short-label if CX ≠ 0
LOOPE/
LOOPZ
Loop while
equal/ loop
while zero
LOOPE/LOOPZ
short-label
(CX)  (CX) – 1
short-label if CX ≠ 0 and
ZF=1
LOOPNE/
LOOPNZ
Loop while
not equal/
loop while
not zero
LOOPNE/LOOPNZ
short-label
(CX)  (CX) – 1
short-label if CX ≠ 0 and
ZF=0

134
Jumps Based on a single flagJumps Based on a single flag
JZ ;Jump if zero flag set to 1 (Jump if result is zero)
JNZ ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)
JS ;Jump if Sign flag set to 1 (result is negative)
JNS ;Jump if Not Sign (result is positive)
JC ;Jump if Carry flag set to 1
JNC ;Jump if No Carry
JP ;Jump if Parity flag set to 1 (Parity is even)
JNP ;Jump if No Parity (Parity is odd)
JO ;Jump if Overflow flag set to 1 (result is wrong)
JNO ;Jump if No Overflow (result is correct)
There is no jump
based on AC flag

135
JZ ; JE (Jump if Equal) also means same.
JNZ ; JNE (Jump if Not Equal) also means same.
JC ;JB (Jump if below) and JNAE (Jump if Not
Above or Equal) also mean same.
JNC ;JAE (Jump if Above or Equal) and JNB (Jump
if Not Above) also mean same.
JZ, JNZ, JC and JNC used after arithmetic operation
JE, JNE, JB, JNAE, JAE and JNB are used after a
compare operation.
JP ; JPE (Jump if Parity Even) also means same.
JNP ; JPO (Jump if Parity Odd) also means same.

Machine control instructionsMachine control instructions
HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 will enter a halt state. The only way to get
the processor out of the halt state are with an interrupt signal on the INTR
pin or an interrupt signal on NMI pin or a reset signal on the RESET input.
NOP instruction
This instruction simply takes up three clock cycles and does no
processing.
It increments the IP to point to the next location. After this, it will execute the
next instruction. This instruction is normally used to provide delays in
between instructions.

137
ESC instruction
 This instruction is used to pass instructions to a
coprocessor such as 8087 math coprocessor which shares
the add. & data bus with an 8086.
 Instructions for the coprocessor are represented by 6 bit
code embedded in the escape instruction.
 when 8086 fetches instruction bytes, co-processor also
picks up these bytes and puts in its queue.
 The co-processor will treat normal 8086 instructions as
NOP.
 Floating point instructions are executed by 8087 and during
this 8086 will be in WAIT.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

LOCK instruction {assert BUS LOCK SIGNAL}
• This is a prefix to an instruction. This prefix makes sure that during execution of the
instruction, control of system bus is not taken by other microprocessor.
• In multiprocessor systems, individual microprocessors are connected together by a
system bus.
• This is to share the common resources. Each processor will take control of this bus
only when it needs to use common resource.
• The lock prefix will ensure that in the middle of an instruction, system bus is not taken
by other processors. This is achieved by hardware signal ‘LOCK’ available on one of
the CPU pin.
• This signal will be made active during this instruction and it is used by the bus control
logic to prevent others from taking the bus.
• Once this instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.

139
WAIT instruction
 This instruction takes 8086 to an idle condition.
 The CPU will not do any processing during this.
It will continue to be in idle state until TEST pin of 8086
becomes low or an interrupt signal is received on INTR or
NMI.
On valid interrupt, ISR is executed and processor enters
the idle state again.
This instruction is used to synchronize the 8086 with
external hardware such a 8087 math coprocessor

148
SUMMERY
In this unit you have studied the architecture of 8086, function of
pins of 8086 processor. In the architecture you have seen that it is
divided into 2 parts EU & BIU.
The memory of 8086 processor is segmented into 16 segments.
Each of 64 Kbyte.
You have also studied the minimum & maximum mode of 8086
processor.
The various addressing modes of 8086 processor with example is
studied.
At last you have studied the instruction set of the 8086 processor
and some assembly language programming is done.Tuesday, April 25, 2017 guptavikas.1051@rediffmail.com

149
Thank you
Have a nice day

8086 microprocessor

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8086 microprocessor