The document outlines the architecture and features of the Intel 8086 microprocessor, which is a 16-bit microprocessor with a 20-bit address bus capable of accessing up to 1 MB of memory. It describes the internal architecture, including the execution unit (EU) and bus interface unit (BIU), and details the function of various registers and memory segmentation. Additionally, it explains the organization of instructions, addressing modes, and how the microprocessor handles data and instruction execution efficiently using pipelining.

1. Microcomputers and
Interfacing
(ECEg-5171)
Lecture 02
Intel 8086 MICROPROCESSOR ARCHITECTURE

2. Outline
Features of 8086 Microprocessor
The 8086 Microprocessor internal architecture
– The Execution Unit
– The Bus Interface Unit
Register Organization
 General purpose registers
 Segment Registers
 Pointers and Index Registers
 Flag Registers
Bus Operation
Memory Segmentation 2

3. Features
 It is a 16-bit microprocessor.
 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16-bit registers.
 Word size is 16 bits.
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.

4.  8086 is designed to operate in two modes, Minimum and Maximum.
 It can pre-fetches up to 6 instruction bytes from memory and
queues them in order to speed up instruction execution.
Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has a separate address.
It requires +5V power supply.
 A 40 pin dual in line package.
Features

5. Internal architecture of 8086

6. Internal architecture of 8086

7. Internal architecture of 8086
 8086 has two blocks BIU and EU.
• The BIU handles all transactions of data and addresses on the buses for EU.
• It performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.
• EU executes instructions from the instruction system byte queue.
• Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining. This
results in
efficient use of the system bus and system performance. 7

8. EXECUTION UNIT
8
 The main parts :
• Control Circuitry
• Instruction decoder
• ALU
• General purpose registers(AX,BX, CX and DX)
• Special purpose registers(SP,BP,SI and
• Flag register.
 Main Functions:
• Fetches instructions from the Queue in BIU
• Decodes instructions fetched by the BIU,
• Sends request signals to the BIU to access the external module
• Performs arithmetic, logic and internal data transfer operations within the
microprocessor
• Generate control signals,
• Executes instructions.

9. EXECUTION UNIT – General Purpose Registers
 General purpose registers:
 8086 microprocessor has four 16 bit general purpose registers AX, BX, CX and
DX.
 Each of these can be divided into two 8 bit registers such as AH, Al; BH, BL;
etc.
 Beside their general use, these registers also have some specific(default)
functions.
 AX register (16 bits):
 It holds operands and results during multiplication and division
operations. All I/O data transfers using IN and OUT instructions use
A register (AL/AH or AX). It functions as accumulator during string
operations.
 BX register (16 bits):
9
• It holds the memory address (offset address) in indirect addressing

10. EXECUTION UNIT – General Purpose Registers
 CX register (16 bits):
 It holds count for instructions like
loop, rotate, shift and string
operations.
 DX register (16 bits):
 It is used with AX to hold 32 bit
values during multiplication and
division.
 It is used to hold the address of the
I/O port in indirect I/O addressing
mode.

11. EXECUTION UNIT – Pointer And Index Registers
 Pointer and Index Registers
 Used to keep offset addresses.
 Used in various forms of memory addressing.
 In the case of SP and BP the default reference to form a physical address is the
Stack Segment.
 The index registers (SI & DI) generally default to the Data segment register
(DS).
 The SI and the DI registers may also be used to access data stored in arrays.
Pointer Registers:
Stack Pointer (SP 16 bits)
It holds offset address of the top of the
Stack. Base Pointer (BP 16 bits)


BP can hold offset address of any location in the stack
segment. 11

12. EXECUTION UNIT – Pointer And Index Registers
Index Registers:
SI: Source Index register
 It is normally used to hold the offset address for Data Segment(DS).
 When string operations are performed, the SI register points to
memory locations in the data segment which is addressed by the DS
register. Thus, SI is associated with the DS in string operations.
DI: Destination Index register
 It is normally used to hold the offset address for Extra Segment(ES) .
 It holds offset address of destination in Extra Segment during string
operations. 12

13. EXECUTION UNIT – Flag Register
13
 A flag is a flip flop which indicates some conditions produced by the execution of
an instruction or controls certain operations of the EU .
 In 8086 The EU contains
• A 16-bit flag register
• 9 of the 16 are active flags and remaining 7 are undefined.
• 6 status flags: indicates some conditions affected by the ALU
– After every arithmetic or logic operation, they give the status of the
current result.
• 3 control Flag:
– The Control flags are used to control certain operations. They are changed by
the programmer.

14. EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some programs
and procedures .
Parity (PF) Indicates the number of 1-bits that result from an operation.
PF=0;odd parity, PF=1;even parity.
Auxiliary
(AF)
Holds the carry (half – carry) after addition or borrow after subtraction
between bit positions 3 and 4 of the result (for example, in BCD
addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=0; positive
14

15. Flag Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt
request) I=0; INTR pin disabled. I=1; INTR pin
enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
Overflow occurs when signed numbers are added or
subtracted. An overflow indicates the result has exceeded
the capacity of the Machine 15
EXECUTION UNIT – Flag Register

16. EXECUTION UNIT – Flag Register
• Six of the flags are status indicators reflecting properties of the
last arithmetic or logical instruction.
• For example, if register AL = 7FH and the instruction ADD AL,1
is executed then what will be the stet of conditional flags?
AL = 80H
CF = 0; there is no carry out of bit 7
PF = 0; 80H has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed

17. BUS INTERFACE UNIT (BIU)
 Contains
 6-byte Instruction Queue (Q)
 The Segment Registers (CS, DS, ES, SS).
 The Instruction Pointer (IP).
 The Address Summing block (Σ)->Address Generation Circuit

18. BUS INTERFACE UNIT (BIU)
 Functions
 It provides the interface of 8086 to external memory and I/O devices.
 It operates with respect to bus cycles (machine cycles). This means it performs
various machine cycles such as memory read, I/O read etc. to transfer data
with memory and I/O devices.
 The BIU handles all transactions of data and addresses on the buses for EU.
o
It generates the 20 bit physical address for memory access.
o
It fetches instruction from memory.
o
It transfers data to and from the memory and I/O.
o
It supports pipelining using the 6 byte instruction queue.

19. • It is a 6 byte first in first out (FIFO) memory used to implement pipelining.
• This queue permits pre-fetch of up to 6 bytes of instruction code. Whenever the
queue of the BIU is not full, the BIU is free to look ahead in the program by pre-
fetching the next sequential instruction.
• BIU fetches the next six instruction bytes from the Code Segment and stores it
into the queue.
• Execution Unit (EU) removes instructions from the queue and executes them.
The queue is refilled when at least two bytes are empty as 8086 has a 16 bit
data bus.
THE QUEUE (Q)

20. THE QUEUE (Q)
 Three conditions that will cause the EU to enter a waiting mode
• When the instruction requires access to a memory location not in the queue.
• When the instruction to be executed is a jump instruction; the instruction
queue should be flushed out (known as branch penalty too much
jumping around reduces the efficiency of the program)
• During the execution of slow instructions
•for example the instruction AAM (ASCII Adjust for Multiplication)
requires 83 clock cycles to complete for an 8086

21. Memory Segmentation
21

Two types of memory organizations are commonly used: linear addressing and
segmented addressing.

In linear addressing the entire memory space is available to the processor in one
linear array.

In segmented addressing the available memory space is divided into segments.

In 8086/88 the complete physically available memory is divided into 16 logical
segments.

Each segment is 64kB in size and addressed by one of the segment registers.

22.  Segments are special areas in the memory that is
defined in a program, containing the code, data,
and stack.
 The size of each segment is 64 KB.
 A segment may be located any where in
the memory
 Segments may be overlapped or non-
overlapped
Memory Segmentation…
22

23.  Each of these segments can be used for a specific function.
Code Segment (CS)
• Contains the machine instructions that are to execute.
• Typically, the first executable instruction is at the start of this segment, and the
operating system links to that location to begin program execution.
• CS register will hold the beginning address of this segment.
Data Segment (DS)
• Contains program defined data, constants and works areas.
• DS register is used to store the starting address of the DS
Stack Segment (SS)
– Contains any data or address that the program needs to save temporarily or for used
by your own “called” subroutines.
Extra Segment(ES)
• String instruction always uses extra segment.
• Used for shared memory.
23
Memory Segmentation…

24. Physical, Offset, and Logical addresses
 Physical address is the 20-bit address that is actually put on the address pins of the
8086 microprocessor and decoded by the memory interfacing circuitry. It is an actual
physical location in RAM or ROM within the 1MB memory range.
 Logical address consists of a segment value and an offset address.
• Address viewed with respect to one segment (Seg.Reg : Offset)
 Offset The distance(displacement) in bytes from the segment address to another
location within the segment.
• Thus the first byte of the code segment is at offset 00,the second byte is at offset 01
and so
forth.
Actual Address = Segment Address + Offset

25. Segment registers
25
format) to obtain the real address of the data in data
 In 8086/88 the processors have 4 segments registers
 Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES)
and Stack Segment (SS) register.
 All are 16 bit registers.
 Each of the Segment registers store the upper 16 bit address of the starting address of
the corresponding segments.
 CS register
 Contains the starting address of code segment.
 The content of the CS register is added with the content in the Instruction Pointer
(IP)
register to obtain the address of the instruction that is to be fetched for execution.
 DS register
 Contains the starting address of data segment.
 The address in DS register will be added with the value in the address field (in
instruction

26. Segment registers
 SS Register
 Contains the starting address of the stack segment.
 The content in this register will be added with the content in the Stack Pointer (SP)
register
to obtain the required word.
 ES (Extra Segment) Register
 Used by some string (character data) operations to handle memory addressing
 Points to the extra segment in which data is used. String instruction always uses
extra segment.
 ES register is associated with the Data Index (DI) register.
26

27.  It allows to extend the address ability of a processor i.e. segmentation allows the use of 16
bit registers to give an addressing capability of 1 MB. Without segmentation, it would require
20 bit registers.
 Allows the placing of code, data and stack portions of the same program in different
parts (segments) of the memory, for data and code protection.
 Permits a program and/or its data to be put into different areas of memory each time
program
is executed, i.e. provision for relocation may be done .
 The segment registers are used to allow the instruction, data or stack portion of a program to
be more than 64Kbytes long. The above can be achieved by using more than one code, data
or
Advantage of Segment memory Scheme
stack segments.
27
 Segmentation builds re-locatable and re-entrant programs easily.

28. Instruction pointer & summing block
28
 Instruction Pointer (IP)
 It is a 16-bit register which contains the offset address or displacement for the
next instruction in the Code Segment that will be executed by the CPU.
 The value in the IP register will be added into the value in the CS register to
obtain the real
address of an instruction.
 Address of the next instruction is calculated as CS x 10H + IP.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch occurs.
 Address Generation Circuit
 The BIU has a Physical Address Generation Circuit. It generates the 20 bit
physical
address using Segment and Offset addresses using the formula:

29. Segment and Memory Addressing

30. Instruction pointer & summing block
The segment-offset scheme allows programs to be relocated in memory on 16 byte
boundaries
Address Generator

31. Addressing Modes : Memory Access
31
 Physical Address will have to be calculated Physical Address : Actual
address of a byte in memory. i.e. the value which goes out onto the address
bus.
 Memory Address represented in the form of
Seg : Offset (eg - 89AB:F012)
 Each time the processor wants to access memory, it takes the contents
of a segment register, shifts it one hexadecimal place to the left (same as
multiplying by (10)16 ), then add the required offset to form the 20- bit
address
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)
F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)

32. • Example For Address Calculation (segment: offset)
• If the data segment starts at location 1000h and a data reference contains the
address 29h where is the actual data?
Required Address
Offset
Segment Address
0000 0000 0010 1001
0000
0001 0000 0000 0010 1001
0001 0000 0000 0000

33. Segment and Address register combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)
• ES:BX ES:SI