The 8086 is a 16-bit microprocessor that can access up to 1MB of memory. It has an internal architecture with two main units - the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles fetching instructions from memory and passing them to the EU via an instruction queue. The EU then decodes and executes the instructions. The 8086 supports segmented memory addressing using segment registers and offsets. It has general purpose registers like the accumulator, flags to indicate arithmetic results, and pointer/index registers used for memory addressing.
Bus Interface Unit(BIU) of 8086 MicroprocessorArafat Hossan
BIU and EU of 8086 MP
The Bus Interface unit (BIU)
Different Parts of BIU
Instruction Queue
Segment Register
Code segment (CS)
Stack segment (SS)
Extra segment (ES)
Data segment (DS)
Instruction Pointer
A introduction to 8086 microprocessor
Your Crash course in your Pocket! Microprocessors: 8085, 8086, 80386, Pentium… Microcontrollers: 8051, ARM… Computer Organisation & Architecture
what is 8086 microprocessor, and its features
But we couldn’t pass up celebrating the 8086's anniversary in style. Time for a little DIY action to turn it into a work of art!
On this channel you can get education and knowledge for general issues and topics
The architecture of 8086 provides a number of improvements over 8085 architecture.
The complete architecture of 8086 can be divided into two parts.
(a) Bus Interface Unit (BIU)
(b) Execution Unit (EU)
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
Bus Interface Unit(BIU) of 8086 MicroprocessorArafat Hossan
BIU and EU of 8086 MP
The Bus Interface unit (BIU)
Different Parts of BIU
Instruction Queue
Segment Register
Code segment (CS)
Stack segment (SS)
Extra segment (ES)
Data segment (DS)
Instruction Pointer
A introduction to 8086 microprocessor
Your Crash course in your Pocket! Microprocessors: 8085, 8086, 80386, Pentium… Microcontrollers: 8051, ARM… Computer Organisation & Architecture
what is 8086 microprocessor, and its features
But we couldn’t pass up celebrating the 8086's anniversary in style. Time for a little DIY action to turn it into a work of art!
On this channel you can get education and knowledge for general issues and topics
The architecture of 8086 provides a number of improvements over 8085 architecture.
The complete architecture of 8086 can be divided into two parts.
(a) Bus Interface Unit (BIU)
(b) Execution Unit (EU)
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
computer organizaton and architecture
topic- microprocessors, segment registers
this ppt gives brief discription about microprocessors topic in computer organization and architecture
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
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This document will discuss each of the underlying technologies to create and implement an e- commerce website.
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In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
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COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
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2. 2
Features
• It is a 16-bit μp.
• 8086 has a 20 bit address bus can access up
to 220 memory locations (1 MB).
• It has multiplexed address and data bus
AD0- AD15 and A16 – A19.
• It requires +5V power supply.
• A 40 pin dual in line package.
3. 3
• 8086 is designed to operate in two modes,
Minimum and Maximum.
• It can prefetches up to 6 instruction bytes
from memory and queues them in order to
speed up instruction execution.
• Address ranges from 00000H to FFFFFH
• Memory is byte addressable - Every byte has a
separate address.
5. 5
Internal architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU handles all transactions of data and
addresses on the buses for EU.
• The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
• EU executes instructions from the instruction
system byte queue.
6. 6
• Both units operate asynchronously to
give the 8086 an overlapping instruction
fetch and execution mechanism which is
called as Pipelining. This results in
efficient use of the system bus and
system performance.
• BIU contains Instruction queue, Segment
registers, Instruction pointer, Address
adder.
• EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register,
Flag register.
7. 7
BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)
8. 8
THE QUEUE (Q)
• The BIU uses a mechanism known as an
instruction stream queue to implement a pipeline
architecture.
• This queue permits pre-fetch of up to 6 bytes of
instruction code. Whenever the queue of the BIU is
not full, it has room for at least two more bytes and
at the same time the EU is not requesting it to read
or write operands from memory, the BIU is free to
look ahead in the program by pre-fetching the next
sequential instruction.
9. 9
• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.
• After a byte is loaded at the input end of the queue,
it automatically shifts up through the FIFO to the
empty location nearest the output.
• The EU accesses the queue from the output
end. It reads one instruction byte after the other
from the output of the queue.
• The intervals of no bus activity, which may occur
between bus cycles are known as Idle state.
10. 10
Opcode
Data
Opcode queue
From
memory
Repeat the same procedure
for successive contents of Q
Execute it with data bytes
decoded by the decoder
Take 2nd byte from Q as
opcode, decode 2nd byte
opcode
Execute it with data bytes
decoded by the decoder
Is it
Single
byte?
Take 2nd byte from Q as
opcode, decode 2nd byte
opcode
(Decode also decides the no. of
data bytes for the instructions)
Update
queue
Opcode 2nd byte
yes
No
The Queue Operation
11. 11
Segmented Memory
Code segment (64KB)
Data segment (64KB)
Extra segment (64KB)
Stack segment (64KB)
1MB
The memory in an 8086/88
based system is organized as
segmented memory.
The CPU 8086 is able to
address 1Mbyte of memory.
The Complete physically
available memory may be
divided into a number of logical
segments.
00000
FFFFF
Physical Memory
12. 12
• The size of each segment is 64 KB
• A segment is an area that begins at any location which is
divisible by 16.
• A segment may be located any where in the memory
• Each of these segments can be used for a specific
function.
– Code segment is used for storing the instructions.
– The stack segment is used as a stack and it is used to store the
return addresses.
– The data and extra segments are used for storing data byte.
13. 13
• The 4 segments are Code, Data, Extra and Stack segments.
• A Segment is a 64kbyte block of memory.
• The 16 bit contents of the segment registers in the BIU
actually point to the starting location of a particular segment.
• Segments may be overlapped or non-overlapped
14. 14
Segment registers
• In 8086/88 the processors have 4 segments
registers
• Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
16. 16
Instruction pointer & summing block
• The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
• The IP always references the Code segment register
(CS).
• The value contained in the instruction pointer is called as
an offset because this value must be added to the base
address of the code segment, which is available in the
CS register to find the 20-bit physical address.
• The value of the instruction pointer is incremented after
executing every instruction.
• To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing
block) to the address contained in the CS , which has
been shifted four bits to the left.
18. 18
• The following examples shows the CS:IP scheme of
address formation:
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR
four binary digits left
3 4 B A 0 ( C S ) +
8 A B 4 ( I P )
3 D 6 5 4 (next address)
34BA 8AB4CS IP
34BA0
3D645
44B9F
Code segment
8AB4 (offset)
19. 19
• Example For Address Calculation (segment: offset)
• If the data segment starts at location 1000h and a data
reference contains the address 29h where is the actual
data?
Required Address
Offset
Segment Address
0000 0000 0010 1001
0000
0001 0000 0000 0010 1001
0001 0000 0000 0000
20. 20
EXECUTION UNIT
• Decodes instructions fetched by the BIU
• Generate control signals,
• Executes instructions.
The main parts are:
• Control Circuitry
• Instruction decoder
• ALU
21. 21
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
8 bits 8 bits
16 bits
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
AX
BX
CX
DX
Pointer
Index
8 bits 8 bits
16 bits
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
EXECUTION UNIT – General Purpose Registers
22. 22
EXECUTION UNIT – General Purpose Registers
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic
AH Byte multiply, byte divide
BX Store address information
CX String operation, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O
(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register)
23. 23
Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to
form a physical address is the Stack Segment (SS-
will be discussed under the BIU)
• The index registers (SI & DI) and the BX generally
default to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
24. 24
• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register
points to memory locations in the data segment which is
addressed by the DS register. Thus, SI is associated with
the DS in string operations.
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI register
points to memory locations in the data segment which is
addressed by the ES register. Thus, DI is associated with
the ES in string operations.
• The SI and the DI registers may also be used to access data
stored in arrays
25. 25
EXECUTION UNIT – Flag Register
• A flag is a flip flop which indicates some conditions produced by
the execution of an instruction or controls certain operations of
the EU .
• In 8086 The EU contains
a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
6 flags indicates some conditions- status flags
3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF
Carry
Over flow Direction
Interrupt Trap
Sign
Zero
Auxiliary
Parity
U - Unused
26. 26
EXECUTION UNIT – Flag Register
Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. S=1; negative, S=0
27. 27
Flag Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging
feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
Overflow occurs when signed numbers are added or
subtracted. An overflow indicates the result has exceeded
the capacity of the Machine
28. 28
Execution unit – Flag Register
• Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed