This document proposes algorithms for floorplanning reconfigurable functional units on reconfigurable architectures. It aims to minimize fragmentation while considering device heterogeneity, reconfiguration capabilities, and inter-unit communication. The approach partitions a task graph into reconfigurable regions, floorplans units within each region, and then floorplans the regions on the device using simulated annealing. Experimental results show improvements over existing approaches in area usage and communication performance.

1. Time-driven reconfiguration-aware floorplacer BY Alessio Montone [email_address] NDDRESD Baceno, Goglio – Jul 29, 2008

5. INTRODUCTION

12. FLOORPLACEMENT

13. Floorplanning vs. Placement Placement Floor plan Characteristic Floorplanning Placement # items <100 >10.000 Items (for FPGAs) IP-Core Slice, CLB Aim Find a position for each item obj. function depends mainly on Area mainly on Wirelength Constraints Items can be positioned everywhere There is a set of possible positions

17. THE PROPOSED APPROACH

20. Input

21. Proposed Approach: overview

28. 2 nd Algorithm:TFiRR - VI

29. 2 nd Algorithm: TFiRR – Example

32. 3 rd Algorithm: RR floorplacement – Example - I

33. 3 rd Algorithm: RR floorplacement – Example - II

36. EXPERIMENTAL RESULTS

37. Identification of the number of RRs

41. COMPARISON WITH THE STATE OF THE ART

42. State of the art Authors Comm. Infrastructure Resource Aware Reconfiguration Aware Device Limits Aware Bazargan et al. No No Yes No Yuh et al. Limited, w/ High Overhead No Yes Yes Singhal et al. No No Yes No Feng et al. No Yes No No

51. Questions