this is the presentation shows how test pattern generators and output response compactors are developed using cellular automata techniques which are used for built in self test purpose.

1. ECE-DEPARTMENT
1. SHIVA SHANKER BEERAVELLI : 10T81A0448
2. PALUSA KRANTHI KUMAR GOUD : 10T81A0417
3. G.SHIVA NARAYANA REDDY : 10T81A0449
4. SHEELAM RAMU : 10T81A0431
Internal Guide:
Mr.K.ASHOK KUMAR
Assoc. Prof & HOD-ECE

2. A MINI-PROJECT
ON
IMPLEMENTATION OF
HYBRID CELLULAR AUTOMATA AS A TEST
PATTERN GENERATER & RESPONSE COMPACTOR
FOR BIST

3. CONTENTS:
 Objective
 Working Principles
 Diagrammatic View
 Advantages /Disadvantages With Examples
 Applications in Real Time Scenario
 Future Extension of the Project
 Summary
 References /Bibliography

4.  WHY TESTING IS IMPORTANT IN VLSI
DESIGN ?
 Specifications
 Code designing
 Code verification
 RTL designing
 Simulation
 Synthesis
 Fabrication
TESTING
 packing
PROBLEM:
Testing of circuits in past was done
by ATE

5. PRESENT APPROACH FOR TESTING:
(DFT-DESIGN FOR TESTABILITY)
 BUILT-IN-SELF TEST
 BIST eliminating the dependence on an external
automated test equipment (ATE)
Block Diagram shows TESTING Process
Seed value
Seed value
din
Good/fault

6. MAIN OBJECTIVE:
 To construct the TPG
 To construct the ORA
Using CELLULAR AUTOMATA (CA)
Pseudo random
generator

7. CELLULAR AUTOMATA:
 Cellular automata is collection of cells with regular
collections.
Working Principles/Rules:
 Each cell connects to its local neighbors by using
rule 90 and rule150.
Flip-flops

8.  Rule 90:  Rule 150:
 Transition function [rule 90] : Xc(t+1) = Xc-1(t) xor Xc+1(t).
 Transition function [rule 150]: Xc(t+1) = Xc-1(t) xor Xc(t) xor Xc+1(t).
C-1 : past
C : present
C+1 : future
Diagrammatic View:

9. Cellular automata as a TEST PATTERN GENERATER :

10.  CA produces (2^n-1) test patterns automatically.

11. Cellular automata as a RESPONSE COMPACTOR:
din din
din
din
din

12.  Lower cost of test, since the need for external electrical
testing using an ATE will be reduced, if not eliminated.
 better fault coverage, since special test structures can be
incorporated onto the chips.
 easier customer support.
 capability to perform tests outside the production electrical
testing environment.
 Shorter test times if the BIST can be designed to test more
structures in parallel.
Advantages:

13.  additional silicon area and fob processing requirements .
 additional pin requirements.(since the BIST circuitry need a way to
interface with the outside world to be effective)
 possibly bigger package size
Disadvantages:

14.  Integrated circuit manufacture :BIST is used to make faster,
less-expensive integrated circuit manufacturing tests.
 Computers(pc’s test itself at startup)
 Medicine (medical devices test themselves to assure continued
safety )
 Military (used in missiles where the bist is computer c
controlled)
Applications in Real Time Scenario :

15. Future Extension of the Project:
•Built-In Self-Repair (BISR).
•Transparent BIST for RAMs.
•Programmable memory BIST.

17. References /Bibliography:
1. Bushnell and Agrawal, “Essentials of Electronic Testing for
Digital, Memory & Mixed-Signal VLSI Circuits” New York:
Kluwer Academic Publishers, 2002
2. Serra, M.; Slater, T.; Muzio, J.C.; Miller, D.M., “The
analysis of one-dimensional linear cellular automata and
their aliasing properties, IEEE Transactions on, Volume: 9 ,
Issue: 7 , July 1999, Pages:767 – 778.
3. Jianbing Zhao., “A Novel FPGA Manufacture-oriented
Interconnect Fault Test,” 9th International Conference on
Solid-State and Integrated-Circuit Technology, 2008