This document provides a summary of Laird Snowden's experience and qualifications. It includes contact information, a performance summary, and lists membership in professional organizations. The bulk of the document describes Snowden's extensive experience in semiconductor testing and new product introduction, including bringing fabrication facilities online, developing automated test equipment, improving yield, and reducing test time. It highlights experience at companies including Bell Labs, AT&T, TriQuint, and Silicon Labs.

1. LAIRD SNOWDEN
 184 Avenida Tejas, Kyle, TX 78640  512-210-9786  larsnow1@aol.com https://www.linkedin.com/in/laird-snowden-
11657015
NPI | SENIOR MTS |SEMICONDUCTOR
PERFORMANCE SUMMARY
CTRL-CLICK:CURRICULUM VITAE
CTRL-CLICK:RECOMMENDATIONS FROM PROJECT PRINCIPLES
CTRL-CLICK:COVER LETTER
MEMBER IEEE, RESEARCHGATE, HORIZON 2020,BELL LABS ALUMNI
I enjoy , I challenges will acquire the knowledge Ineed in real time as I have in all my successes,because I love going into a
dark room,illuminating it and building it out, improving and fixing new technology and problems, no matter what job I have, I
will do this, I will look for a better, more efficient way of doing things, in even the most humble job, which can be anything,
does nothave to be the same thing I have done in the past, I enjoy new challenges, the things most people run away from, I
will run towards.
You can find more detailed information and pictures on my Linkedin page, which is a superset of my Semiconductor
experience and so will have other areas ofmy work and experience;Anthropological,Theology, Climatology, Medical, and so
on. I enjoy all studies and pushing back the boundaries of what is doable.
https://www.linkedin.com/in/lairdsnowde
I work with people, investigate, do private research and then work with peers to solve problems, if need be, I can work as a
sole contributor, but I prefer not to, since implementation is more difficult.
I have extensive experience in RF/ASIC/Hybrid/Analog/Digital NPI. At AEL/TRACOR I built brass boards for feedforward
amplifiers,Log Video Amplifiers (delay line technology to allow tracking operation in the presence of jamming signals) , SRM
ALR65 phased array modules including developing a ceramic filter for a 10 band RF Dual converter module to fix an out of
tolerance spur. I built an automated rack and stack spurious analyzer tester, as well as satellite display tester and vario us
lab test setups for RF detectors.
At Bell Labs I performed lab testing with all instruments including BERT, S-Parameter including probe at 80 GHz on a
distributed amplifier,S-Parameter TDR option to locate discontinuities. I brought up automated production test for both Rack
and Stack and ATE. This included the AT&T Longlines fiberoptic GaAs:OC48 CDR,Laser Driver, Transimpedance Amplifier,
Limiting Amplifier and also OC48 Transceiver transmitter and receivers (BiCMOS).
I developed the world’s first ATE/Sonet IP tester with LTX to testthe transceiver and meet the 8 second test time (down from
30 minutes with rack and stack). If doing this again, I would use IP and hybridize a low cost J750 to do the same thing.
I developed a means to model our GaAs fab to device probe and a means to model device probe to package test. I used this
data and these models to improve yield, moving our SBU from losing money with every part we shipped to the most
profitable, returning $250M on $500M sales, I was told this was impossible, so that is why I did it. I created a relational
database, loading crons and developed Neural Network models which could handler high dimension non orthogonal data
(information in tails) handles crossing and non-crossing interactions, i implemented wafer predictive yield reports at the
foundry based on process data,which we used to build our wafer store house. I built an internal RF die probe lab to bring up
OC 192 devices and for NPI FA.
I wrote my own test executive and set up the SRM data and program network for production testers
When AT&T transferred our 3 inch SARGIC GaAs HEMT EPI line to TriQuint and converted to 5 inch wafers, another SBU
tried for 2 years to bring it up and failed. I told our group we have to take it away from them, because my wafer store was
almost depleted. My group elected me to lead the bring up. I held weekly meetings, set the fab targets, analyzed and
discussed bring up test data and together, we formulated corrective actions using the input from the team. We had first lot
success at 98% device wafer yield in 90 days ! Package yield also in the high 90%.
At Silicon Labs (CMOS), I worked with Agilent to add a digital filter for the lower f1 corner of their E5052 analyzer to extend
jitter performance, they had been using a brick wall filter, which failed our jitter spec due to the error of a brickwall fil ter.
I deployed this on all testers at Silicon Labs Phy and clocks line to test sub Pico second jitter in production

2. I interviewed our 11 man design team, wrote a 100 page test document in accordance with recommendations for each test
block, developed and wrote the tests for the world’s first any rate clock. Brought up test.
I did the same for the world’s firstcrystaless oscillator,adding a modified temperature profile which compensated the part in
500 milliseconds from 0 degrees to 80 degrees (spec). This part also included on chip test instruments to reduce test time
(line settling) and had to have metrological calibrations on the internal testsections. Total test time was less than 2 sec onds.
The part had many configurations, 6 output buffer types, etc., I wrote a test that would auto configure itself based on the lot
number (pull the config data from the customer order data base)
I brought up PXI National Instruments automation for lab verification
I have taught College Evening Division Electrical Engineering courses in Theory, Math and Lab.
Silicon Validation: ATE and Lab Full production bring up Wafer probe to 80 GHz bring
up.
Product NPI Bring up Software programming Yield Improvement
New Technology Bring up Statistics, SQA, SQL. Business Turn Around
Semiconductor Fab Bring up Lot Acceptance criteria Technical Integration
Test Circuit Design
Process and device FA
Mixed Signal Test
Vendor new product bring up
Advanced Device Modeling
RF Microwave test bring
up
Reliability Testing
Offshore deployment
Project Management
JEDEC. BellCore, Mil Spec test
Data Sheet creation 6 sigma,
cpk limits
Multi-Site test bring up
Career Highlights BUSINESS
● NEW TECHNOLOGY DEVELOPMENT: Developed and partner with Key Vendors to define and build new
technologyneeded for New ProductIntroduction. Built Worlds firstATE/Telecommunications tester which reduced
Fiber Optic Chip Set Device Under test time from 55 minutes to 8 seconds.
● BUSINESS TURNAROUND: Analyzed AT&T Fiber Optic LONGLINES SBU financial losses, created Neural
network models thathad been impossible and turned SBU around from losing money to returning $250M on $500M
sales (per year)
● MANUFACTURING FACILITY BRING UP: Took over team leadership of$1B GaAs III-V SARGIC HEMT/EPI fab
bring up at Tri-Quint from previous leader who still failed after two years of work. I had the fab up and running at
98% yield in 90 days using my data from our SBU turnaround.
Key Accomplishments ENGINEERING
 Salvaged critical Defense Electronics account for F-15 EW Modules. : Called upon to fix a failure in our new warfare
module after 9 months of part failures risked the loss of a significant military contract and associated penalties. I was told it
was a lossyRF line.I designed and builta special RFProbe and discovered the true cause, which was not a lossy line but LO
leakage at a notch filter in the circuit.. . I designed new ceramic resonator filter to prove it and then I showed myboss,who then
told me they did not include the notch filter because the chief scientist said it was too hard to design and would not work. My
filter design worked perfectlyand was put into production. I saw it working in the gulf war when SAM missiles were not hitting
our pilots. I also saved the contract and also $3M in retooling costs by finding a way to retrofit my new filter without re -tooling
the module frame.
 I reduced time to bring up NPI test for complex mixed signal devices with NVM cutting bring up by a factor of ten.
Software Design: In order to meet the test development tasks for this new part, I wrote software to create mixed signal
test patterns. I Wrote mixed signal digital pattern generator for all protocols, I2C, SPI, Manchester etc, with microcode for
analog testing, significant reduction in time to develop mixed signal test and I provided editable and archived patterns all
automatically commented.
 Developed and deployed the World’s first ATE/SONET IUP tester on an LTX Fusion HF Mainframe . CREATE ATE
Testing Built WORLDS FIRST Telecommunication ATE: Our C level manager asked if I could develop a tester for a
new project, OC48 SONET Transceiver chip set for high volume and low cost, everyone else told him it could not be done. I
said I could do it and told him how. I built the world’s first Hybrid ATE tester with LTX for our Transceiver chipset. Specified
hardware modification, new test methodology and co-developed the test software with LTX. ICD paper: Hybrid ATE built on

3. their Fusion HF platform to meet high volume low cost of test bulletin Project $3.2M budget, within a year, designed an
intermediate device personality board, created test methods, and developed handler and manual testing interface hardware.
This was accomplished within cost and throughput goals, creating a new standard for telecommunication testing. Final full
SONET test time was 4 seconds; down from 30 minutes for Rack and Stack testing. Test time reduction and throughput
provided a 1 year pay back. I would do it much differently today further saving millions in bring up cost .
Career Experience
NORTH CAROLINA CONTRACT SEPT 2016 TO DECEMBER 2016
LAB VALIDATION TEST REQUIRED AUTOMATION DEVELOPMENT:
1 I BROUGHT UP THE CUSTOMER TEST BOARD SETUPS TO PROVE IN REV A AND REV B PARTS
2 DESIGNED AND DEPLOYED TWO FLEXIBLE NATIONAL INSTRUMENTS TEST CARD TO DEVICE INTERFACE, TO ACCESS ALL NI RESOURCES AS ATE
TESTERS DO. THIS REDUCED VALIDATION TEST BRING UP TIME AND ENABLED DESIGNERS TO DEBUG OFFSHORE VECTOR SETS ON REAL DEVICES
(WHERE THERE WAS DISPERSION BETWEEN SIMULATION AND DEVICE PERFORMANCE).
3 I MET VERY SHORT DEADLINE TO BRING UP TEST AND SHIP 277 SAMPLES WITH DATA COLLECTION.
4. I DESIGNED A DIGITAL LEVEL SHIFTER CAPABLE OF DYNAMICALLY ADJUSTING DIGITAL VOH IN REAL TIME TO FOLLOW A DEVICE OUTPUT PORT
(TO PREVENT LATCHUP) FOR A CUSTOM ASIC.
5. SETUP BACKEND DATA ANALYSIS WITH THE PRODUCTION MANAGER TO CREATE CUSTOMER VALIDATION DATA REPORTS, TO REDUCE
VALIDATION COMPLETION TIME.
SABBATICAL
PRIVATE RESEARCH AND STUDY, MEMBER RESEARCHGATE.NET
( 2013 to Present)
After my wife passed away, I took sabbatical during this time
1. I developed,designed and builta recorded music sound field restoration system, Ibuilt three of them.
2. I studied managementand leadership and gained a greatdeal of experience in debate,leadership.
3. I studied Theologyand Anthropology to round out my technical education.I rebound very old books and builta very nice
library, preferring the erudition of ancientmanuscripts and writings to postmodern writings which tend to be shal low,
superficial and somewhatrandom.
4. IOT Electronics is also myhobby, I worked with Arduino, RaspberryPi, and sensor,memorymapped IO,cloud computing
and so on. I had designed a memorymapped IOproduction tester when I started my career, so I find Arduino et al fun and
easy for IOT .
5 Architecture, I designed a chapel emblematic ofa first century church,it is has been builtat a cloister for the Dominican
Sisters.
6. I began to compose classical music, I have composed hundreds,one ofmy early ones is on my Linkedin page
(composition #35).I do this to relax.
& I authored 158 Technical papers on diverse topics to grow and verify knowledge and understanding and to share with
others.
SILICON LABS, AUSTIN, TX
(A $620M fabless semiconductor company with 1,100 Employees)
NPI | Staff Engineer | SEMICONDUCTOR (PARTIAL LIST OF ACCOMPLISHMENTS)
(2003 – 2013)
PRODUCTION Restoration: We had parts failing at the customer location. Our team thoughtit was die crack propagation. I
looked more closelyat the X-Ray and found the cracks did not propagate pastthe seal ring. I found the failure more consistent
with ESD damage. I used a field meter to prove that ESD voltage was building up in the Torlon end effecter of the test handler;
after some re design ofthe kits. I implemented a testchamber ionizer and restored full production .
MANUFACTURING DEVELOPMENT: Our RDL production phase noise instruments were atend of life. The closest
instrumentIcould find was Agilent E50502. It however did not have a low enough noise floor. I specified a digital filter modification
I needed to Agilent and they created the firmware according to my specifications. Iwas able to get jitter for OC48 and OC192
SONET IP rates with one acquisition atless than 300 mS,returning sub pico second jitter..
QUALITY ASSURANCE: As NPI engineer for the world’s firstviable any rate clock and also the first any rate crystal less
oscillator….I was responsible for full manufacturing and risk mitigation. I specified and installed a central NIST primary clock

4. reference,using a Rubidium atomic clock and GPS disciplining to guarantee parts were being setto the correct frequency, verified
on a continuous basis
Software Design: In order to meetthe testdevelopmenttasks for this new part, I wrote software to create mixed signal test
patterns. I Wrote mixed signal digital pattern generator for all protocols,I2C,SPI, Manchester etc, with microcode for analog
testing,significantreduction in time to develop mixed signal testand I provided editable and archived patterns all automa tically
commented.
AT&T BELL LABS MICROELECTRONICS, NEW YORK CITY, NY ; READING WORKS 1988
TO 2003
(A $40B telecommunications company with 26,000 Employees)
NPI | STAFF ENGINEER | MTS | Semiconductor
(Full P&L ($500M Revenue Goal), 20 employeeswith 5 direct)
MTS (Member Technical Staff) performed at Director level, fab bring up and SBU turn around.
 PRODUCTION Restoration: My first job at AT&T Bell Labs microelectronics was wafer probe for the longlines fiber optic
chip set. The entire Rack and Stack test executive was a Bell Labs creation. It hung all the time and was not intuitive to use. I
rewrote the entire program (500,000 lines and added an additional 500,000lines) after that it worked flawlessly, any operator
could use it, it configured itself by the lot traveler) it prevented damage to probe cards and it provided full on line statistics
printout. I wrote the software for xbar and R, historical data qq norm plot, etc.
 PRSENTATION: Invited by NIST to present a paper to ARFTG Convention, ctrl-click to read. On my work in building the first
membrane probe card with Cascade Microtech
 PRESENTATION Paper ICD Test and Product International Symposium, ctrl-click to read My development of world’s first
Hybrid ATE with LTX
 Fab Bring up Restoration: I called a meeting and after two years of waiting for the Wireless SBU failed bring our fab up at
TriQuint, I informed our GM, that my wafer storehouse was almost depleted and that we needed to take it over immediately, I
asked by GM and Chief Scientist with leading Technical methodology to Bring up our $1B fab, which we transferred from
AT&T Reading PA. to TriQuint OR. This is one of the world’s most complex Semiconductor fab processes (SARGIC HEMPT
EPI III/V GaAs semiconductor) because I had identified the process targets from my previous project when I improved our
package yield from 20 % to 98% . Over the course of 90 days, devised the strategy and led implementation by defining goals,
roles, and tasks with metrics to chief scientists and validated results. Achieved a new first in wafer yield at 98 percent. This
met customer reliability requirements and AT&T continued to earn $1M per second on our longlines chipset.
 CREATE ATE Testing Built WORLDS FIRST Telecommunication ATE: Our C level manager asked if I could
develop a tester for a new project, OC48 SONET Transceiver chip set for high volume and low cost, everyone else told him it
could not be done. I said I could do it and told him how. I Built the world’s first Hybrid ATE tester with LTX for our Transceiver
chipset. Specified hardware modification, new test methodology and co-developed the test software with LTX. ICD paper:
Hybrid ATE built on their Fusion HF platform to meet high volume low cost of test bulletin Project $3.2M budget, within a year,
designed an intermediate device personalityboard,created test methods,and developed handler and manual testing interface
hardware.This was accomplished within cost and throughput goals, creating a new standard for telecommunication testing.
Final full SONET test time was 4 seconds; down from 30 minutes for Rack and Stack testing. Test time reduction and
throughput provided a 1 year pay back.
 SBU Turnaround | My first jobs at AT&T Bell Labs was to baby site the wafer probe on our longlines chipset test area, our
SBU was called the “Black Hole of Calcutta” and a “Rat Hole we pour money down” I hated that and I decided to change it.
Everyone told me it could not be done, others had tried and failed and I said, NO, I can fix it. I studied the problem, desi gned
the fix, then verified the fix and then confirmed the verification, then turned it on and it worked perfectly, as I had already proven
it would. Yield & Throughput Improvement: AT&T Bell Labs had attempted to create models from uncorrelated data with
continual failure eroding profits. Internal research revealed a methodology(ctrl-click for white paper) that could handle all of the
constraints. Had to develop a photographic map technique of PCM wafer process data in 3D imaging to understand
the yield patterns. These efforts resulted in creating an understanding of the process, which improved yield and throughput
and resulted in SBU restoring profitabilityand becoming the mostprofitable division of Bell Labs with $250M in profits. Wrote a
published IEEE paper on the method.
 Discuss Product Definition requirement for Jitter Analyzer with Agilent: This became the TS-500, TS-1000,
TS-1500 which is based on an Defense Electronics Test platform for Radar EW Systems.
AEL HUGHES (AMERICAN ELECTRONICS LABS), MONTGOMERYVILLE, PA 1985 –
1988
(A $4B electronic warfare module company with 500 Employees)

5. Microwave/Digital Engineer | NPI | Semiconductor | Microelectronics
($10M budget with5 employees)
RF/Microwave Engineer
 Product Redesign: Called upon to fix a failure in our new warfare module after 9 months ofpart failures risked the loss of
a significant military contract and associated penalties. I was told it was a lossy RF line. I designed and built a special RF
Probe and discovered the true cause,which was not a lossyline butLO leakage ata notch filter in the circuit.. . I designe d new
ceramic resonator filter to prove it and then I showed my boss, who then told me they did not include the notch filter because
the chief scientist said it was too hard to design and would not work. My filter design worked perfectly, I proved it in
operationally in the Vibration simulator with an F-15 tail vibration program, it was fully deployed into production. I saw it
working in the gulf war when SAM missiles were not hitting our pilots.
 Customized Testing / Validation: My boss told me that we were second source for a SUBACS memory hybrid module.
We could not afford an ATE test set,so we decided to build our own tester out of a Commodore 64 (a lot like today’s Arduino)
My boss trusted me to design it, I used memory mapped IO coupled with Transmission gates in my test system design..
Interfaced an access time tester and acquired pass -fail test vectors, expanded test procedures, and designed and built
hardware and software, I wrote the test vectors in Assembly to speed up testing. Created thermal test chamber and
added debug test routines, retest test flows and validated. Delivered a superior product while eliminating millions in costs
and demonstrating superiority in blind tests against competitors. In the entire project, we only had one return, which
was a module someone dropped in a solder bath and it blew up… I can’t prevent that
RETS:Broomall PA,/Chicage IL
Professor ELECTRICAL/Microcomputer EE Courses I had perfect 4.0. I was invited to teach the same
degree , Evening Division, I taught Passive electronics, Semiconductor theory, transistor design,
amplifier and oscillator design, digital and micro processor and programming and engineering math
and lab. I enjoyed teaching and had good student reviews. As a student I was on the Dean’s list and
had highest Academic Honors.
Technical Skills
Transmission line theory, PCB signal integrity, EMI reduction (Si500) NPI, C++, CMOS, BiCMOS, SiGe, SiC, ERGIC, CVD SARGIC HEMPT EPI, RF
Probe, RF TEST and DEBUG RF LAB IP3, NF, ACPR, phase noise, lock time Offshore manufacturing Bring Up, DFT, GR&R, Teaching Engineering
Theory, Internal RF Die probe, Test Hardw are design and construction, Vendor Product Development, Test Circuit design, Produc t electrical design
FA, Process FA, Device Quality testing, Process QA, Developing leading edge test capability, NIST standards, Metrology, Yield improv ement, Mixed
Signal, ASIC, NVM, Digital communication protocol, Manchester, SPI, I2C, pattern creation Macros, Lights Out test automation, Know n Good Die, SQL
Engineering database, Yield Optimization, SBU turnaround, manufacturing optimization, process development, Team leadership, Semiconductor Fab
Bring up, RF characterization, Lab setup and Rack and Stack Automation, ATE test bring up, Multi Site test development, Multi Site Probe and Handler
development and bring up, ATE/RF test circuit design, polynomial Thermal sw eep optimization, Test executive creation, AWK, SED Unix Perl, TCU,
VB Excel Macro creation, Microsoft Office, VISIO, Oracle, Image, Cadence envision, Lab view , Matlab, Plus, Trough, Croons, Applications
Engineering, Product definition, SCAN test bring up, PHY layer, Data Telecommunications, fiber optic chip set, long line repeaters, OC48, OC192,
OC768. Jitter, BERT, VNA, SNA , MM, Sampling Scope, Noise Figure meter, WaveformAnalyzers, Spectrum analyzer, YIG pre selector, Waveguide,
TWT, RF w aveguide, Soto Tech, w afer defect density, strategic planning RF PCB board design, debug, and development vector signal analyzer,
vector signal generator Lab View PCB mixed signal and RF design RF SoC IP including transmitters, DLL PLL pow er amplifiers Mixers filters
ADC/DAC crystal oscillators and PMU. RF system characterization measuring EVM phase noise sensitivity Design of external matc hing netw orks
Smith Charts EMI RF Calibration, Brass Boards test_coverage HAST latch_up, ESD, HBM, CDM, Burn_in, machine model, GUI_code
subversion_code_control, GBIB, Firew ire, Applications_engineering, New_product_development, 1310nm, 1550nm lasers FPGS, Micro Processor
programming, Assembly Language Programming, Full Lab analysis and setupand automations and data collection, Full verification ATE
Engineering and Pre Productiontesting and deployment to full productiontest. SRAM, NVM, DOE, Thermal package Analysis, The rmal die
analysis, Thermal analysis: Package handler test, probe test, burnin. Loadbiard design, burn in board design with protection and
monitoring, HAST boarddesign, Mil-Specand testing, Bell core testspecs. SPC, MMIC Schumberger 5000 Matlab Lab View Test stand,
FMEA, Six Sigma, CPK, CPL, ASIC, CPU, uP, Analod, Digital, Mixed Signal,, ASSEMBLY Language, SPC
DESIGN and Function:
op-amp differential amplifiers, ADC’s, DAC’s, digital interfacing, DSP, DLL PLL, CDR, Laser, Transimpednace Amp, Log Video Amp, transceivers,
Framers, High performance board design (phase, VSWR and frequency layout optimization). Design of Experiments DOE.
Microscopy:
Bright Field, Dark Field, Namarski, Confocal, Nikon photoresist and SiN cap filters, SEM, TEM, Light Emission
BUSINESS KEYS
Product Development, Product Management, Cross-functional Team Leadership, Strategy, Product Market Analysis, Management,
Competitive Analysis, Start-ups, Strategic Partnerships, Go-to-market Strategy, Manufacturing Strategy, Yield Optimization, Profit
Optimization, Manufacturingstrategy, Manufacturing bring up, Testing,Process Improvement, Risk Mitigation, Critical Product Definition
Salesforce.com Model N SAP SAS ENTERPROSE CPQ

6. Major Projects
 AT&T Microelectronics Fiber Optic LONGLINES NPI
manufacturing lead engineer
 AEL Electronic Warfare Defense Electronic module
NPI, ceramic filter design, reliability testing, FA and
deployment to production
 Silicon Labs,worlds first any-rate clock new product
bring up from design to full production deployment
 Teach associate level EE Courses
Education
EDUCATION
AT&T BUSINESS SCHOOL, SOMERSET, NJ
Bachelor Science: ELECTRICAL ENEGINEERING
RETS COLLEGE, NEWTOWN SQUARE, PA
ASSOCIATE OF SCIENCE IN ELECTRONICS
I was invited to teach Engineering Course theory after graduation because I had perfect grades, I accepted the offer and
taught evening division while working at AEL in the day..
EE COURSES at BELL LABS
Radio Frequency, Analog, and Digital test, design and redesign
Process, Statistics, Data Modeling, Quality: AQL, Xbar and R, CPK, 6 Sigma
SOFTWARE
VB, C++, UNIX, PERL, AWK, Matlab, SAS-Enterprise, SQL, Oracle, envision, Image, S, Microsoft Office, Visio etc
PUBLICATIONS
Snowden, Laird R., “Process Control Monitor to Device Data Correlation,” ARFTG Conference Digest-Spring, 45th (Volume
27), 1995
PERFORMANCE AWARDS
AT&T: Key contributor 20,000 stock options, Spot RSU grants, Methodologies returned 250 million dollars.
SILICON LABS: Stock SPOT RSU grants awarded for performance
PROFESSIONAL MEMBERSHIPS
IEEE
Society of Old Crows (Electronic Warfare Society)
SECURITY CLEARANCE: Secret
Security Clearance
Previously held: Confidential and Secret