Digital design chap 3

DIGITAL ELECTRONICS
CHAPTER 3
DEE 204

DIGITAL ELECTRONICS
• Function of combination logic
Conversion of BCD to 7 segment
decoder.
Multiplexer, tri-state output, fan
out, address, half adder, full
adder, comparator.
Logic minimisation and Karnaugh
maps.

FUNCTION OF COMBINATION LOGIC
• BCD to 7 segment decoder
 displays decimal characters 0 to 9
using a 7 segment configuration
 takes a 4-bit BCD input and
provides output by passing current
through it and LED emits light
 Lamp test: to verify that no
segments are burned out
 Zero suppression: blank out
unnecessary zeros in multi-digit
displays

• Circuit for a BCD to 7 segment decoder

• Table of input and output variables of BCD to 7
segment decoder

• Table of input and output variables of BCD to
7 segment decoder

• Multiplexer (MUX)
- also known as data selector
- is a device that allows digital information
from several sources to be routed onto a
single line for transmission over that line to a
common destination
- has several input lines and single output line

• Block diagram for a 1-of-n data
selector/multiplexer

• Multiplexer
For an 8-input MUX
with truth table:
INPUTS OUTPUTS
A2 A1 A0 Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

• Multiplexer
The connection to a 74LS151 IC is as shown:

• Tri-state logic
- normal logic circuits only have two
output states; HIGH and LOW
- in complex digital systems a number of
gate inputs may be required, causing
certain operation problems

Related problems:
 Transistor-transistor-logic (TTL)
totem-pole outputs or CMOS active
pull-up/pull-down outputs can’t be
connected together
 open-collector outputs can be
connected together with common
collector but resistor connected
externally, loading and speed

• Problems solved by
- developing special circuits with one more
output state known as third state or high
impedance state
- usually used as buffer gates
- modification of NAND gate with addition of
diodes D1 and D2 and an inverter gate

• Fan-out
- maximum number of inputs of several gates
that can be driven by the output of a logic
gate
- maximum number of inputs of the same IC
family that the gate can drive maintaining its
output levels within specified limits

• Fan-in
- the number of inputs
- at hardware level, it provides
information about the intrinsic speed of
the gate itself
- increases or decreases the propagation
delay

• Address:
- location in memory
- indicates the positions of instructions
and data in the memory
- starts with the number ‘0’ and up to the
largest address

• Half adder
- adds two bits and produces a sum and carry
output
- accepts two binary digits on inputs and
produces two binary digits on outputs, a sum
bit and a carry bit
Rules of binary addition
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10

• Half-adder
The logic symbol
and logic diagram
for a half-adder:

• Half adder
The truth table for a half adder:

• Full adder
- has an input carry while the half-adder does
not
- accepts two input bits and an input carry and
generates a sum output and an output carry

• Full adder logic symbol

• Full adder logic diagram
( ) inout CBAABC ⊕+=
( ) inCBAS ⊕⊕=

• Full adder truth table

• Comparators
- a special combinational circuit designed
primarily to compare the relative magnitude
of two binary numbers
- for two n-bit numbers A and B as inputs, the
outputs could be either A=B, A<B or A>B
- depending on the relative magnitudes, one
of the outputs will be HIGH

• Comparator
The block diagram
of a n-bit
comparator:

• Comparator
Logic diagram of a one-bit comparator:

• Comparator
Truth table of a one-bit comparator:

• Logic minimization or simplification
 Boolean sum of products (SOP) – when
two or more product terms are summed
by Boolean addition
 Boolean product of sums (POS) – when
two or more sum terms are multiplied
 Karnaugh map

• The sum of products (SOP) form
Example:
ACCBABA
DCBCDEABC
ABCAB
++
++
+

• Example:
Convert Boolean expression to SOP form
( )
( )( )
( ) CBAc
DCBBAb
EFCDBABa
++
+++
++
)
)
)

• Solution
 An SOP expression is ‘1’ if one or more of the product terms
is ‘1’
( )
( )( )
( ) ( ) ( ) CBCACBACBACBAc
BDBCBBADACABDCBBAb
BEFBCDABEFCDBABa
+=+=+=++
+++++=+++
++=++
)
)
)

• The product of sums (POS) form
Example:
( )( )
( )( )( )
( )( )( )CACBABA
DCBEDCCBA
CBABA
++++
++++++
+++

• Example:
Convert Boolean expression to POS form
( )( )( )
( )( )
( )( )
( )( )( )( )( )DCBADCBADCBADCBADCBA
DCBADCBAAADCBDCB
DCBADCBADDCBACBA
DCBADCBCBA
+++++++++++++++
++++++=+++=++
++++++=+++=++
+++++++
asformPOSthegivingthus,
AorAvariablemissingistermsecondthegconsiderin
DorDvariablemissingisfirst termthegconsiderin

• Example:
Simplify or minimize Boolean expression

• Karnaugh map
- a systematic method for simplifying
Boolean expressions
- similar to the truth table presenting all
possible values of input variables and
resulting output of each value

• Karnaugh map

• Karnaugh map
3-variable K-map
0 1
00
01
11
10
C
AB
CBA CBA
CBA BCA
CAB ABC
CBA CBA

• Karnaugh map : 4-variable K-map
00 01 11 10
00
01
11
10
CD
AB
DCBA DCBA
DCBA DCBA
DCAB DCAB
DCBA DCBA
CDBA DCBA
BCDA DBCA
ABCD DABC
CDBA DCBA

• Karnaugh map
Example:
Draw the truth table and Karnaugh map for
ABBAY +=

• Karnaugh map
for the given
expression
0 1
00 1 1
01
11 1
10 1
C
AB
CBACABCBACBA +++

• Map the Karnaugh map for the given expression
111011010100
itin1puttingandexpressiontheevaluating
ABCCABCBACBA +++

• Mapping the
Karnaugh map
for the given
expression
0 1
00 1
01 1
11 1 1
10
C
AB

010110000011101100101100
itin1puttingandexpressiontheevaluating
DCBADCBADCABDCABDCBACDBA +++++

00 01 11 10
00 1 1
01 1
11 1 1
10 1
CD
AB

• Map the Karnaugh map for the given expression
011
010
101001
011100000
CABBAA
iablesoutput varpossibleallgconsiderin
++
++ CABBAA

• Mapping the
Karnaugh map
for the given
expression
0 1
00 1 1
01 1 1
11 1
10 1 1
C
AB

• Deriving
expression from
Karnaugh map
0 1
00
01
11
10
C
AB
CBA CBA
CBA BCA
CAB ABC
CBA CBA

• Deriving
expression from
Karnaugh map
- grouping the 1s
0 1
00 1
01 1
11 1 1
10
C
AB

• Deriving
expression
from
Karnaugh
map
-determining
the Boolean
expression
0 1
00 1
01 1
11 1 1
10
C
AB
CBA
BC
AB

• Deriving the expression from the Karnaugh map
00 01 11 10
00 1 1
01 1 1 1 1
11
10 1 1
CD
AB

• Grouping the 1s in the Karnaugh map
00 01 11 10
00 1 1
01 1 1 1 1
11
10 1 1
CD
AB CA
BA
DBA

Digital design chap 3

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