The document provides an overview of VLSI circuit design, including IC products such as processors, memory chips, and embedded systems, alongside the theoretical foundations of MOS transistors and CMOS inverters. It discusses the processes involved in CMOS fabrication, transistor sizing, and VLSI trends like Moore’s Law, which predicts the doubling of transistor density over time. Additionally, it includes a historical perspective on the evolution of transistors and integrated circuits, along with details of the author's research interests and publications.

1. VLSI Circuit Design

2. IC Products
 Processors
– CPU, DSP, Controllers
 Memory chips
– RAM, ROM, EEPROM
 Analog
– Mobile communication,
audio/video processing
 Programmable
– PLA, FPGA
 Embedded systems
– Used in cars, factories
– Network cards
 System-on-chip (SoC)
Images: amazon.com

3. Content
MOSFET Theory
 MOS transistor theory including Gate-Oxide-Channel structure at different gate
voltages (Accumulation, Depletion, Inversion),
 MOS operating regions at various Gate and Drain voltages (Cut-off, Inversion,
Linear, Saturation),
 threshold voltage and equation at zero substrate bias,
 I-V characteristics (drain current equation),
 C-V characteristics (MOS capacitances),
 Non-ideal I-V effects (2nd order effects).
CMOS inverter
 Basics of CMOS inverter.
 graphical derivation of the DC transfer characteristics,
 inverter operation at various operating regions,
 variation of the transfer characteristics with change in the βn/βp ratio,
 Noise Margin.
 Non-inverting buffers, Tri-state buffers, Tri-state Inverters,

4. Content (cont.)
CMOS Processing
 Basic processes of silicon semiconductor technology including
– wafer processing,
– photolithography,
– oxidation,
– adding impurities through epitaxy,
– deposition,
– ion-implantation and
– diffusion and
– the silicon gate process.
 Major steps (including different masks and corresponding
process cross sections) involved in fabricating a CMOS inverter
(using n-well CMOS processing) will be discussed in detail.

5. Content (cont.)
CMOS gates
 Compound Gates,
 Transistor Sizing,
 Pass Transistors and
 Transmission Gates.
Delay Estimation
 RC delay model & Elmore delay
 Logical Effort

6. VLSI:Very Large Scale Integration
 Integration: Integrated Circuits
– multiple devices on one substrate
 How large is Very Large?
 SSI (small scale integration)
– 7400 series, 10-100 transistors
 MSI (medium scale)
– 74000 series 100-1000
 LSI 1,000-10,000 transistors
 VLSI > 10,000 transistors
 ULSI/SLSI (some disagreement)

7. The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

8. ENIAC - The first electronic computer (1946)
Digital Integrated Circuits © Prentice Hall 1995Introduction

9. Dual port RAM
Full custom
Standard cell
ASIC with mixture of full custom,RAM and standard cells
FIFO
Single port RAM

10. Pentium

11. August 15, 2019204424 Digital Design Automation
11
VLSI Trends: Moore’s Law
 In 1965, Gordon Moore predicted that
transistors would continue to shrink, allowing:
– Doubled transistor density every 18-24 months
– Doubled performance every 18-24 months
 History has proven Moore right
 But, is the end is in sight?
– Physical limitations
– Economic limitations
I’m smiling
because I
was right!
Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com

12. Moore’s Law (cont)
 Intel co-founder Gorden Moore notice in 1964
 Number of transistors doubled every 12 months
while price unchanged
 Slowed down in the 1980s to every 18 months
 Amazingly still correct, likely to keep until 2010.

13. Moore’s Law, Intel’s Version
Transistors
10K
100K
1M
10M
1975 1980 1985 1990 1995
4040 8080
8086 80286
80386
80486
Pentium
Pentium III
1K
2000

14. IC Scales
Integration level Abbreviation Number of devices on a chip
Small Scale Integration SSI 2 to 50
Medium Scale Integration MSI 50 to 5,000
Large Scale Integration LSI 5,000 to 100,000
Very Large Scale Integration VLSI 100,000 to 10,000,000
Ultra Large Scale Integration ULSI 10,000,000 to 1,000,000,000
Super Large Scale Integration SLSI over 1,000,000,000

15. Road Map Semiconductor Industry
1995 1997 1999 2001 2004 2007
Minimum feature size (mm) 0.35 0.25 0.18 0.13 0.10 0.07
DRAM
Bits/chip 64 M 256 M 1 G 4 G 16 G 64 G
Cost/bits @ volume
(millicents) 0.017 0.007 0.003 0.001 0.0005 0.0002
Microprocessor
Transistors/cm2
4 M 7 M 13 M 25 M 50 M 90 M
Cost/Transistor @ volume
(millicents) 1 0.5 0.2 0.1 0.05 0.02
ASIC
Transistors/cm2
2 M 4 M 7 M 13 M 25 M 40 M
Cost/Transistor @ volume
(millicents) 0.3 0.1 0.05 0.03 0.02 0.01
Wafer size (mm) 200 200 200 -
300
300 300 300 –
400 (?)

16. Brief History
 First Transistor, AT&T Bell Lab, 1947
(John Bardeen & Walter Brattain) (Ge)
 First Single Crystal Germanium, 1950
 First Single Crystal Silicon, 1952
 First IC device, TI, 1958 (Jack Kilby)
 First IC product, Fairchild Camera,
1961(Robert Noyce)

17. First Transistor, Bell Lab, 1947
Photo courtesy:
AT&T Archive

18. John Bardeen, William Shockley and Walter Brattain
Photo courtesy: Lucent Technologies Inc.
First Transistor and Its Inventors

19. First IC Device Made by Jack Kilby of Texas
Instrument in 1958
Photo courtesy: Texas Instruments

20. First Silicon IC Chip Made by Robert
Noyce of Fairchild Camera in 1961
Photo courtesy: Fairchild Semiconductor International

21. MOSFET
~10nm
2000年 2015年
圖形取自Texas Instruments

22. IC Design:
CMOS Inverter
Metal 1, AlCu
P-Epi
P-Wafer
N-WellP-Well
PMD
p + p +n +n +
W
Metal 1
Contact
P-well
N-wellPolycide gate and local
interconnection
N-channel active region
N-channel Vt
N-channel LDD
N-channel S/D
P-channel active region
P-channel Vt
P-channel LDD
P-channel S/D
Shallow trench isolation (STI)
Vss
Vdd
NMOS PMOS
Vin
Vout
STI
(a)
(b)
(c)

23. MPU

24. CMOS Chip with
4 Metal Layers
FSG
Metal 4 Copper
Passivation 1, USG
Passivation 2, nitride
Lead-tin
alloy bump
FSG
CopperMetal 2
FSG
FSG
CopperMetal 3
FSG
P-epi
P-wafer
N-wellP-well
n+
STI p+
p+
USGn+
PSG Tungsten
FSG
Cu Cu
Tantalum
barrier layer
Nitride etch
stop layer
Nitride
seal layer
M 1
Tungsten local
Interconnection
Tungsten plug
PMD nitride
barrier layer
T/TiN barrier &
adhesion layer
Tantalum
barrier layer

25. Teacher Profile
https://sites.google.com/site/syedmkbari/Home
 Research Interest:
 Analog, RF, Mixed Signal & Digital circuit and IC design
 Ultra low power circuits
 High frequency electronics
 Background Highlight:
 7 years Experience as Analog IC Design Engineer
 13 Publications, 1 Patent
 Designed ICs:
 LDO Regulator
 Boost Regulator
 LED Driver
 CFL Driver
 PFM Controller.
 Microprocessor Supervisor
 Bandgap Reference

26. Journal Publications
 2. Khondker Zakir Ahmed, Syed Mustafa Khelat Bari, Harun ur Rashid, “Design and Implementation of PFM mode
high efficiency Boost Regulator,” Journal of Analog Integrated Circuits and Signal Processing (4 August 2011), pp. 1-
10. doi: 10.1007/s10470-011-9717-3.
1. Md. Waliullah Khan NOMANI, Syed Mustafa Khelat BARI, Tanwir Zubair ISLAM, Mohammad Nazrul ISLAM,
‘‘Invariant Bangla Character Recognition using a Projection-slice Synthetic-discriminant-function-based Algorithm,”
Istanbul University–Journal of Electrical and Electronic Engineering, Vol. 7 # 2, pp. 403-409, 2007
Selected Conference Publications
 15. Syed Mustafa Khelat Bari, Nur-e-elahi Shonchoy, Farah Tasnuba Kabir, Arif Khan “Design and Performance
Analysis of Ultra Fast CNFET Comparator and CMOS Implementation Comparison” (accepted in UKSim2012 in
Cambridge, UK).
 14. Syed Mustafa Khelat Bari, Subrata Biswas, AKM Arifuzzzaman, Habib Nazir, "A Novel Design and Performance
Analysis of Dynamic Threshold-Voltage CNTFET for High-Speed Multiple Voltage Level Detector" (accepted in
UKSim2012 in Cambridge, UK).
 13. Rakibul Akanda, AKM Arifuzzzaman, Syed Mustafa Khelat Bari, "Designing Quaternary Logic Gates Using
Carbon Nanotube Field Effect Transistor", been accepted for presentation at the 16th IEEE Mediterranean
Electrotechnical Conference (MELECON 2012), to be held in Yasmine Hammamet, Tunisia from 25-28 March 2012.
 12. Ahmed Mortuza Saleque, S.M. Ferdous, Mohd. Sadeed Al Hossain, Taisir Shahid, Syed Mustafa Khelat Bari,
“Characterization and Performance Analysis of a Sensorless Interior Permanent Magnet Synchronous Motor Controlled
by an Artificial Neural Network based Algorithm” in the proceedings of XIII International Conference on Electrical
Machines, Drives and Power Systems, ELMA 2011, October 2011, Varna, Bulgaria, p. 97-108, ISSN 1313-4965.
 11. Syed Mustafa Khelat Bari, Khondker Zakir Ahmed, Didar Islam, "Implementation of Highly Accurate NMOS VTH
Based Clamping Technique in Low Current Comparator" pp. 592-595, Proceedings of IEEE Asia-Pacific Conference on
Circuits and Systems, IEEE APCCAS-2010, on Dec 06-09, 2010, Kuala Lumpur, Malaysia. DOI -
10.1109/APCCAS.2010.5774917

27.  10. Khondker Zakir Ahmed, Mohammad Shahidul Islam, Syed Mustafa Khelat Bari, M. R. R. Mazumder, A.B.M.H. Rashid, "Design
of a linearly increasing inrush current limit circuit for DC-DC boost regulators" pp. 863-866, Proceedings of IEEE Asia-Pacific
Conference on Circuits and Systems, IEEE APCCAS-2010, on Dec 06-09, 2010, Kuala Lumpur, Malaysia. DOI-
10.1109/APCCAS.2010.5774913
 9. Khondker Zakir Ahmed, Syed Mustafa Khelat Bari, Didar Islam, A.B.M. H.Rashid, "Design and Implementation of Ultra Low
Bias Current High Efficiency PFM Mode DC-DC Boost Regulator" pp. 454-457, Proceedings of International conference on
Electrical and Computer Engineering, ICECE 2010, on Dec 18-20, 2010, Dhaka, Bangladesh. DOI- 10.1109/ICELCE.2010.5700727
 8. Syed Mustafa Khelat Bari, Khondker Zakir Ahmed, Mohiuddin Hafiz and A.B.M. H.Rashid “An Improved Method of Highly
Accurate Supply Detection using Bandgap Reference Circuit and Its Implementation in a Pseudo BiCMOS Process” pp. 311-314,
Proceedings of the 5th International Conference on Electrical and Computer Engineering (ICECE 2008), Dec 20-22, 2008.
 7. Khondker Zakir Ahmed, Syed Mustafa Khelat Bari, Moakhkharul Islam, Didar Islam, Mohiuddin Hafiz and Q. D. M. Khosru
“Analysis of efficiency optimization for PFM mode switching DC-DC boost regulator” pp. 195-198, Proceedings of the 5th
International Conference on Electrical and Computer Engineering (ICECE 2008), Dec 20-22, 2008.
 6. Mohiuddin Hafiz, Tania Ansari, Khondker Zakir Ahmed, Syed Jaffry and Syed Mustafa Khelat Bari, “A very low voltage high
duty cycle step-up regulator”, pp. 506-511, Proceedings of the 5th International Conference on Electrical and Computer Engineering
(ICECE 2008), Dec 20-22, 2008.
 5. Khondker Zakir Ahmed, Syed Mustafa Khelat Bari, Didar Islam, “Design and implementation of semi-quadratic slope
compensation circuit for PWM peak current mode Boost regulator”, pp. 512-515, Proceedings of the 5th International Conference on
Electrical and Computer Engineering (ICECE 2008), Dec 20-22, 2008.
 4. Z. Islam, M. W. K. Nomani, S. M. . Bari, M. R. Haider and M. N. Islam, ‘‘Joint power spectrum addition technique for optical
color pattern recognition,’’ in Proc. EUSIPCO 2004, Vienna, Austria, Sept. 2004.
 3. M. W. K. Nomani, T. Z. Islam, S. M. K. Bari, M. R. Haider, and M. N. Islam, “Distortion Invariant Class-associative Target
detection using Projection-slice Synthetic Discriminant Function” in Proc. of 3rd International Conference on Electrical & Computer
Engineering, ICECE2004, December 28-30, pp. 108-111, Dhaka, Bangladesh.
 2. M. W. K. Nomani, S. M. K. Bari, T. Z. Islam, M. R. Haider, and M. N. Islam, ‘‘Gain-adjustable non-linear iscrimination function for
optical pattern recognition,’’ in Proc. ICEECE, December 22-24, 2003, Dhaka, Bangladesh.
 1. S. M. K. Bari, T. Z. Islam, M. W. K. Nomani, M. R. Haider and M. N. Islam, ‘‘Invariant Bangla Character Recognition using a
Projection-slice Synthetic-discriminant-function-based Algorithm,’’ in Proc. NCCPB, February 21, 2004, Dhaka, Bangladesh.