This document provides an introduction to VLSI (Very Large Scale Integration) and the history of transistor scaling. It discusses the following key points in 3 sentences: The document traces the history of integrated circuits from the first transistor in 1958 to modern chips containing billions of transistors. It explains how scaling down transistor sizes has allowed for exponential increases in processing power and memory density over time. The document also introduces different transistor types (bipolar, MOSFET) and scaling techniques (constant field, constant voltage) used to continue shrinking dimensions and improving performance of integrated circuits.

1. • Introduction to vlsi
• Unit-1
Prepared by
S.Vijayakumar, AP/ECE
Ramco Institute of Technology
Academic year
(2018-2019 even sem)

2. VLSI

3. History of VLSI
• In 1958, Jack Kilby built the first integrated
circuit flip-flop with two transistors at Texas
Instruments.
• In 2008, Intel’s Itanium microprocessor
contained more than 2 billion transistors
• and a 16 Gb Flash memory contained more
than 4 billion transistors.

4. • This incredible growth has come from steady
miniaturization of transistors and
improvements in manufacturing processes.
• However, as transistors become smaller, they
also become faster, dissipate less power, and
are cheaper to manufacture

5. • The processing performance once dedicated
to secret government supercomputers is
now available in disposable cellular
telephones.
The memory once needed for an entire
company’s accounting system is now carried by
a teenager in her iPod.

6. • Improvements in integrated circuits have
enabled space exploration, made automobiles
safer and more fuel efficient, revolutionized
the nature of warfare.

7. • In 1947, John Bardeen and Walter Brattain
built the first functioning point contact
transistor at Bell Laboratories,

8. • Ten years later, Jack Kilby at Texas Instruments
realized the potential for miniaturization
if multiple transistors could be built on one
piece of silicon.

9. • The invention of the transistor earned the
Nobel Prize in Physics in 1956 for Bardeen,
Brattain, and their supervisor William
Shockley.
• Kilby received the Nobel Prize in Physics in
2000 for the invention of the integrated
circuit.

10. • Transistors can be viewed as electrically
controlled switches with a control terminal
and two other terminals that are connected or
disconnected depending on the voltage or
current applied to the control.

11. • after inventing the point contact transistor,
Bell Labs developed the bipolar junction
transistor.
• Bipolar transistors were more reliable, less
noisy, and more power-efficient.

12. • Early integrated circuits primarily used bipolar
transistors.
• Bipolar transistors require a small current into
the control (base) terminal to switch much
larger currents between the other two
(emitter and collector) terminals.

13. • The quiescent power dissipated by these base
currents, drawn even when the circuit is not
switching, limits the maximum number of
transistors that can be integrated onto a single
die.

14. • 1960s, Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs) began to enter
production.
• MOSFETs offer the compelling advantage that
they draw almost zero control current while
idle.

15. • two flavors: nMOS and pMOS, using n-type
and p-type silicon, respectively.
• In 1963, Frank Wanlass at Fairchild described
the first logic gates using MOSFETs.
• [Wanlass63]. Fairchild’s gates used both nMOS
and pMOS transistors, earning the name
Complementary Metal Oxide Semiconductor,
or CMOS

16. • The circuits used discrete transistors but
consumed only nanowatts of power, six orders
of magnitude less than their bipolar
counterparts.
• The circuits used discrete transistors but
consumed only nanowatts of power, six orders
of magnitude less than their bipolar
counterparts.

17. • Early commercial processes used only pMOS
transistors and suffered from poor
performance, yield, and reliability.
• Processes using nMOS transistors became
common in the 1970s .

18. • Intel pioneered nMOS technology with its
1101 256-bit static random access memory
and 4004 4-bit microprocessor,

19. • nMOS logic gates still consumed power while
idle.
• Power consumption became a majorissue in
the 1980s as hundreds of thousands of
transistors were integrated onto a single die.
• CMOS processes were widely adopted and
have essentially replaced nMOS and bipolar
processes for nearly all digital logic
applications.

20. • In 1965, Gordon Moore, he found transistor
count doubling every 18 months. This
observation has been called Moore’s Law.
• number of transistors in Intel microprocessors
has doubled every 26 months since the
invention of the 4004.

22. • Moore’s Law is driven primarily by scaling down
the size of transistors and, to a minor extent, by
building larger chips.
• Integration Levels
• SSI: 10 gates
• MSI: 1000 gates
• LSI: 10,000 gates
• VLSI: > 10k gates

23. • Even though an individual CMOS transistor
uses very little energy each time it switches,
the enormous number of transistors switching
at very high rates of speed have made
powerconsumption a major design
consideration again.

24. • Moreover, as transistors have become so
small, they cease to turn completely OFF.
Small amounts of current leaking through
each transistor now lead to significant power
consumption when multiplied by millions or
billions of transistors on a chip.

26. C-V Characteristics
• Each terminal of an MOS transistor has
capacitance to the other terminals. In general,
• these capacitances are nonlinear and voltage
dependent (C-V);
• Simple MOS Capacitance Models
• Detailed MOS Gate Capacitance Model
• Detailed MOS Diffusion Capacitance Model

27. • The gate of an MOS transistor is a good
capacitor.
• Indeed, its capacitance is necessary to attract
charge to invert the channel, so high gate
capacitance is required to obtain high Ids.

28. MoS gate capacitance models
• the gate capacitor can be viewed as a parallel
plate capacitor with the gate on top and
channel on bottom with the thin oxide
dielectric between.
• Therefore, the capacitance is

29. • Most transistors used in logic are of minimum
manufacturable length because this results in
greatest speed and lowest dynamic power
consumption.Thus, taking this minimum L as a
constant for a particular process, we can
define

30. • the gate capacitance has two components:
• the intrinsic capacitance Cgc (over the
channel) and
• the overlap capacitances Cgol (to the source
and drain).

31. Intrinsic gate capacitance
• The intrinsic capacitance was approximated as a
simple parallel plate in with capacitance C0 =
WLCox.
• The intrinsic capacitance has three components
representing the different terminals connected to
the bottom plate:
• Cgb (gate-to-body),
• Cgs(gate-to-source), and
• Cgd (gate-to-drain).

32. • the bottom plate of the capacitor depends on
the mode of operation of the transistor.
• Cutoff:
• When the transistor is OFF (Vgs < Vt), the
channel is not inverted and charge on the gate
is matched with opposite charge from the
body. This is called Cgb, the gate-to-body
capacitance.

33. • For negative Vgs, the transistor is in
accumulation and Cgb =C0.
• As Vgs increases but remains below a
threshold, a depletion region forms at the
surface. This effectively moves the bottom
plate downward from the oxide, reducing
• the capacitance.

34. • Linear.:When Vgs > Vt, the channel inverts
and again serves as a good conductive bottom
plate. However, the channel is connected to
the source and drain, rather than the body, so
Cgb drops to 0.
• At low values of Vds, the channel charge is
roughly shared between source and drain, so
Cgs = Cgd = C0/2.

35. • As Vds increases, the region near the drain
becomes less inverted, so a greater fraction of
the capacitance is attributed to the source and
a smaller fraction to the drain.

36. • Saturation. At Vds > Vdsat, the transistor
saturates and the channel pinches off. At this
point, all the intrinsic capacitance is to the
source.
• Because of pinchoff, the capacitance in
saturation reduces to Cgs = 2/3 C0 for an ideal
transistor

38. Overlap capacitances
• The gate overlaps the source and drain in a
real device and also has fringing fields
terminating on the source and drain. This
leads to additional overlap capacitances.

39. • For the purpose of delay calculation of digital
circuits, we usually approximate
• Cg = Cgs + Cgd + Cgb
• = C0 + 2CgolW

40. Detailed MOS Diffusion Capacitance
Model
• In addition to the gate, the source and drain
also have capacitances.
• These capacitances are not fundamental to
operation of the devices, but do impact circuit
performanceand hence are called parasitic
capacitors.

41. • The source and drain capacitances arise from
the p–n junctions between the source or drain
diffusion and the body and hence are also
called diffusion capacitance Csb and Cdb .
• The capacitance depends on both the area AS
and sidewall perimeter PS of the source
diffusion region.

42. • The total source parasitic capacitance is
where Cjbs (the capacitance of the junction between the body and
the bottom of the source has units of capacitance/area)
Cjbssw (the capacitance of the junction
between the body and the side walls of the source) has units of
capacitance/length

43. • CJ is the junction capacitance at zero bias and
is highly process-dependent. MJ is the
junction grading coefficient,
• is the built-in potential that depends on
doping levels.

44. • The sidewall capacitance term is of a similar
form but uses different coefficients.

46. • In this course you will learn the following
•Motivation for Scaling
• Types of Scaling
Why scaling?
shrinking device dimensions to increase
transistor density & operating frequency and
reduction in power dissipation & gate delays.

47. Motivation for Scaling
• The reduction of the dimensions of a MOSFET
has been dramatic during the last three
decades.
• Starting at a minimum feature length of 10
mm in 1970 the gate length was gradually
reduced to 0.15 mm minimum feature size in
2000, resulting in a 13% reduction per year.

49. • Proper scaling of MOSFET however requires
not only a size reduction of the gate length
and width but also requires a reduction of all
other dimensions including the gate/source
and gate/drain alignment, the oxide thickness
and the depletion layer widths.
• Scaling of the depletion layer widths also
implies scaling of the substrate doping density.

50. Types of Scaling
• Two types of scaling are common:
• 1) constant field scaling
• 2) constant voltage scaling.
• 3. General scaling

51. • Three different models.
• all device dimensions scale by the same factor
S (with S > 1 for a reduction in size).
• This includes the width and length of the
transistor, the oxide thickness, and the
junction depths.
• Similarly, we assume that all voltages,
including the supply voltage and the threshold
voltages, scale by a same ratio U.

52. Constant field scaling
• Voltages and dimensions are scaled by the same
factor S.
• Keeping the electrical fields constant ensures the
physical integrity of the device and avoids
breakdown or other secondary effects.
• This scaling leads to greater device density(Area),
higher performance (Intrinsic Delay), and reduced
power consumption (P).
• However, it requires a reduction in the power
supply voltage as one decreases the minimum
feature size.

53. Constant voltage scaling
• Only dimensions are scaled and voltages is
kept constant.
• It is good till 0.8 um.
• Disadvantages:
the electric field increases as the minimum
feature length is reduced. This leads to velocity
saturation, mobility degradation, increased
leakage currents and lower breakdown voltages.

54. Two problems in scaling
• Some of the intrinsic device voltages such as
the silicon bandgap and the built-injunction
potential, are material parameters and cannot
be scaled.
• • The scaling potential of the transistor
threshold voltage is limited. Making the
threshold too low makes it difficult to turn off
the device completely.

55. General scaling
• Dimensions and voltages of the devices are
scaled independently.