This document describes the design of a digital phase locked loop (DPLL) circuit. It includes specifications for operating frequency ranges from 100MHz to 1GHz, block diagrams of the major components, schematics and test benches of the phase detector, charge pump, loop filter, voltage controlled oscillator (VCO), frequency dividers, and multiplexer. Simulation results show the DPLL locking at output frequencies of 1GHz, 900MHz and 800MHz for different control voltages and component values. The team contributions and challenges in designing and simulating the full DPLL are also noted.

1. DIGITAL PHASE LOCKED LOOP
E E-524 DIGITAL VLSI LABORATORY
SAM VIVIN RAJ KRISHAN
HIMAKAR REDDY GADDAM
NARENDRA NAIDU LINGUTLA
December 12 , 2014

2. OUTLINE
 Introduction
 Specifications
 Design
 Schematics of Major Blocks
 Test Benches of Major Blocks
 Schematic and Test Bench of DPLL
 Challenges

3. INTRODUCTION
Digital Phase Locked Loop:
 Multiply Clock Frequency
 Clock Synchronization
 Less stable than DLL(2nd order)
Applications:
 Telecommunications
 Clock synchronization and multiplication in Micro processors
 Clock generation

4. SPECIFICATIONS
Name Value
Process SS, TT, FF
Supply 1.6V -1.98V
Temperature -40 C – 127 C
Input frequency 100 MHz
Output Frequency 1 GHz, 900MHz , 800MHz
Load 10 pF
SPECIFICATIONS

5. BLOCK DIAGRAM OF PHASE LOCKED LOOP
PHASE
DETECTOR
LOOP
FILTER
DIVIDE BY 10
Fout
Feedback
Signal(Fout/N)
Finput
PUSH
PULL
VCO
UP
Down
Ipd
Vcntrl Vout
CLOCK
BUFFER
DIVIDE BY 8
DIVIDE BY 9
4X1 MUX

6. TEAM CONTRIBUTION
Schematics & Simulation :
 Phase Detector , Push-Pull Charge Pump – Himakar Gaddam
 Loop filter ,Voltage Control Oscillator , Clock Buffer - Sam Vivin Raj
 Frequency Divider , Multiplexer - Narendra Naidu
Overall Simulation and test bench – Sam , Himakar , Narendra

7. DPLL – DESIGN CALCULATIONS
 fin = 100MHz; fout = 1GHz; Supply Voltage = 1.62V; Process - SS
 Loop Bandwidth – ωn
ωn = ωin/50 = 2πfin/50 = 12.57Mrad/sec
Damping Factor – ζ
 C = 10pF, C2 = C/10 = 1pF
 ζ = 1.25 (Slightly over damped, almost critically damped)
 ζ = 0.5ωnRC
 R = ζ/(0.5ωnC)
 R = 19.9KΩ (in loop filter)

8. Contd..
For 5 stage VCO;
Vin = Vctrl =(1.62 + 0.47) / 2 = 1.045V
N = 5, VDD = 1.62V, Vth = 0.47V
ID = 52.97 μA
R = 10.86kΩ;
Kvco = 475Mhz/V ( from the simulation)
6C = 6.54fF;

9. Contd..
where N = 10 =
Icp = 33.26μA
Rlarge =34.57Ω

10. MAJOR BLOCKS SCHEMATIC, TESTBENCH
AND SIMULATIONS

11. PHASE DETECTOR
Desired Parameters:
fin = 100MHz;
fout = 1GHz; fout/10 = 100MHz
fout = 900MHz; fout/9 = 100MHz
fout = 800MHz; fout/8 = 100MHz
During testing
• fclkA = 100MHz
• fclkb = 95MHz

12. PHASE DETECTOR
SCHEMATIC:

13. PHASE DETECTOR
TEST BENCH:
load

14. PHASE DETECTOR
SIMULATION RESULTS:
Fin=100MHz
Fout =95MHz
UP
DOWN

15. Push – Pull Charge pump
Desired parameters :
 For 5 stage VCO;
Kvco = 475MHz/V
 Push pull charge pump
Icp = 33.26μA
Rlarge = 34.57kΩ

16. PUSH-PULL CHARGE PUMP
SCHEMATIC:
Rlarge = 34.57K ohms
Rlarge
UP BAR
DOWN

17. PUSH-PULL CHARGE PUMP
TEST BENCH:
UPBAR
DOWN
Load
UP BAR
DOWN
Load

18. PUSH-PULL CHARGE PUMP
SIMULATION RESULTS:
Ipd
UPBAR
DOWN
Icp
DOWN
UP
Vcntl

19. Vcntl = 1.045V

20. Loop Filter
Desired Parameters :
 Capacitance(C) = 10pF, C2 = 1pF
 Loop Bandwidth – ωn
ωn = 12.57Mrad/sec
 Damping Factor – ζ
ζ = 1.25 (Slightly over damped, almost critically
damped)
R = 19.9kΩ

21. LOOP FILTER SCHEMATIC

22. Voltage Controlled Oscillator(VCO)
Desired Parameters :
For 5 stage VCO;
Vin = Vctrl =(1.62 + 0.47) / 2 = 1.045V
N = 5, VDD = 1.62V, Vth = 0.47V
ID = 52.97 μA
R = 10.86kΩ;
Kvco = 475Mhz/V
6C = 6.54fF;

23. VOLTAGE-CONTROLLED OSCILLATOR
SCHEMATIC:
R = 6.39K ohms
Vcntrl = 1.045 V
VDD = 1.62V ; VSS = 0

24. VOLTAGE CONTROL OSCILLATOR
TEST BENCH:

25. VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:
Freq = 1GHz

26. VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:
Kvco = 475Mhz/V

27. VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:
Freq = 900MHzR = 8.62K ohms
Vcntrl = 1.045 V
VDD = 1.62V ; VSS = 0

28. VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:
Kvco = 596Mhz/V

29. VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:
R = 11.17K ohms
Vcntrl = 1.045 V
VDD = 1.62V ; VSS = 0
Freq = 800MHz

30. Kvco = 663Mhz/V
VOLTAGE CONTROL OSCILLATOR
SIMULATION RESULTS:

31. CLOCK BUFFER
Design:
H=Cout / Cin = 10pF/3.27fF = 3058.1
G = 1, B = 1
F = GBH = 1*1*3058.1 = 3058.1. Taking ρ= 4;
N = Log43058 = 5.789
N = 6 stages
= 3.81

32. CLOCK BUFFER TEST BENCH
SCHEMATIC:

33. Clock Buffer Test Bench
Test bench:

34. CLOCK BUFFER TEST BENCH
SIMULATION RESULTS:
IN

35. Frequency Divider
Design :
 Divide by 10,9,8
 Components used:
XOR Gate , Nor2x1 , Nand2x1
Flip – Flops
AND Gate

36. DIVIDE BY 10 CIRCUIT
SCHEMATIC:

37. DIVIDE BY 10 CIRCUIT
TEST BENCH:

38. DIVIDE BY 10 CIRCUIT
SIMULATION RESULT:

39. DIVIDE BY 9 CIRCUIT
SCHEMATIC:

40. DIVIDE BY 9 CIRCUIT
TEST BENCH:

41. DIVIDE BY 9 CIRCUIT
SIMULATION RESULT:

42. DIVIDE BY 8 CIRCUIT
SCHEMATIC:

43. DIVIDE BY 8 CIRCUIT
TEST BENCH:

44. DIVIDE BY 8 CIRCUIT
SIMULATION RESULT:

45. 4X1 MULTIPLEXER :
SCHEMATIC :

46. 4X1 MULTIPLEXER :
TESTBENCH :

47. 4X1 MULTIPLEXER :
WAVEFORM 1 : S0 = 1; S1 = 0
Y = D1 = In2

48. 4X1 MULTIPLEXER :
WAVEFORM 2 :
S0 = 0; S1 = 1
Y = D2 = In3

49. 4X1 MULTIPLEXER :
WAVEFORM 3 :
S0 = 0; S1 = 0
Y = D0 = In1

50. SIMULATION OF ENTIRE PROJECT

51. DIGITAL PHASE LOCKED LOOP
SCHEMATIC:

52. DIGITAL PHASE LOCKED LOOP
TEST BENCH: Load = 10pF

53. DIGITAL PHASE LOCKED LOOP IN LOCK
SIMULATIONS: Freq = 1GHz
Process corner –> SS; VDD –> 1.62; T = 125C

54. DIGITAL PHASE LOCKED LOOP IN LOCK
SIMULATIONS: Freq = 1GHz
Process corner –> tt; VDD –> 1.8; T = 27C

55. DIGITAL PHASE LOCKED LOOP IN LOCK
SIMULATIONS:
Freq = 900MHz
Process corner – SS; VDD – 1.62; T = 125C

56. DIGITAL PHASE LOCKED LOOP IN LOCK
SIMULATIONS: Freq = 800Hz
Process corner –> SS; VDD –> 1.62; T = 125C

57. Results
Fout = 1GHz Fout = 900Mhz Fout = 800Mhz
Vcntl 1.045 1.045 1.045
Frequency divider N = 10 N = 9 N =8
Icp 33.26μA 23.85μA 19.1μA
Rlarge 34.57Kohm 48.21Kohm 60.20Kohm
R at VCO 6.39Kohm 8.62Kohm 11.17Kohm
At Process Corner – SS ; VDD – 1.62 ; T = 125’C

58. CHALLENGES
 Adjusting R in VCO to get the required Frequency
 Frequency dividers for divide by 9,10 circuits

59. Thank you