3. INTRODUCTION
Digital Phase Locked Loop:
Multiply Clock Frequency
Clock Synchronization
Less stable than DLL(2nd order)
Applications:
Telecommunications
Clock synchronization and multiplication in Micro processors
Clock generation
4. SPECIFICATIONS
Name Value
Process SS, TT, FF
Supply 1.6V -1.98V
Temperature -40 C – 127 C
Input frequency 100 MHz
Output Frequency 1 GHz, 900MHz , 800MHz
Load 10 pF
SPECIFICATIONS
5. BLOCK DIAGRAM OF PHASE LOCKED LOOP
PHASE
DETECTOR
LOOP
FILTER
DIVIDE BY 10
Fout
Feedback
Signal(Fout/N)
Finput
PUSH
PULL
VCO
UP
Down
Ipd
Vcntrl Vout
CLOCK
BUFFER
DIVIDE BY 8
DIVIDE BY 9
4X1 MUX
6. TEAM CONTRIBUTION
Schematics & Simulation :
Phase Detector , Push-Pull Charge Pump – Himakar Gaddam
Loop filter ,Voltage Control Oscillator , Clock Buffer - Sam Vivin Raj
Frequency Divider , Multiplexer - Narendra Naidu
Overall Simulation and test bench – Sam , Himakar , Narendra
7. DPLL – DESIGN CALCULATIONS
fin = 100MHz; fout = 1GHz; Supply Voltage = 1.62V; Process - SS
Loop Bandwidth – ωn
ωn = ωin/50 = 2πfin/50 = 12.57Mrad/sec
Damping Factor – ζ
C = 10pF, C2 = C/10 = 1pF
ζ = 1.25 (Slightly over damped, almost critically damped)
ζ = 0.5ωnRC
R = ζ/(0.5ωnC)
R = 19.9KΩ (in loop filter)
8. Contd..
For 5 stage VCO;
Vin = Vctrl =(1.62 + 0.47) / 2 = 1.045V
N = 5, VDD = 1.62V, Vth = 0.47V
ID = 52.97 μA
R = 10.86kΩ;
Kvco = 475Mhz/V ( from the simulation)
6C = 6.54fF;