Real 2nd order LC PLL loop analysis.pptx

LC PLL loop analysis
For both USB3 & DP
Sai Goutham Sunkara

Block Diagram
Pre-
Scaler
(DIVR)
vosc
up/dn
vregref
PFD
refclk_xtal
txclk{n/p}
LC
Tank
refclk_fll
rclk<1>
CP/LF
Amplitude
Detect
Lock
Detect
vreglcpll
SD Mod
SSC Gen
Postdiv
(DIVP)
hsref_out{n/p}
REG
vregdig
Amplitude
Control
Engine
Auto
Freq
Detect
Freq.
Control
Engine
Synthsized/P&R Block
Bias
Gen
Analog
Test
Mux
vreg_0p8
Cntrl/Config
Registers
Timing
Interface
Scan
Interface
rclk<0>
hsref_in
CML2CMOS
DIV2
Override
Registers
External Bring-Up
Engine
HSREF
DIV
(DIVH)
REG REG
REFCK
SEL
Feedback
Divider
(FBDIV)

Simulation Matrix
Name Corners Testbench/
Analysis
Sweep
Variables
Description
Stability SS/TT/FF Matlab Icp
Fref
Kvco
Using linear phase model of PLL, measure loop bandwidth,
phase margin and peaking over various combinations of PLL
parameters and reference clock frequencies
Phase Step,
Model
SS/TT/FF Matlab Icp
Kvco
Using linear phase model of PLL, examine phase step
response
Phase Step,
Spectre
SS/TT/FF Spectre Icp
Kvco
Using Verilog-A models of PLL blocks, repeat phase step
response
Refclk_Noise SS/TT/FF Matlab Icp
Fref
Kvco
Using linear phase model of PLL, examine reference clock
noise transfer function. Apply Golden PLL to measure TX
clock jitter
VCO_Noise SS/TT/FF Matlab Icp
Fref
Kvco
Using linear phase model of PLL, examine VCO noise transfer
function. Apply Golden PLL to measure TX clock jitter
Frac-N BCS/TT/WCS AMS Icp
Kvco
Jitter resulting from non-integer feedback divider ratio.
Charge Pump
Up/Down
Mismatch
BCS/TT/WCS AMS Icp
Kvco
Jitter resulting from worst case mismatch between Up and
Down currents
Jitter Budget SS/TT/FF Excel Summary of all PLL jitter sources

Linear PLL Phase
Domain Model
• The linearized PLL model shown above is used to model
the various transfer functions (Reference Clock and VCO
Noise) as well as the PLL’s loop responses.
Kpd Kcp
Kvco
s
1
N
fn_vco
frefclk fout
HLF(s)
fn_ref

Use Cases
• Our primary use case is with a 480 MHz reference clock input, generating a 5 GHz clock with added spread-
spectrum modulation (SSC).
• Both the non-integer feedback divider ratio and SSC imply a fractional-N PLL, which we implement using a
sigma-delta modulator to alternate the (integer) feedback divider value every reference clock cycle.
• The sigma-delta modulator can not operate at quite fast enough to work at 480 MHz, so a reference clock
divider will implement a divide-by-two before the PLL and we will work with a 240 MHz reference clock.
• The other reference clock present on the chip is a 24 MHz clock from the crystal oscillator.
• Again, the non-integer feedback divider ratio and SSC imply a fractional-N PLL.
• The high feedback divider value lowers the open-loop gain which means we need to have a very high charge-
pump current to compensate.
• As we will show below, the large charge-pump current and fractional-N operation makes for a very
difficult/impossible loop filter design within our area budget. Therefore, do not recommend this mode of
operation.

Use Cases
(Cont)
• The final use case is to use the PLL as a clean-up
PLL to take the 24 MHz reference clock and scale it
up in frequency.
• The PLL does not need to run at 5 GHz but
rather at any convenient frequency.
• SSC may be added in the subsequent TX PLL
and is not needed here.
• If operated in integer mode, the lower
reference clock frequency presents much less
of a design constraint on the loop filter.
• Suggested frequency of operation is 4.8 GHz to
allow integer mode operation.

Use Case Configuration
• After all of analysis that is shown in the slides below, here are the final simulation settings for the various use cases
Use Case Fref Fvco Icp R1 C2 Mode
1 (USB3.2) 240 MHz 5 GHz 13.88 uA 10 kW 5.32 pf Fractional
2 (PLL) 24 MHz 4.8 GHz 13.88 uA 25 kW 7.98 pf Integer
3 (DP) 240 MHz 5.4 GHz 13.88 uA 10 kW 5.32 pf Fractional
4 (DP) 240 MHz 4.05 GHz 13.88 uA 15 kW 2.66 pf Fractional
Desired but
not feasible
24 MHz 5 GHz

Loop Filter Equations, FREF – 240MHz
• Many sources for these equations, most of the following is taken from “Practical Phase-Locked Loop Design” by Dennis Fischette,
ISSCC Tutorial 2004 unless otherwise noted.
• wn = Undamped Natural Frequency =
𝐾𝑣𝑐𝑜∗𝐾𝑐𝑝∗𝐼𝑐𝑝
𝑁∗𝐶1
• Where
• Kvco = VCO Gain (rad/V-s)
• Kcp = Phase Detector Gain (rad-1)
• Icp = Charge Pump Current (A)
• N = Feedback Divider Ratio
• C1 = Loop Filter Capacitor (the big one)

Loop Filter Equations, C1, FREF – 240MHz
• We have three use cases and programmability on the charge pump current.
• Kcp = 1/2p
• Icp[1] = m*6.94uA, where m=1 to 15, with an accuracy of around +/-20%
• Fref = 480 MHz, 240 MHz or 24 MHz
• N ~ 10.42, 20.83 or 208.3
• Kvco = 2.51 to 6.91 Grad/V-Sec (nominal 4.71 Grad/V-Sec +/- 47%)
• Capacitor and Resistor variation is +/-20%
• Introducing the ‘damping factor’ term, ζ (zeta) which gives us a measure of loop stability and peaking. Note that all of these equations ignore the impact of C2.
• ζ usually has a range of 0.45 to 1.5, we will target a value of 1.0 (critical damped) at the worst case combination of Icp, Kvco and C1
• ζ = 𝜔𝑛/(2𝜔𝑧)[2]
• To have ζ =1.0 worst case, we need to target ζ =1.2*sqrt(1.47*1.2)=1.59 with nominal values, but this is a bit too high for the opposite PVT corner
• We will target ζ =1.27 at nominal, leading to a bit over-damped system on average but not too under-damped at extreme corners.

Loop Filter
Equations, C1,
FREF – 240MHz
• The relationship between the natural
frequency, crossover frequency and zero
frequency can be approximated by
• 𝜔𝑐~𝜔𝑛
2
/𝜔𝑧
[1]
• And from the previous slide
• ζ = 𝜔𝑛/(2𝜔𝑧) = 1.27, solving for 𝜔𝑧
• 𝜔𝑧 = 𝜔𝑛/2.54
• For our primary use case of fref=240 MHz,
fvco=5GHz we will target 𝜔𝑐=2*p*0.8MHz
which gives us 𝜔𝑛 = 2*p*0.8MHz /2.54 =
1.98 Mrad/sec
• Plugging this back into and solving for C1
• wn = Undamped Natural Frequency =
𝐾𝑣𝑐𝑜∗𝐾𝑐𝑝∗𝐼𝑐𝑝
𝑁∗𝐶1

Loop Filter Equations, C1 (Cont), FREF – 240MHz
• (From Previous Page)
Fref N Kvco Icp C1
240 MHz 20.83 4.71 Grad/V-S 13.88 uA 128 pf
› For the use case where Fref=24 MHz and Fvco = 4.8 GHz but keeping C1=128 pf
we make the following changes
– Reduce Target Bandwidth to 0.26 MHz
– We are tempted to increase Icp to maintain bandwidth, and some tradeoffs may
be made, but when we size C2 (see below) we see some limitations.

Loop Filter Equations, R1, , FREF – 240MHz
• For our primary use case we have C1=128 pf, we can solve for the zero location
• 𝜔𝑛 = 1.98 Mrad/sec
• 𝜔𝑧 = 𝜔𝑛/2.57 = 0.78 Mrad/sec = 1/(R1*C1)
• Solving for R1 we get R1=10.1 kW
• For the Fref=24 MHz/Fvco=4.8 GHz case, the reduced bandwidth target increases
R1=31.4 kW
• Note that for additional flexibility at different reference clock rates and VCO frequencies,
we have made R1 programmable ranging from 5.0 to 40.0 kohms

Loop Filter
Equations,
Solving for
C2, Fref 24
MHz
• Using some rough estimates, for a 24 MHz reference clock and the feedback divider is
toggling in the range of 206 to 210 (with an average of 208.3).
• Tref = 41667 ps
• Tfb_206 = 41200 ps
• Terr = 467ps
• Let’s bound the VCO drift to 1ps over a reference clock cycle, so the worst case
• Df = 5GHz – (1/(200ps + 1ps/208.3) ) = 120 kHz
• Then solving C2 from the eq. (Kvco[1] = 0.75 GHz/V, Icp = 104 uA)
• ∆𝐹𝑣𝑐𝑜 = 𝐾𝑣𝑐𝑜 ∗ 𝐼𝑐𝑝 ∗
𝑇𝑒𝑟𝑟
𝐶2
• C2 = 282 pf!
• Therefore, using a 24 MHz reference clock with a fractional-N divider is not an option.
• [1] – Note that KVCO is in GHz/V here since we’re dealing with sec-1 rather than radians/sec

Loop Filter Equations, Solving for C2, Fref 24 MHz
• Now let’s say we have a 240 MHz reference clock and the (fractional) feedback divider is
toggling between 18 and 23 (with an average of 20.83).
• Tref = 4166 ps
• Tfb_23 = 4600 ps, Tfb_18 = 3600ps
• Terr_wcs = 566 ps
• Let’s bound the VCO drift to 1ps over a reference clock cycle, so the maximum frequency
delta is:
• Df = 5GHz – (1/(200ps + 1ps/20.83) ) = 1.2 MHz
• Then solving C2 from the equation (Kvco = 0.75 GHz/V, Icp = 13.88 uA)
𝑇𝑒𝑟𝑟
𝐶2
• C2 ~ 5.0 pf
• Now that is a reasonable value

Loop Filter Equations, Solving for C2, Integer Mode
• Now let’s say we have a 24 MHz reference clock with a 4.8 GHz VCO frequency (Integer Mode, Div-
By-200)
• Terr is now based on the PFD reset time (minimum up/down pulse widths)
• Terr_wcs = 150 ps
• Let’s bound the VCO drift to 1ps over a reference clock cycle, so the maximum frequency delta is:
• Df = 4.8GHz – (1/(208.3ps + 1ps/200) ) = 115 kHz
• Then solving C2 from the equation (Kvco = 0.75 GHz/V, Icp = 13.88 uA)
𝑇𝑒𝑟𝑟
𝐶2
• C2 = 13.6 pf
• This is a bit large, we will target a maximum of C2=10.6 pf and accept slightly higher frequency
drift.

Finer Optimization
• We have three controls (Icp, C2 and R1) that we can configure for optimum
performance for the various configurations.
• We want to target our performance as follows:
• Loop Bandwidth between 0.4 and 1.0 MHz (Nominal)
• Fractional-N T_Drift < 1ps (Nominal)
• Minimize Closed Loop Peaking Response (over PVT)
• Minimize VCO Noise Peaking Response (over PVT)
• Keep total area ‘reasonable’ (C1 < 160pf)
• Keep C2/C1 ‘reasonable’ (C2 < 10.6pf)

Optimization Results
Design, Nominal WCS Results over PVT
Icp R1 C1 C2 Phase
Margin
CL
Peak
VCO
Peak
T_Drift BW
6.94 uA 15.6 kW 160 pf 2.60 pf 66.1 deg 1.95 dB 1.95 dB 1ps 0.79 MHz
13.88 uA 10.1 kW 160 pf 3.79 pf 62.2 deg 2.25 dB 2.25 dB 1.38 ps 1.07 MHz
› Fref=240 MHz, Fvco = 5.0 GHz
› Fref=24 MHz, Fvco = 4.8 GHz (Integer Mode, Target T_Drift < 2ps)
Icp R1 C1 C2 Phase
Margin
CL
Peak
VCO
Peak
T_Drift BW

18
Optimization Results
Icp R1 C1 C2 Phase
Margin
Close-Loop
Peak
VCO
Peak
T_Drift BW
6.94 uA 13.4 kW 160 pf 2.98 pf 64.3 deg 2.02 dB 2.07 dB 1 ps 0.85 MHz
› Fref=240 MHz, Fvco = 5.4 GHz (DP Mode, KVCO=1 GHz/V)
› Fref=240 MHz, Fvco = 4.05 GHz (DP Mode, KVCO=0.35 GHz/V)
Icp R1 C1 C2 Phase
Margin
Close-Loop
Peak
VCO
Peak
T_Drift BW

Copyright © Infineon Technologies AG 2021. All rights reserved. 19
Loop Filter Design
2021-03-05 restricted
• We will control the R1 value with lf_rtune<2:0> control bits and the
C2 value with lf_ctune<1:0> control bits
lf_rtune R1
000 5.0 kW
001 10.0 kW
010 15.0 kW
011 20.0 kW
100 25.0 kW
101 30.0 kW
110 35.0 kW
111 40.0 kW
lf_ctune C2
00 2.66 pf
01 5.32 pf
10 7.94 pf
11 10.64 pf

21
Linear Equation Loop Dynamics, Primary Mode
• The linear model has the following parameters and PVT
variations
• Fref = 240 MHz
• Fvco = 5.0 GHz
• R1 = 10.0 kW +/-20%
• C1 = 160 pf +/-20%
• C2 = 5.32 pf +/-20%
• KVCO = 0.75 GHz/V +/-47%
• ICP = 13.88 uA +/-20%
• (Note, Current is 1/R based and will track resistor variation to within +/-
10% beyond appropriate resistor skew)

22
Matlab Results, Linear Model, Primary Use Case
• Fref = 240 MHz, Fvco = 5 GHz, Nominal Conditions

23
Matlab Results, Linear Model, Primary Use Case (Cont)

24
Matlab Results, Linear Model, Primary Use Case over PVT
• Worst Case VCO Noise Peaking and
Worst Case Phase Margin
• R => +20%
• C => +20%
• KVCO => +47%
• ICP => +10%

25
Matlab Results, Linear Model, Primary Use Case over PVT
• Worst Case Closed Loop Peaking
• R => -20%
• C => -20%
• KVCO => -47%
• ICP => -10%

26
Linear Equation Loop Dynamics, Secondary Mode
• The linear model has the following parameters and PVT
variations
• Fref = 24 MHz
• Fvco = 4.8 GHz
• R1 = 25 kW +/-20%
• C1 = 160 pf +/-20%
• C2 = 7.98 pf +/-20%
• KVCO = 0.75 GHz/V +/-47%
• ICP = 13.88 uA +/-20%
• (Note, Current is 1/R based and will track resistor variation to within +/-
10% beyond appropriate resistor skew)

27
Matlab Results, Linear Model, Secondary Use Case
• Fref = 24 MHz, Fvco = 4.8 GHz, Nominal Conditions

28
Matlab Results, Linear Model, Secondary Use Case (Cont)

29
Matlab Results, Linear Model, secondary Use Case over PV
• Worst Case Closed Loop Peaking and
Worst Case Phase Margin
• R => -20%
• C => -20%
• KVCO => -47%
• ICP => -10%

30
Matlab Results, Linear Model, secondary Use Case over
PVT
• Worst Case VCO Noise Peaking
• R => +20%
• C => +20%
• KVCO => +47%
• ICP => +10%

31
Matlab Results, Linear Model, 4.05 GHz (DisplayPort)
• Fref = 240 MHz, Fvco = 4.05 GHz
• Kvco = 0.3 GHz/V, Icp = 13.88 uA, C2 = 2.66 pf, R1 = 15 kW
• Worst Case Phase Margin = 64.5 deg
• Worst Case Closed Loop Peaking = 2.08 dB
• Worst Case VCO Noise Peaking = 1.86 dB

32
Matlab Results, Linear Model, 5.4 GHz (DisplayPort)
• Fref = 240 MHz, Fvco = 5.4 GHz
• Kvco = 1.0 GHz/V, Icp = 13.88 uA, C2 = 5.32 pf, R1 = 10 kW
• Worst Case Phase Margin = 52.2 deg
• Worst Case Closed Loop Peaking = 2.03 dB
• Worst Case VCO Noise Peaking = 3.22 dB

33
Verilog-A Models for Loop Simulations
• These blocks have Verilog-A Behavioral models and they model the
following block parameters:
• Charge-Pump:
• cfgrcp<3:0> bits – Bias gain/tweak bits
• mcp<3:0> bits – Output current gain
• up/down mismatch
• PFD:
• pfddelay<3:0> bits – Minimum pulse width setting
• VCO:
• kvco
• capsel<6:0> bits – Coarse Freq. tuning
• itailsel<3:0> bits – Amplitude control
• vctl – VCO Control voltage
• Sigma-Delta
• Second Order, may be disabled in integer mode

34
Loop Simulations for Fractional-N Noise, Primary Mode
• Simulations are done with a second-order sigma-delta modulator implementing a Fractional Divide
Ratio of Fvco/Fref (20.8333 for primary case)
• Divider ranges from 19 to 22
• Divider updates every reference clock edge (240 MHz).
• Fref = 240 MHz, Fvco = 5.0 GHz, Icp = 13.88 uA, R1 = 10.0 kW, C2=5.32 pf

35
Loop Simulations for Fractional-N Noise, Primary Mode
• WCS Jitter = 0.982ps_pp: Icp+20%, KVCO+47%, SS_LowR Corner

36
Spectre/Verilog-A Charge-Pump Mismatch Simulation
• Not significant in Primary Use Case (dominated by Frac-N), Use Secondary Case
• Mismatch between Up/Down currents is swept between -15% to +15%, higher
than block level simulations indicated
• Simulated jitter is roughly the minimum timestep (maxstep=100fs) Worst case
simulation results was actually at typical corner with no mismatch (abs_jitter =
124fs).
• We will use this value for the spreadsheet, but in actuality the performance is better.

37
PLL Jitter Budget
• From Input Reference Clock to TX CML Output Clock. Sources Include:
• Reference Clock Phase Noise (USB2-PLL)
• Reference Clock Select Power-Supply Noise
• Reference Clock Divider Power-Supply Noise
• LC-Tank Thermal and 1/f noise
• LC-Tank Power Supply Noise
• Charge-Pump Up/Down Mismatch
• Fractional-N T-Drift Jitter
• CML2CMOS Power Supply Noise
• Output Divider/CML Driver (DIVP) Power Supply Noise

38
PLL Jitter Budget (Summary)
Budget Simulation Results
Typical Worst-Case
DJ RJ TJ DJ RJ TJ DJ RJ TJ
Jitter Source ps_pp ps_rms ps_pp ps_pp ps_rms ps_pp ps_pp ps_rms ps_pp
Reference Clock Phase Noise (USB2-PLL) 0.35 4.94 0.10 1.45 0.21 2.90
Reference Clock Select PS Noise 0.50 0.50 0.08 0.08 0.52 0.52
Reference Clock Divider PS Noise 0.50 0.50 0.33 0.33 0.57 0.57
LC-Tank Thermal and 1/f noise 0.15 2.12 0.07 1.02 0.07 1.04
LC-Tank PS Noise 1.50 1.50 0.47 0.47 1.02 1.02
Charge-Pump Up/Down Mismatch 0.50 0.50 0.12 0.12 0.12 0.12
Fractional-Mode Delta-f 1.50 1.50 0.49 0.49 0.98 0.98
CML2CMOS PS Noise 0.50 0.50 0.11 0.11 0.34 0.34
DIVP PS Noise 0.30 0.30 0.14 0.14 0.24 0.24
Total 5.30 0.38 10.67 1.74 0.13 3.51 3.78 0.22 6.87

39
Verilog-A vs Schematic simulations
• The Fractional-N jitter simulations were repeated with various
combinations of Verilog-A models or Schematic netlists to determine the
speed impacts as well as the accuracy of the Verilog-A models
DIVR PFD CP LF VCO CML2CMOS DIVP FBDIV
Configuration Name
config_pm_cm_vm VerilogA VerilogA VerilogA Sch VerilogA VerilogA VerilogA VerilogA
config_pm_cs_vm VerilogA VerilogA Sch Sch VerilogA VerilogA VerilogA VerilogA
config_pm_cs_vs VerilogA VerilogA Sch Sch Sch VerilogA VerilogA VerilogA
config_ps_cs_vm VerilogA Sch Sch Sch VerilogA VerilogA VerilogA VerilogA
config_ps_cs_vs VerilogA Sch Sch Sch Sch VerilogA VerilogA VerilogA
config_pm_cm_vm VerilogA VerilogA VerilogA VerilogA Sch VerilogA VerilogA VerilogA
Sim Duration CPU Time Used Peak Memory Frac Jitter Sim Settings
adexl_frac_n_pm_cm_vm 15us 9350 sec 0.5 Gb 416 fs Conservative, APS
adexl_frac_n_pm_cm_vs 15us 120000 sec 0.57 Gb Sim Failed Conservative, APS
adexl_frac_n_pm_cs_vm 15us 147000 sec 0.35 Gb 446 fs Conservative, APS
adexl_frac_n_ps_cs_vm 15us 194000 sec 0.40 Gb 489 fs Conservative, APS
adexl_frac_n_pm_cs_vs 15us 358000 sec 0.76 Gb 401 fs Conservative, APS (14.8-15us)
adexl_frac_n_ps_cs_vs 15us 496368 sec 0.78 Gb 465 fs Conservative, APS (14.8-15us)
› All simulations are within the measurement accuracy due to finite time-steps
› The all Verilog-A simulations took 2.6 hours, the one with critical blocks run as
schematics took over 50 times longer, at 5.7 days

40
SSC Co-Simulations
• Using the AMS simulator, instantiate the SSC and Sigma-Delta RTL with the
LCPLL Loop schematic
› The SSC generator is very configurable, this simulation was set for Fssc~31 kHz
and ~4800 ppm frequency deviation.

41
Design Trade-Off Summary
• PPA – Power/Performance/Area
• Power: Not much of a concern for LC-Tank based design. Feedback
Divider and 5 GHz clock tree are naturally power hungry.
• Performance: Low bandwidth (1 MHz) PLL Loop rejects incoming
phase noise which is one of the two dominate noise sources in the
design.
• Area: Low bandwidth requires large loop filter capacitor.
• Other design considerations
• LC-Tank can have a large Kvco, need to balance Kvco/Loop Gain with
stability needs, bandwidth requirements and loop filter size
• LC-Tank vs Ring-Osc
• Without a very clean input reference, low PLL loop bandwidth is required.
VCO noise is a high-pass response, so unless the VCO is very low noise it
will create excessive jitter.
• SSC/Fractional-N requirements constrain charge-pump currents and
loop-filter sizes, see slides 19-28.

42
Fractional-N/Sigma-Delta behavior
• When used in Fractional-N Mode, the feedback divider divide ratio is modulated
at the reference clock rate using a second-order sigma-delta modulator to
‘whiten’ the noise. Optional dither can also be added to prevent tones which
may be present for certain combinations of reference clock and VCO clock rates.
• The primary use case uses a 240 MHz reference clock and a 5 GHz VCO clock,
below is a histogram of the divide ratio.

43
Effects of offset on pfddelay induced jitter
• 100 run Monte-Carlo at TT to examine the jitter that might arise from
extra delay in the pfd reset loop due to mismatch.
• Done with a 250 MHz reference at 5 GHz to remove Fractional-N Jitter
› Minimum Delay
› m_jitter = 23.8fs
› s_jitter = 21.7fs
› Minimum Delay
› m_jitter = 22.8fs
› s_jitter = 10.7fs

44
Closed-Loop Stability
• To ensure that model parameters align with actual schematic
performance and to check for any significant deviation from the linear
model loop analysis we have performed a phase-step response
simulation with the Verilog-A model as well as a full schematic netlist.
• The simulation conditions are as follows:
• cfgrcp<2:0>=3 (Nominal biasing)
• icpdac<2:0>=2 (Icp=14.5 uA typical)
• Fvco=5.0 GHz, Fref=250 MHz (allows integer mode operation)
• lf_ctune<1:0>=1
• lf_rtune<2:0>=1
• pfddelay<3:0>=3
• varcm1/varcm2/dcmodevar<3:0>=5,6,7
• Over all 23 PVT Corners x 3 Inductor Corners = 69 Total simulations
• Two configurations were tested, one with Verilog-A models for the feedback
divider and PFD (config_mixed1) and all schematics (config_sch)

45
Spectre/Verilog-A Closed Loop Phase Step Simulation
• Primary Use Case
• All combinations of Kvco, Icp, Resistor and Capacitor Variation
• Apply 90 deg phase step and ensure no ringing
• s40usb40phy_pll_sys_sim/tb_lcpll_loop/adexl_ph_step

46
Spectre/Schematic Closed Loop Phase Step Simulation
• Repeat Primary Use Case over all 69 PVT combinations
• Apply 90 deg phase step and ensure no ringing
› Y-Axis is phase error, in
radians
› The corner with the largest
over/under-shoot is
FF_HR_HOT/TTIND

47
Spectre/Schematic Closed Loop Jitter Simulation (SS/FFIND
• Repeat Primary Use Case at Typical/Fast/Slow corners
• Ran 3us at moderate errpreset, dual-cores, simulation
took >3day

48
Spectre/Schematic Closed Loop Jitter Simulation (Cont)
• Looking at absolute jitter, ~380 fSec (SS/FFIND)

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