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PHASE LOCKED LOOP FOR GSM 900

The document outlines the design of a phase locked loop (PLL) for GSM 900 specifications, detailing key parameters such as input frequency, supply voltage, and output frequency range. It includes simulations and schematics for various components like the phase frequency divider and charge pump, as well as completed tasks such as DRC and LVS checks. Future work involves completing the overall layout and post-layout simulations.

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Submitted by: Chirag Patel Ravi Vachhani Vijay Sankar DESIGN OF A PHASE LOCKED LOOP FOR GSM 900
Specifications: Input Frequency: 200 – 220 MHz Supply Voltage: 3.3V DC Technology used: 0.25 μm CMOS Output Frequency Range: 800 - 900 MHz Settling Time: <10us
General block diagram A Phase Locked loop (PLL) is a system which generates an output signal which is synchronized in frequency and phase to an input signal.
Phase Frequency Divider schematic
PFD SIMULATION Case 1 :Ref2 leading Ref 1
PFD SIMULATION Case 2 : Ref 1 leading Ref 2
PFD SIMULATION Case 3 : In phase response
Charge Pump- Schematic
Charge Pump Simulation
Frequency Divider ( by 4) Schematic
Frequency Divider ( by 4)
VCO LC Oscillator
VCO Tuning Range
VCO Output
PLL
PLL Output
Layout
Things done : Schematics, Simulation and Layout of all individual blocks. DRC and LVS of all blocks. Things to do : Complete Layout of the entire system. LVS of the entire system Post Layout simulation
References [1] D.K. Shaeffer, A.R. Shahani, S.S. Mohan, H.Samavati, H.R. Rateh, M. Del Mar Hershenson, M. Xu, C.P, Yue, D.J. Eddleman, and T. Lee, “ A 115mW, 0.5-um CMOS GPS receiver with wide Dynamic-Range Active Filters, “ IEEE J. Solid-State Circuits, Vol.33, No.12, pp. 2219-2231, December 1998 [2] R.Best,&quot;Phase-Locked Loops&quot;, McGrawHill. [3] B.Razavi, &quot;Design of Analog CMOS Integrated Circuits&quot;, McGraw- Hill. [4] F. M. Gardner, &quot;Charge pump phase locked loops&quot; IEEE trans. on communications, Vol. COM-28, NO.11, Nov 1980. [5] Youngmin Kim, Bo Zhai and Byungwok Min, &quot;Frequency Synthesizer for GPS Radio Application&quot;.[6] Jenkin Chan, Vivian Lee, Amar Basu, “A 1.573-GHz Low power, Wide Locking Range GPS Frequency Synthesizer in 0.18-um CMOS”.

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PHASE LOCKED LOOP FOR GSM 900

  • 1.
    Submitted by: ChiragPatel Ravi Vachhani Vijay Sankar DESIGN OF A PHASE LOCKED LOOP FOR GSM 900
  • 2.
    Specifications: Input Frequency: 200 – 220 MHz Supply Voltage: 3.3V DC Technology used: 0.25 μm CMOS Output Frequency Range: 800 - 900 MHz Settling Time: <10us
  • 3.
    General block diagramA Phase Locked loop (PLL) is a system which generates an output signal which is synchronized in frequency and phase to an input signal.
  • 4.
  • 5.
    PFD SIMULATION Case1 :Ref2 leading Ref 1
  • 6.
    PFD SIMULATION Case2 : Ref 1 leading Ref 2
  • 7.
    PFD SIMULATION Case3 : In phase response
  • 8.
  • 9.
  • 10.
    Frequency Divider (by 4) Schematic
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
    Things done :Schematics, Simulation and Layout of all individual blocks. DRC and LVS of all blocks. Things to do : Complete Layout of the entire system. LVS of the entire system Post Layout simulation
  • 19.
    References [1] D.K.Shaeffer, A.R. Shahani, S.S. Mohan, H.Samavati, H.R. Rateh, M. Del Mar Hershenson, M. Xu, C.P, Yue, D.J. Eddleman, and T. Lee, “ A 115mW, 0.5-um CMOS GPS receiver with wide Dynamic-Range Active Filters, “ IEEE J. Solid-State Circuits, Vol.33, No.12, pp. 2219-2231, December 1998 [2] R.Best,&quot;Phase-Locked Loops&quot;, McGrawHill. [3] B.Razavi, &quot;Design of Analog CMOS Integrated Circuits&quot;, McGraw- Hill. [4] F. M. Gardner, &quot;Charge pump phase locked loops&quot; IEEE trans. on communications, Vol. COM-28, NO.11, Nov 1980. [5] Youngmin Kim, Bo Zhai and Byungwok Min, &quot;Frequency Synthesizer for GPS Radio Application&quot;.[6] Jenkin Chan, Vivian Lee, Amar Basu, “A 1.573-GHz Low power, Wide Locking Range GPS Frequency Synthesizer in 0.18-um CMOS”.