one of the famous Silicon Valley golden rules which state “Higher the clock frequency, Greater the power consumption”. Digging deep into deep submicron CMOS technology, there are design and power management challenges present for Analog and Mixed Signal devices such as PLL and it is very much important to optimize PLL to create a successful and power optimized system. Here, ALF CP PLL is designed in a way that it can operate on low supply voltage but with a 20% reduction in the overall power consumption. The PLL output frequency can be tuned from 80 MHz to 330 MHz and at 350 MHz PLL consumes 190μW at 1V of supply.
The MOSFET is an important element in embedded system design which is used to control the loads as per the requirement. The MOSFET is a high voltage controlling device provides some key features for circuit designers in terms of their overall performance.
The MOSFET is an important element in embedded system design which is used to control the loads as per the requirement. The MOSFET is a high voltage controlling device provides some key features for circuit designers in terms of their overall performance.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
introduction, types & structure of MOSET ,turn ON and OFF of device, working, I-V characteristics of MOSFET,Different regions of operations,applications, adv & disadvantages
DESIGNING PHASE FREQUENCY DETECTOR USING DIFFERENT DESIGN TECHNOLOGIESIAEME Publication
This paper presents the designs of phase frequency detector. The simulation results are focused on accounting the frequency operation, power dissipation and noise. The various PFDs are designed using 0.35 m CMOS technology on SPICE simulator with 3.3V supply voltage. The transfer curve of the different logic designed PFDs shows that the mentioned designs are dead zone free. In the first section, a basic introduction ab out phase locked loop and the importance of PFD is discussed. In the second section, a brief description about the different logic designs used in this paper is given. Subsequently, in the third section, simulation results of various models optimized are observed, explained and finally based on these observations results have been concluded at the end.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
introduction, types & structure of MOSET ,turn ON and OFF of device, working, I-V characteristics of MOSFET,Different regions of operations,applications, adv & disadvantages
DESIGNING PHASE FREQUENCY DETECTOR USING DIFFERENT DESIGN TECHNOLOGIESIAEME Publication
This paper presents the designs of phase frequency detector. The simulation results are focused on accounting the frequency operation, power dissipation and noise. The various PFDs are designed using 0.35 m CMOS technology on SPICE simulator with 3.3V supply voltage. The transfer curve of the different logic designed PFDs shows that the mentioned designs are dead zone free. In the first section, a basic introduction ab out phase locked loop and the importance of PFD is discussed. In the second section, a brief description about the different logic designs used in this paper is given. Subsequently, in the third section, simulation results of various models optimized are observed, explained and finally based on these observations results have been concluded at the end.
AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM ...VLSICS Design
This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211miliwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology.
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...VLSICS Design
A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL...Editor IJCATR
The Phase Frequency Detectors (PFD’s) are
proposed in this research paper by using the
two different structures of D Flip-Flop that is
the traditional D Flip-Flop and modified D
Flip-Flop with a NAND gate which can
overcome the speed and area limitations of the
conventional PFD. Both of the PFD’s use 20
transistors. The traditional PFD consumes
133.92 μW power when operating at 40 MHz
frequency with 1.8 Volts supply voltage
whereas the modified PFD consumes 100.51
μW power operating at 40 MHz frequency with
1.8 Volts supply voltage. The designs are
implemented by using 0.18 meter CMOSprocess in Tanner 13.ov. These can be used in
PLL for high speed applications
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE...IJERA Editor
The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since
this is the only signal which has the highest switching activity. Normally for a multiband clock domain network
we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase
clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide
band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed
which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of
6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of
frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible
divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW.
This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE
802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology.
This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized
using „Xilinx ISE 10.1‟.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
Design and Analysis of Second and Third Order PLL at 450MHzVLSICS Design
Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth.
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology VLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi
gigahertz communication systems such as optical data links, wireless products, microprocessor &
ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core
of a microprocessor, which includes the largest power density on the microprocessor. In an effort to
reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of
dynamic and static power consumption. Lowering the supply voltage, however, also reduces the
performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available
in some application domains, is to replicate the circuit block whose supply voltage is being reduced in
order to maintain the same throughput .This paper introduces a design aspects for low power phase
locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process
technology parameters, which in turn offers high speed performance at low power. The main novelty
related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect
dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit
parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,
translation onto silicon, CAD, practical experience in layout design
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
As Technology progress deeper into submicron
CMOS, traditional analog circuits face problems that are
not to be solved purely by analog innovations. Instead,
new architectures are being proposed which take advantages
of the relatively cheaper of the digital circuits to augment or
improve the diminishing performance of the analog
circuitry. The conventional approach performs the design of
14 bands CMOS frequency synthesizers with spur reduction
for MB-OFMD for analog circuits which have high
distortions and noise. My proposed work is to replace the
analog input PLL into All Digital PLL with spur reduction.
Then the frequency mixing architecture alleviates
harmonics mixing and pulling to diminish spur
generation. The simulation is performed using Model SIM
and the implementation using Microwind to diminish spur
reduction.
Efficient Method of Power Saving Topologically-Compressed With 21Transistor’s...IJMTST Journal
The increasing market trends of extremely low power operated handy applications like laptop, electronic gadgets etc requires microelectronic devices with low power consumption. It is obvious that the transistor dimensions continues to shrink and as require for more complex chips increases, power management of such deep sub-micron based chip is one of the major challenges in VLSI industry. The manufacturers are always targeting for low power designs for the reason that to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression technique, merger of logically equivalent transistors to an eccentric latch structure. Fewer transistors, only three, connected to clock signal which reduces the power drastically, and the smaller total transistor count assures to retain the chip area as conventional FFs. In addition, fully static full-swing operation makes the cell lenient of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are expendable with proposed FF while preserving the same system performance and layout area. The performance of this paper is evaluated on the design simulation using HSPICE simulator.
Dual Edge Triggered Phase Detector for DLL and PLL ApplicationsIJERA Editor
An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional designs and can be operated at a frequency range of 250MHz to 1GHz.The proposed DET-PD is designed using 180nm CMOS process technology at a 1.8V supply voltage in cadence virtuoso and circuit simulated in cadence spectre.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
1. Presented By: Dhwani P. Sametriya
141060752015
Guided By: Dr. Sandeep Aggarwal
Visiting Faculty, C-DAC
Design of Low Voltage High Frequency PLL using
ALF Charge Pump
2. • Objective
• Motivation
• Phase Locked Loop
• Literature Review
• Existing Design and Phase I
• Proposed Design and Design Specifications
• Implementation
• PLL Testing
• Conclusion & Future work
• Time Line
• References
List of Content
3. To achieve a power efficient design of Phase Locked Loop (PLL) operating on low
supply voltage in 90 nm CMOS technology.
Objective
4. • The need of power efficient, compact and reliable devices has
increased.
• Whether at the system or system-on-chip or any MCU or MPU, PLL
are ubiquitous in the same design to address such issues as clock
generation and recovery, clock distribution, jitter and noise reduction
and frequency synthesis for various applications.
Motivation
6. No. Research Paper
Publishing
Year
Key Points
1 Charge-Pump Phase-Lock Loops 1980
Introduction of Charge pump in PLL design
with passive loop filters to reduce ripples in
final output.
2
A High Speed and Low Power
Phase-Frequency Detector and
Charge – pump.
1999
High Speed Low Power PFD based on TSPC
Edge positive triggered D Flip-Flop.
3
A 0.5-V 1.9-GHz Low-Power
Phase-Locked Loop in 0.18-μm
CMOS.
2007
ULV PLL is designed in 0.18 μm CMOS
Technology for low power and low voltage
applications with different techniques.
4
A 0.5-V 0.4–2.24-GHz
Inductorless Phase-Locked Loop
in a System-on-Chip.
2011
Low voltage High Speed PLL based LV-VCO
for low voltage and power and LV-SCM for
High Speed Operation is proposed.
5
Scaling Analog Circuits into deep
nanoscale CMOS: Obstacles and
ways to overcome them
2015
Recent CMOS Scaling references and
understanding of analog VDD.
Literature Review
9. Initial Requirements and Architecture
Selection
Individual Building Block design and
simulation process
Integration of building blocks and Final
system simulation
10. Design Specification
Parameter Value
Technology 90 nm CMOS
Supply Voltage (VDD) 1V
Reference Frequency (fref) 5 MHz ~ 21 MHz
VCO Gain (Kvco) 483 MHz/V
CP Current (Icp) 20 μA
Output Frequency (fvco) 90 MHz ~ 350 MHz
VCO Type Ring
Divider Stage 16
12. • X-OR based Phase Detector is not able to detect low frequency
signals which leads the loop into dead zone.
• D-FF based PFD provides zero or minimum dead zone and
efficiently detects small phase differences of high frequencies in
PLL.
Why D-FF PFD..?
17. • At low supply voltage, Single Ended Charge Pump with Passive
Loop Filter faces current mismatch (source and drain current)
and voltage headroom.
• two stacked transistor method is used in differential CP.
• An Op-Amp with high slew rate is used as negative feedback in
design to reduce burden of differential CP.
• Active Loop Filter isolates Vcp from Vcntrl to avoid ripples in
Vcntrl and provide PLL a dynamic behavior.
Why ALF Charge Pump ..?
22. • LC-VCO has narrow tuning range, greater power consumption
and large die area and it is difficult to integrate inductor in CMOS
process.
• Ring VCO consists of differential delay cells which can be easily
integrated on chip and occupies comparatively less area.
• Even number of differential delay cells are used to achieve 50%
duty cycle and to easily initiate oscillation.
Why Ring VCO ..?
27. • FD operates at High Frequency VCO output, as a result FD
consumes almost half of the power consumed by PLL.
• TSPC FD uses dynamic latches which allow higher frequency of
operation, while minimizing power consumption with reduced
number of transistors.
Why Frequency Divider ..?
34. As PLL is a feedback system, transfer function of Designed PLL
is as follows:
Feedforward gain = G(s) =
Kd∗Kv∗Z 𝑠
𝑠
Feedback gain = H(s) =
1
𝑁
Loop gain = G(s)*H(s) =
Kd∗Kv∗Z 𝑠
𝑠∗𝑁
Closed Loop Gain of PLL:
𝐺(𝑠)
1+𝐺(𝑠)𝐻(𝑠)
=
𝐾𝑑∗𝐾𝑣∗𝑁∗𝑍(𝑠)
𝑠∗𝑁+𝐾𝑑∗𝐾𝑣∗𝑍(𝑠)
36. • It is essential for PLL to provide accurate and glitch-free clock
signals for target application.
• As a consequence, PLL’s functionality needs to be verified
during design and debug process and also through production
testing.
Need of PLL Testing
37. • Following test specifications need to be considered while
performing testing of ALF CP PLL :
1) Lock Time
2) Phase Error
3) Loop Bandwidth
ALF CP PLL Test Specifications
38. • SIMULINK is used to investigate the dynamic behaviour of a
complex system such as PLL and this can be done by
developing processes to manipulate system building blocks on a
palate. SIMULINK performs all three operations: pre-processing,
simulation and post processing in one package.
SIMULINK Simulation
41. Besides of exploring PLL and its components in unprecedented
depth in terms of logic and operation, by designing, simulating and
testing the proposed ALF Charge Pump LVPLL in 90nm CMOS
technology I was able to minimize the average power consumption
at 1 volt as represented in the graph which is the pictorial
representation of scaled statistics and comparison with existing
leading PLL design as mentioned in the references.
Conclusion
42.
43. After successful software simulation of proposed ALF CP PLL,
Layout and FPGA prototype of proposed PLL will be designed for
physical simulation.
Future Work
44. Time Line
= Completed
AUGUST – SEPTEMBER
Phase 0
Problem Statement and Guide Allocation
Study of industrial parameters effects on different architectures
of Charge Pump
Literature Survey and Review
OCTOBER - NOVEMBER
Phase 1
Working on Basic Building Blocks of PLL and CMOS 45 nm
Technology
Software Implementation of PFD and Charge Pump
Study of VCO and Frequency Divider in PLL
3rd
Semester Final Theory and Practical Examination
DECEMBER - JANUARY
Phase 2
Study of Design Challenges
Software Implementation of PFD,ALF CP,VCO,FD
Dissertation Phase – I
Research Paper Start up
FEBRUARY – MARCH
Phase 3
Integration of all the individual blocks and PLL Testing
Research Paper Start up
APRIL - MAY
Phase 4
Mid Semester Review
Conclusion & Completion of Research
Completion of Thesis
MAY - JUNE
Phase 5 Dissertation Phase – II & Poster Presentation
45. References
1. J. Stephen Brugler and Paul G.A. Jaspers,” Charge Pumping in MOS Devices”, in IEEE Transaction on Electron
Devices, vol. 16,no. 3,pp. 297 – 302, March 1969.
2. Guido Groeseneken and Herman E. Maes, “Basics and Applications of Charge Pumping in Submicron MOSFET's”, in
21st International Conference on Microelectronics, vol. 2, pp. 581-589, 14-17 Sept. 1997.
3. Jieh-Tsorng Wu, “MOS Charge Pumps for Low-Voltage Operation”, in IEEE Journals of Solid-State Circuits, vol. 33, no.
4, April 1998.
4. Floyd M. Gardner, “Charge Pump Phase Looked Loops”, IEEE Transaction on Communication, vol. Com-28, no. 11,
November 1980.
5. Vassilis Kalenteridis, Konstantinos Papathanasiou, Stylianos Siskos. Analysis and Design of Charge Pumps for
Telecommunication Applications. Christian Piguet; Ricardo Reis; Dimitrios Soudris. VLSI-SoC: Design Methodologies for
SoC and SiP, 313, Springer, pp.43-60, 2010, IFIP Advances in Information and Communication Technology, 978-3-642-
12266-8.
6. Kuo-Hsing Cheng,Yu-Chang Tsai, Yu-Lung Loand Jing-Shiuan Huang,” A 0.5-V 0.4–2.24-GHz Inductorless Phase-
Locked Loop in a System-on-Chip”, in IEEE Transaction on Circuit and Systems – I, vol. 58, no. 5,pp. 849 – 859, May
2011.
7. Joung-Wook Moon, Kwang-Chun Choi and Woo-Young Choi, “A 0.4-V, 90 ~350-MHz PLL With an Active Loop-Filter
Charge Pump”,in IEEE Transaction on Circuit and Systems – II, vol. 61, no. 5,pp. 319 – 323, May 2014.
8. Chris Auth, Mark Buehler, Annalisa Cappellani, Chi-hing Choi, Gary Ding,Weimin Han, Subhash Joshi, Brian McIntyre,
Matt Prince, Pushkar Ranade, Justin Sandford and Christopher Thomas,” 45nm High-k+Metal Gate Strain-Enhanced
Transistors”, in the Intel Technology Journal, vol. 2, no. 2, 2008.
9. Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi,” Design and test challenges in Nano-scale analog and mixed
CMOS technology”, in International Journal of VLSI design & Communication Systems (VLSICS),vol.2, no.2, June 2011
46. 10. Keilu Shu, “CMOS PLL Synthesizers: Analysis and Design”, Springer Science + Business Media Inc., 2005.
11. Dean Banerjee, PLL Performance, Simulation and Design, 4th Edition, Dog Ear Publishing, 2006.
12. Jitter in PLL-Based Systems: Causes, Effects, and Solutions, Cypress semiconductors Corporation white paper database,
ISBN - 408-943-2600.
13. Won - Hyo Lee, Jun - Dong Cho and Sung - Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge
–pump”, inIEEE Proceedings of the ASP-DAC '99. Asia and South Pacific, vol.1, pp. 269 – 272, April 1999.
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