This document discusses the design and operation of an all-digital phase locked loop (ADPLL). It covers topics such as the digitally controlled oscillator (DCO) core design, noise modeling in the ADPLL, tuning the ADPLL for GSM, impairments like capacitor mismatch and compensation techniques.
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
Digital Signal Processing[ECEG-3171]-Ch1_L03Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
Digital Signal Processing[ECEG-3171]-Ch1_L03Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
C2 discrete time signals and systems in the frequency-domainPei-Che Chang
Discrete-Time Signals and Systems in the Frequency-Domain
Discrete-Time Fourier Transform
time domain convolution theorem
frequency domain convolution theorem
Z transform
Digital Signal Processing[ECEG-3171]-Ch1_L02Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced
#Africa#Ethiopia
Sampling is a Simple method to convert analog signal into discrete Signal by using any one of its three methods
if the sampling frequency is twice or greater than twice then sampled signal can be convert back into analog signal easily......
The presentation gives basic insight into Information Theory, Entropies, various binary channels, and error conditions. It explains principles, derivations and problems in very easy and detailed manner with examples.
C2 discrete time signals and systems in the frequency-domainPei-Che Chang
Discrete-Time Signals and Systems in the Frequency-Domain
Discrete-Time Fourier Transform
time domain convolution theorem
frequency domain convolution theorem
Z transform
Digital Signal Processing[ECEG-3171]-Ch1_L02Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced
#Africa#Ethiopia
Sampling is a Simple method to convert analog signal into discrete Signal by using any one of its three methods
if the sampling frequency is twice or greater than twice then sampled signal can be convert back into analog signal easily......
The presentation gives basic insight into Information Theory, Entropies, various binary channels, and error conditions. It explains principles, derivations and problems in very easy and detailed manner with examples.
On Chip Calibration And Compensation Techniques (11 03 08)imranbashir
The advent of CMOS technology in RF integrated circuits has lead to integration. A practical manifestation of such SoC is DRP, a solution engineered at Texas Instruments Inc. in which digital baseband has been integrated with a RF transceiver all in CMOS technology. A logical step forward in use of such technology is to harness the power of the digital architecture and the baseband in implementing innovative solutions to enhance radio performance over corner conditions and mitigate interferences arising as a result of integration. This research focuses on five practical examples of software solutions for common challenges in DRP.
Sending multimedia data (e.g. data, image and
video) using Power Line Communications (PLC) has been growing
significantly. In fact, impulsive noise (IN) causes significant
degradation which restricts communication performance in PLC.
In this paper, we propose to study the impact of IN on image
communication in Orthogonal Frequency Division Multiplexing
(OFDM) based PLC. A strightforward conventional iterative
IN reduction algorithm, presented in [9] can be applied to
improve bit-error rate (BER) in OFDM system. But, this iterative
algorithm is insufficient to improve the visual quality Peak Signalto-
Noise Ratio (PSNR) performance in image communication.
First, we study its performance in terms of BER and PSNR using
a convolutional encoder (CE). Then, we modify its concept by
introducing CE and Viterbi decoder into the iterative algorithm.
Finally, we aim to show the impact of BER degradation on
visual quality PSNR performance of the reconstructed image.
Our results lay out that the proposed method provides good
PSNR and visual quality improvement than the conventional
algorithm with and without CE.
A Technique for Dynamic Range Improvement of Intermodulation Distortion Produ...Pete Sarson, PH.D
This paper describes a phase switching algorithm for Interpolating Digital-to-Analog Converter (DAC) based Arbitrary Waveform Generators (AWG). This was possible by using the standard phase switching algorithm with the addition of simple phase offset and systematic phase difference adjustment; this was discovered by experimenting with suppression of the intermodulation distortion (IMD) components of a two-tone signal. In this case, we examine the 3rd, 5th and 7th order IMD tones and the effect of the phase switching algorithm and phase shift has on the AWG by measurement with a digitizer. Then we show what the effect of the developed two-tone phase switching technique has upon the performance measurement of a 16-bit Analog-to-Digital Converter (ADC). It is shown that using the original algorithm, no improvement could be achieved for the odd order IMD products. However, by using an even order suppression technique (another phase difference) with a phase shift, a suppression was achieved compared to the standard two-tone signal generation (without phase switching). We show how this technique allows the use of a low-cost tester resource to test IMD products with a higher dynamic range than was previously possible.
This Analog Communication Lab Manual is prepared for JNTU, Hyderabad (in a general way to be utilized for the maximum institutions) for R18 regulation.
Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEsPete Sarson, PH.D
This paper describes how using a phase switching technique can produce a low distortion signal from an Arbitrary Waveform Generator (AWG), and how this technique aligns the performance of the AWGs between testers, to evaluate the Total Harmonic Distortion (THD) performance of Analogue-to-Digital Converters (ADCs). Once a device has been characterized and correlated to the bench, the test engineer needs to start the release procedure in getting the device into a production ready state. One major issue that a test engineer faces is the difference in ADC THD performance test results using the same Automated Test Equipment (ATE) manufacture testers (AWGs). This paper will then show how the Gauge Repeatability and Reproducibility (GRR) between testers can be produced more easily allowing less stringent guard-bands to guarantee the performance of those devices that have performance criteria close to the device specification. This work will also go some way to proving previous papers’ works on distortion shaping testing to enhance the spectral performance of Arbitrary Waveform Generators.
8. DCO ΣΔ : Design Considerations Composite ΣΔ Noise ↑, N ↑ , M ↓ , TB size ↑, f CLK ↓ Critical parameters: M, CLK, N, δ C -> Δ f Due to resolution of digital input (M) Due to size of capacitor Δ f Reference [3] - Bogdan Staszewski, Chih-Ming Hung
9. DCO ΣΔ : Design Considerations Effect of SD order (N) M = 10, Δ f = 30kHz, f CLK = 450MHz N = 1 N = 2 N ↑ , L SD,M Х , L SD, Δ f lower between 1-10M & higher @ 100MHz Composite response (solid black line) DOES NOT include natural DCO phase noise!
10. DCO ΣΔ : Design Considerations Effect of Fractional Word Length (M) N = 2, Δ f = 30kHz, f CLK = 450MHz M = 2 M = 10 Composite response (solid black line) DOES NOT include natural DCO phase noise! M ↑ , L SD,M ↑ , L SD, Δ f X, Current consumption ↑
11. DCO ΣΔ : Design Considerations Effect of Capacitor Size ( Δ f) M = 10, N = 2, f CLK = 450MHz Δ f = 10kHz Δ f = 30kHz Δ f ↑ , L SD,M ↑ , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
12. DCO ΣΔ : Design Considerations Effect of ΣΔ Clock ( f CLK ) M = 10, N = 2, Δ f = 30kHz f CLK = 225MHz f CLK = 450MHz f CLK ↑ , L SD,M X , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
57. DCO Gain Calibration & Compensation Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)
60. TDC Calibration & Compensation Error needs to be within ±2% to meet 3 RMS phase-error spec.
61.
62. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset
63.
64. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.
65.
66. DCO Frequency Calibration & Compensation The allocated time for ADPLL lock may not be adequate given DCO center frequency variation.
67.
68.
69. Noisy/Defective vs. Normal DCO PTE is determined based on PHE based estimation of DCO noise. References [5] - Oren Eliezer, Imran Bashir
70. Block Diagram for Cap. Test DCO phase capacitor toggling time domain PHE waveform H(S) References [5] - Oren Eliezer, Imran Bashir