Pushed by the ever-increasing demand of high-speed connectivity, next generation 400Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits FFE, and allows tuning the output impedance to ensure good source termination. Implemented in 28nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >>2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s, while drawing 120mA only from 1V supply. The power efficiency is ~2 times better than previously reported PAM-4 transmitters.

1. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 1 of 28
A 45 Gb/s PAM-4 Transmitter Delivering
1.3Vppd Output Swing with 1V supply in
28nm CMOS FDSOI
M. Bassi1, F. Radice2,
M. Bruccoleri2, S. Erba3, A. Mazzanti1
1 Università degli Studi di Pavia, Pavia, Italy
2 STMicroelectronics, Cornaredo, Italy
3 STMicroelectronics, Pavia, Italy

2. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 2 of 28
Outline
• Motivation
• PAM-4 vs NRZ for 400G
• Proposed TX Architecture
• High-Swing Voltage Mode Driver
• High-Speed Serializer
• Measurement Results
• Conclusions

3. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 3 of 28
Network Traffic Growth
[Cisco Visual Internet forecast]
• 2.8x traffic growth from 2014 to
2019
• Up to 3.5x in busy-hour time
• Traffic from mobile devices will
exceed the one from wired
devices by 2019
Answer to >25Gb/s interfaces:
• OIF CEI-56G
LR/MR/VSR/XSR/USR roadmap
• IEEE 802.3bs 400GbE task force
(16x25Gb/s or 8x50Gb/s)
[OIF-FD-Client-400G/1T-01.0 White Paper]
Inter-Chassis
Chip to chip interface e.g.
OIC CEI SR/MR IAs
Chip to chip across a Back/Midplane
interface e.g. OIF CEI MR/LR IAs
Chip to Module interface
e.g. OIF CEI VSR IAs
Input/Output to card

4. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 4 of 28
400G Challenges and Opportunities
Challenges
• Gates’ count increase faster than I/O speed
• Power dissipation, rather than technology and routing, mostly limits max
I/O density
• Increasing data rate at > 25Gb/s increases link losses and power
consumption
Possible solutions
• Aggregate channels (WDM)
• Shorten electrical paths to optics
• Use complex modulation schemes
PAM-4 modulation
• Helps maintain loss budget by decreasing Nyquist frequency
• SNR degradation can be recovered by using FEC

5. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 5 of 28
PAM-4 SNR and H Opening
fNyquist = 1/(4Tbit)
Intrinsic H opening = 1.3 [UI]
Eye Amplitude = 1/3
fNyquist = 1/(2Tbit)
Intrinsic H opening = 1 [UI]
Eye Amplitude = 1
• Slight increase in horizontal opening
• Noise power is halved, but eye amplitude reduced by 1/3
High TX output amplitude mandatory to keep high SNR
Tbit 1.3Tbit

6. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 6 of 28
Eye Distortion due to TX Nonlinearity
• Ratio of Level Mismatch (RLM) quantifies PAM-4 eye distortion
• RLM = 3Vmin/Vppd = 80% (picture above) yields:
o 25% reduction in H opening → H opening advantage lost
o 30% reduction in vertical opening @ 10E-6 with 3mVrms noise
• Standard recommends RLM>92%
Vppd
Vmin
RLM = 80%
PAM-4 TX

7. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 7 of 28
Current-Mode Driver
• Theoretical max diff. swing is 4/3(Vdd-Vov)
• Linearity limited by tail current sources
• With Vdd=1V, typically RLM<85%
• Increasing Vdd increases linearity but lower
efficiency
Vdd=1V
Vdd=1.4V
Vdd=1V
Vdd=1.4V

8. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 8 of 28
Voltage-Mode Drivers
• Robust towards non-linear device on-resistance RT
• With RE/Ron>1/1, RLM is better than 96%
• However, matching constraints max swing to VDD

9. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 9 of 28
Swing-Enhanced PAM-4 TX
• Additional currents (1/3Is,2/3Is) injected in the output node
• With Is=3mA, VDD=1V, output swing is raised to 1.3Vppd
• Compared to increasing VDD to 1.3V, 30% better efficiency

10. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 10 of 28
Swing-Enhanced PAM-4 TX
• Driver is transmitting MSB=1 and LSB=1
• Additional current flowing into the load is 𝐼𝐼𝑆𝑆 = 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 + 𝐼𝐼𝐿𝐿𝑆𝑆𝑆𝑆
𝑉𝑉𝐷𝐷𝐷𝐷 + 2𝐼𝐼𝑆𝑆 𝑅𝑅𝐿𝐿
∆𝑉𝑉

11. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 11 of 28
Swing-Enhanced PAM-4 TX
𝑉𝑉𝐷𝐷𝐷𝐷
3
+
2𝐼𝐼𝑆𝑆 𝑅𝑅𝐿𝐿
3
• Driver is transmitting MSB=1 and LSB=0
• Additional current flowing into the load is 𝐼𝐼𝑆𝑆/3 = 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 − 𝐼𝐼𝐿𝐿𝑆𝑆𝑆𝑆
∆𝑉𝑉
3

12. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 12 of 28
TX Replica Bias for Levels Calibration
• Small headroom across current sources when delivering large swing →
linearity impaired and eye still distorted
• Scaled TX replicas employed for current sources calibration
𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 − 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 =
∆𝑉𝑉
6𝑅𝑅𝐿𝐿
𝛼𝛼 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 + 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 =
∆𝑉𝑉
2𝑅𝑅𝐿𝐿
, 𝛼𝛼 < 1

13. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 13 of 28
TX Replica Bias for Levels Calibration
Ensures high linearity even with small
headroom across current sources:
• Without cal: RLM=83%
• With cal: RLM=97%
TX
Replica TX

14. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 14 of 28
TX Driver with FIR
• Multiplexers switch either main tap or delayed data to the driver
• Main tap amplitude always automatically maximized

15. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 15 of 28
Serializer, Driver and Output Network
• Delay ∆T to precisely match 2:1 mux timing
• 5 driver slices for output impedance matching

16. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 16 of 28
Duty Cycle Correction Circuit
• DCD by process mismatches, supply and temperature variation
• Loop can be disabled and controlled manually
DCC Off DCC On

17. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 17 of 28
Output Stage and Network
MSB (4 taps)
LSB (4 taps)5 TX slices
Tap-1 Tap0 Tap1 Tap2
CM driver
SST slices
SST slices
outP
outN

18. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 18 of 28
Output Stage and Network
• 200V MM / 500V CDM, >>2kV HBM ESDs account for 250fF
capacitance each
• Parasitic inductor Ls + asymmetric T-coil enhance bandwidth by 150%
No Network
Ls + T-Coil
+150%

19. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 19 of 28
Test Chip
• 10ML CMOS 28nm FDSOI from STMicroelectronics
• Chips encapsulated in flip-chip BGA packages
• Supply Voltage:1V
• Data Rate: 45Gb/s
• Power: 120mW
• Serializer 60mW
• Replica TX 5mW
• Bias 5mW
• Driver 50mW

20. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 20 of 28
Measurement Setup
• Channel profile includes PCB trace, connector and cable losses
• At the frequency of 12GHz, loss is 6dB

21. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 21 of 28
Differential Output Impedance
• Output impedance can be set with 4Ω precision
• Output return loss inside IEEE802.3bs mask limit
Mask Limit

22. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 22 of 28
Output eyes at 10Gb/s
• Data Rate is 10Gb/s
• FIR disabled
• Swing-enhancing currents improve eye amplitude by 30%
• Output levels calibration loop set (V11,V10,V01,V00) ~
(825mV,610mV,390mV,175mV)
Without Currents With Currents
Amplitude 1Vppd Amplitude 1.3Vppd
diff scale is 85mV/div +10dB attenuator diff scale is 85mV/div +10dB attenuator

23. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 23 of 28
Output eyes at 45Gb/s
• Data Rate is 45Gb/s
• FIR is ON and recovers 6dB at Nyquist
• Swing-enhancing currents improve eye amplitude by 28%
• Output levels calibration loop set (V11,V10,V01,V00) ~
(825mV,610mV,390mV,175mV)
Without Currents With Currents
Amplitude 530mVppd Amplitude 680mVppd
diff scale is 85mV/div +10dB attenuator diff scale is 85mV/div +10dB attenuator

24. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 24 of 28
Boost vs Coefficients
• Each coefficient provides maximum
+/- 6dB boost
• Precision: 5 bits + sign
First Post-Cursor
First Post-Cursor
Second Post-Cursor
First Pre-Cursor
Ideal

25. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 25 of 28
Eye distortion test 1/2
• Test proposed by CEI-56G and IEEE 802.3bs emerging standards
• RLM = 3 min(VB-VA,VC-VD,VD-VC)/(VD-VA)
• At 45Gb/s RLM > 0.92 (spec under discussion) for 20 chip samples
VA
VB
VC
VD
16UI
45Gb/s w/o FIR45Gb/s

26. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 26 of 28
Eye distortion test 2/2
• Equalization by using FFE does not impact RLM
45Gb/s45Gb/s
Without currents With currents

27. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 27 of 28
Summary and comparison
1 Amplitude from picture. Loss recovered by FFE de-embedded.
2 Not including PLL and clock distribution power.
3 Amplitude from picture. Loss recovered by software CTLE de-embedded.

28. 3.6: A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
© 2016 IEEE
International Solid-State Circuits Conference 28 of 28
• High TX pk-to-pk swing and low distortion are key features
for high-speed PAM-4 transmitters
• A hybrid, mostly-SST, 45Gb/s PAM-4 transmitter
architecture is proposed to deliver 1.3Vppd output swing
with 1V supply only
• Calibration through automatic loop ensures low eye
distortion, key requirement for next generation PAM-4
transceivers
• Measurements on more than 20 28nm CMOS FDSOI test-
chips prove the effectiveness of the proposed TX
Conclusions